Cpu.asm 5.8 KB

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  1. TITLE Cpu.asm: Assembly code for the x64 resources
  2. ;
  3. ; This file contains an 'Intel Sample Driver' and is
  4. ; licensed for Intel CPUs and chipsets under the terms of your
  5. ; license agreement with Intel or your vendor. This file may
  6. ; be modified by the user, subject to additional terms of the
  7. ; license agreement
  8. ;
  9. ;
  10. ; Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
  11. ;
  12. ; SPDX-License-Identifier: BSD-2-Clause-Patent
  13. ;
  14. ;
  15. ;
  16. ;
  17. ;
  18. ;* Module Name:
  19. ;*
  20. ;* Cpu.asm
  21. ;*
  22. ;* Abstract:
  23. ;*
  24. ;------------------------------------------------------------------------------
  25. text SEGMENT
  26. ;------------------------------------------------------------------------------
  27. ; VOID
  28. ; EfiHalt (
  29. ; VOID
  30. ; )
  31. ;------------------------------------------------------------------------------
  32. EfiHalt PROC PUBLIC
  33. hlt
  34. ret
  35. EfiHalt ENDP
  36. ;------------------------------------------------------------------------------
  37. ; VOID
  38. ; EfiWbinvd (
  39. ; VOID
  40. ; )
  41. ;------------------------------------------------------------------------------
  42. EfiWbinvd PROC PUBLIC
  43. wbinvd
  44. ret
  45. EfiWbinvd ENDP
  46. ;------------------------------------------------------------------------------
  47. ; VOID
  48. ; EfiInvd (
  49. ; VOID
  50. ; )
  51. ;------------------------------------------------------------------------------
  52. EfiInvd PROC PUBLIC
  53. invd
  54. ret
  55. EfiInvd ENDP
  56. ;------------------------------------------------------------------------------
  57. ; VOID
  58. ; EfiCpuid (
  59. ; IN UINT32 RegisterInEax, // rcx
  60. ; OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx
  61. ; )
  62. ;------------------------------------------------------------------------------
  63. EfiCpuid PROC PUBLIC
  64. push rbx
  65. mov r8, rdx ; r8 = *Reg
  66. mov rax, rcx ; RegisterInEax
  67. cpuid
  68. cmp r8, 0
  69. je _Exit
  70. mov [r8 + 0], eax ; Reg->RegEax
  71. mov [r8 + 4], ebx ; Reg->RegEbx
  72. mov [r8 + 8], ecx ; Reg->RegEcx
  73. mov [r8 + 12], edx ; Reg->RegEdx
  74. _Exit:
  75. pop rbx
  76. ret
  77. EfiCpuid ENDP
  78. ;------------------------------------------------------------------------------
  79. ; UINT64
  80. ; EfiReadMsr (
  81. ; IN UINT32 Index, // rcx
  82. ; )
  83. ;------------------------------------------------------------------------------
  84. EfiReadMsr PROC PUBLIC
  85. rdmsr
  86. sal rdx, 32 ; edx:eax -> rax
  87. or rax, rdx ; rax = edx:eax
  88. ret
  89. EfiReadMsr ENDP
  90. ;------------------------------------------------------------------------------
  91. ; VOID
  92. ; EfiWriteMsr (
  93. ; IN UINT32 Index, // rcx
  94. ; IN UINT64 Value // rdx
  95. ; )
  96. ;------------------------------------------------------------------------------
  97. EfiWriteMsr PROC PUBLIC
  98. mov rax, rdx ; rdx = Value
  99. sar rdx, 32 ; convert rdx to edx upper 32-bits
  100. wrmsr ; wrmsr[ecx] result = edx:eax
  101. ret
  102. EfiWriteMsr ENDP
  103. ;------------------------------------------------------------------------------
  104. ; UINT64
  105. ; EfiReadTsc (
  106. ; VOID
  107. ; );
  108. ;------------------------------------------------------------------------------
  109. EfiReadTsc PROC PUBLIC
  110. rdtsc
  111. shl rax, 32
  112. shrd rax, rdx, 32
  113. ret
  114. EfiReadTsc ENDP
  115. ;------------------------------------------------------------------------------
  116. ; VOID
  117. ; EfiDisableCache (
  118. ; VOID
  119. ; );
  120. ;------------------------------------------------------------------------------
  121. EfiDisableCache PROC PUBLIC
  122. ; added a check to see if cache is already disabled. If it is, then skip.
  123. mov rax, cr0
  124. and rax, 060000000h
  125. cmp rax, 0
  126. jne @f
  127. mov rax, cr0
  128. or rax, 060000000h
  129. mov cr0, rax
  130. wbinvd
  131. @@:
  132. ret
  133. EfiDisableCache ENDP
  134. ;------------------------------------------------------------------------------
  135. ; VOID
  136. ; EfiEnableCache (
  137. ; VOID
  138. ; );
  139. ;------------------------------------------------------------------------------
  140. EfiEnableCache PROC PUBLIC
  141. wbinvd
  142. mov rax, cr0
  143. and rax, 09fffffffh
  144. mov cr0, rax
  145. ret
  146. EfiEnableCache ENDP
  147. ;------------------------------------------------------------------------------
  148. ; UINTN
  149. ; EfiGetEflags (
  150. ; VOID
  151. ; );
  152. ;------------------------------------------------------------------------------
  153. EfiGetEflags PROC PUBLIC
  154. pushfq
  155. pop rax
  156. ret
  157. EfiGetEflags ENDP
  158. ;------------------------------------------------------------------------------
  159. ; VOID
  160. ; EfiDisableInterrupts (
  161. ; VOID
  162. ; );
  163. ;------------------------------------------------------------------------------
  164. EfiDisableInterrupts PROC PUBLIC
  165. cli
  166. ret
  167. EfiDisableInterrupts ENDP
  168. ;------------------------------------------------------------------------------
  169. ; VOID
  170. ; EfiEnableInterrupts (
  171. ; VOID
  172. ; );
  173. ;------------------------------------------------------------------------------
  174. EfiEnableInterrupts PROC PUBLIC
  175. sti
  176. ret
  177. EfiEnableInterrupts ENDP
  178. ;------------------------------------------------------------------------------
  179. ; VOID
  180. ; EfiCpuidExt (
  181. ; IN UINT32 RegisterInEax,
  182. ; IN UINT32 CacheLevel,
  183. ; OUT EFI_CPUID_REGISTER *Regs
  184. ; )
  185. ;------------------------------------------------------------------------------
  186. EfiCpuidExt PROC PUBLIC
  187. push rbx
  188. mov rax, rcx ; rax = RegisterInEax
  189. mov rcx, rdx ; rcx = CacheLevel
  190. cpuid
  191. mov [r8 + 0 ], eax ; Reg->RegEax
  192. mov [r8 + 4 ], ebx ; Reg->RegEbx
  193. mov [r8 + 8 ], ecx ; Reg->RegEcx
  194. mov [r8 + 12], edx ; Reg->RegEdx
  195. pop rbx
  196. ret
  197. EfiCpuidExt ENDP
  198. END