CpuIA32.h 7.5 KB

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  1. /*++
  2. Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. CpuIA32.h
  6. Abstract:
  7. --*/
  8. #ifndef _CPU_IA32_H
  9. #define _CPU_IA32_H
  10. typedef struct {
  11. UINT32 RegEax;
  12. UINT32 RegEbx;
  13. UINT32 RegEcx;
  14. UINT32 RegEdx;
  15. } EFI_CPUID_REGISTER;
  16. typedef struct {
  17. UINT32 HeaderVersion;
  18. UINT32 UpdateRevision;
  19. UINT32 Date;
  20. UINT32 ProcessorId;
  21. UINT32 Checksum;
  22. UINT32 LoaderRevision;
  23. UINT32 ProcessorFlags;
  24. UINT32 DataSize;
  25. UINT32 TotalSize;
  26. UINT8 Reserved[12];
  27. } EFI_CPU_MICROCODE_HEADER;
  28. typedef struct {
  29. UINT32 ExtendedSignatureCount;
  30. UINT32 ExtendedTableChecksum;
  31. UINT8 Reserved[12];
  32. } EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;
  33. typedef struct {
  34. UINT32 ProcessorSignature;
  35. UINT32 ProcessorFlag;
  36. UINT32 ProcessorChecksum;
  37. } EFI_CPU_MICROCODE_EXTENDED_TABLE;
  38. typedef struct {
  39. UINT32 Stepping : 4;
  40. UINT32 Model : 4;
  41. UINT32 Family : 4;
  42. UINT32 Type : 2;
  43. UINT32 Reserved1 : 2;
  44. UINT32 ExtendedModel : 4;
  45. UINT32 ExtendedFamily : 8;
  46. UINT32 Reserved2 : 4;
  47. } EFI_CPU_VERSION;
  48. #define EFI_CPUID_SIGNATURE 0x0
  49. #define EFI_CPUID_VERSION_INFO 0x1
  50. #define EFI_CPUID_CACHE_INFO 0x2
  51. #define EFI_CPUID_SERIAL_NUMBER 0x3
  52. #define EFI_CPUID_EXTENDED_FUNCTION 0x80000000
  53. #define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001
  54. #define EFI_CPUID_BRAND_STRING1 0x80000002
  55. #define EFI_CPUID_BRAND_STRING2 0x80000003
  56. #define EFI_CPUID_BRAND_STRING3 0x80000004
  57. #define EFI_MSR_IA32_PLATFORM_ID 0x17
  58. #define EFI_MSR_IA32_APIC_BASE 0x1B
  59. #define EFI_MSR_EBC_HARD_POWERON 0x2A
  60. #define EFI_MSR_EBC_SOFT_POWERON 0x2B
  61. #define BINIT_DRIVER_DISABLE 0x40
  62. #define INTERNAL_MCERR_DISABLE 0x20
  63. #define INITIATOR_MCERR_DISABLE 0x10
  64. #define EFI_MSR_EBC_FREQUENCY_ID 0x2C
  65. #define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79
  66. #define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B
  67. #define EFI_MSR_PSB_CLOCK_STATUS 0xCD
  68. #define EFI_APIC_GLOBAL_ENABLE 0x800
  69. #define EFI_MSR_IA32_MISC_ENABLE 0x1A0
  70. #define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000
  71. #define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008
  72. #define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004
  73. #define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002
  74. #define FAST_STRING_ENABLE_BIT 0x00000001
  75. #define EFI_CACHE_VARIABLE_MTRR_BASE 0x200
  76. #define EFI_CACHE_VARIABLE_MTRR_END 0x20F
  77. #define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF
  78. #define EFI_CACHE_MTRR_VALID 0x800
  79. #define EFI_CACHE_FIXED_MTRR_VALID 0x400
  80. #define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
  81. #define EFI_MSR_VALID_MASK 0xFFFFFFFFF
  82. #define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000
  83. #define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF
  84. #define EFI_IA32_MTRR_FIX64K_00000 0x250
  85. #define EFI_IA32_MTRR_FIX16K_80000 0x258
  86. #define EFI_IA32_MTRR_FIX16K_A0000 0x259
  87. #define EFI_IA32_MTRR_FIX4K_C0000 0x268
  88. #define EFI_IA32_MTRR_FIX4K_C8000 0x269
  89. #define EFI_IA32_MTRR_FIX4K_D0000 0x26A
  90. #define EFI_IA32_MTRR_FIX4K_D8000 0x26B
  91. #define EFI_IA32_MTRR_FIX4K_E0000 0x26C
  92. #define EFI_IA32_MTRR_FIX4K_E8000 0x26D
  93. #define EFI_IA32_MTRR_FIX4K_F0000 0x26E
  94. #define EFI_IA32_MTRR_FIX4K_F8000 0x26F
  95. #define EFI_IA32_MCG_CAP 0x179
  96. #define EFI_IA32_MCG_CTL 0x17B
  97. #define EFI_IA32_MC0_CTL 0x400
  98. #define EFI_IA32_MC0_STATUS 0x401
  99. #define EFI_IA32_PERF_STATUS 0x198
  100. #define EFI_IA32_PERF_CTL 0x199
  101. #define EFI_CACHE_UNCACHEABLE 0
  102. #define EFI_CACHE_WRITECOMBINING 1
  103. #define EFI_CACHE_WRITETHROUGH 4
  104. #define EFI_CACHE_WRITEPROTECTED 5
  105. #define EFI_CACHE_WRITEBACK 6
  106. //
  107. // Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number
  108. //
  109. #define EfiMakeCpuVersion(f, m, s) \
  110. (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))
  111. /**
  112. Halt the Cpu
  113. @param[in] None
  114. @retval None
  115. **/
  116. VOID
  117. EFIAPI
  118. EfiHalt (
  119. VOID
  120. );
  121. /**
  122. Write back and invalidate the Cpu cache
  123. @param[in] None
  124. @retval None
  125. **/
  126. VOID
  127. EFIAPI
  128. EfiWbinvd (
  129. VOID
  130. );
  131. /**
  132. Invalidate the Cpu cache
  133. @param[in] None
  134. @retval None
  135. **/
  136. VOID
  137. EFIAPI
  138. EfiInvd (
  139. VOID
  140. );
  141. /**
  142. Get the Cpu info by execute the CPUID instruction
  143. @param[in] RegisterInEax The input value to put into register EAX
  144. @param[in] Regs The Output value
  145. @retval None
  146. **/
  147. VOID
  148. EFIAPI
  149. EfiCpuid (
  150. IN UINT32 RegisterInEax,
  151. OUT EFI_CPUID_REGISTER *Regs
  152. );
  153. /**
  154. When RegisterInEax != 4, the functionality is the same as EfiCpuid.
  155. When RegisterInEax == 4, the function return the deterministic cache
  156. parameters by excuting the CPUID instruction.
  157. @param[in] RegisterInEax The input value to put into register EAX.
  158. @param[in] CacheLevel The deterministic cache level.
  159. @param[in] Regs The Output value.
  160. @retval None
  161. **/
  162. VOID
  163. EFIAPI
  164. EfiCpuidExt (
  165. IN UINT32 RegisterInEax,
  166. IN UINT32 CacheLevel,
  167. OUT EFI_CPUID_REGISTER *Regs
  168. );
  169. /**
  170. Read Cpu MSR
  171. @param[in] Index The index value to select the register
  172. @retval Return the read data
  173. **/
  174. UINT64
  175. EFIAPI
  176. EfiReadMsr (
  177. IN UINT32 Index
  178. );
  179. /**
  180. Write Cpu MSR
  181. @param[in] Index The index value to select the register
  182. @param[in] Value The value to write to the selected register
  183. @retval None
  184. **/
  185. VOID
  186. EFIAPI
  187. EfiWriteMsr (
  188. IN UINT32 Index,
  189. IN UINT64 Value
  190. );
  191. /**
  192. Read Time stamp
  193. @param[in] None
  194. @retval Return the read data
  195. **/
  196. UINT64
  197. EFIAPI
  198. EfiReadTsc (
  199. VOID
  200. );
  201. /**
  202. Writing back and invalidate the cache,then diable it
  203. @param[in] None
  204. @retval None
  205. **/
  206. VOID
  207. EFIAPI
  208. EfiDisableCache (
  209. VOID
  210. );
  211. /**
  212. Invalidate the cache,then Enable it
  213. @param[in] None
  214. @retval None
  215. **/
  216. VOID
  217. EFIAPI
  218. EfiEnableCache (
  219. VOID
  220. );
  221. /**
  222. Get Eflags
  223. @param[in] None
  224. @retval Return the Eflags value
  225. **/
  226. UINT32
  227. EFIAPI
  228. EfiGetEflags (
  229. VOID
  230. );
  231. /**
  232. Disable Interrupts
  233. @param[in] None
  234. @retval None
  235. **/
  236. VOID
  237. EFIAPI
  238. EfiDisableInterrupts (
  239. VOID
  240. );
  241. /**
  242. Enable Interrupts
  243. @param[in] None
  244. @retval None
  245. **/
  246. VOID
  247. EFIAPI
  248. EfiEnableInterrupts (
  249. VOID
  250. );
  251. /**
  252. Extract CPU detail version infomation
  253. @param[in] FamilyId FamilyId, including ExtendedFamilyId
  254. @param[in] Model Model, including ExtendedModel
  255. @param[in] SteppingId SteppingId
  256. @param[in] Processor Processor
  257. **/
  258. VOID
  259. EFIAPI
  260. EfiCpuVersion (
  261. IN UINT16 *FamilyId, OPTIONAL
  262. IN UINT8 *Model, OPTIONAL
  263. IN UINT8 *SteppingId, OPTIONAL
  264. IN UINT8 *Processor OPTIONAL
  265. );
  266. #endif