KabylakeRvp3SpdTable.c 29 KB

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  1. /** @file
  2. GPIO definition table for KabylakeRvp3
  3. Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _KABYLAKE_RVP3_SPD_TABLE_H_
  7. #define _KABYLAKE_RVP3_SPD_TABLE_H_
  8. //
  9. // DQByteMap[0] - ClkDQByteMap:
  10. // If clock is per rank, program to [0xFF, 0xFF]
  11. // If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
  12. // If clock is shared by 2 ranks but does not go to all bytes,
  13. // Entry[i] defines which DQ bytes Group i services
  14. // DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB
  15. // DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB
  16. // DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB
  17. // For DDR, DQByteMap[3:1] = [0xFF, 0]
  18. // DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank
  19. // Variable only exists to make the code easier to use
  20. // DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref
  21. // Variable only exists to make the code easier to use
  22. //
  23. //
  24. // DQ byte mapping to CMD/CTL/CLK, from the CPU side - for SKL RVP3, SKL SDS - used by SKL/KBL MRC
  25. //
  26. GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapSklRvp3[2][6][2] = {
  27. // Channel 0:
  28. {
  29. { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
  30. { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
  31. { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
  32. { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
  33. { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
  34. { 0xFF, 0x00 } // CA Vref is one for all bytes
  35. },
  36. // Channel 1:
  37. {
  38. { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
  39. { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
  40. { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
  41. { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
  42. { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
  43. { 0xFF, 0x00 } // CA Vref is one for all bytes
  44. }
  45. };
  46. //
  47. // DQS byte swizzling between CPU and DRAM - for SKL DOE RVP
  48. //
  49. GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramSklRvp3[2][8] = {
  50. { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0
  51. { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1
  52. };
  53. // Samsung K4E6E304ED-EGCF 178b QDP LPDDR3, 4Gb die (256Mx16), x16
  54. // or Hynix H9CCNNNBLTALAR-NUD
  55. // or similar
  56. // 1867, 14-17-17-40
  57. // 2 ranks per channel, 2 SDRAMs per rank, 8x4Gb = 4GB total per channel
  58. GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp16Spd[] = {
  59. 0x24, ///< 0 Number of Serial PD Bytes Written / SPD Device Size
  60. 0x20, ///< 1 SPD Revision
  61. 0x0F, ///< 2 DRAM Device Type
  62. 0x0E, ///< 3 Module Type
  63. 0x14, ///< 4 SDRAM Density and Banks: 8 Banks, 4 Gb SDRAM density
  64. 0x12, ///< 5 SDRAM Addressing: 14 Rows, 11 Columns
  65. 0xB5, ///< 6 SDRAM Package Type: QDP, 1 Channel per die, Signal Loading Matrix 1
  66. 0x00, ///< 7 SDRAM Optional Features
  67. 0x00, ///< 8 SDRAM Thermal and Refresh Options
  68. 0x00, ///< 9 Other SDRAM Optional Features
  69. 0x00, ///< 10 Reserved - must be coded as 0x00
  70. 0x03, ///< 11 Module Nominal Voltage, VDD
  71. 0x0A, ///< 12 Module Organization, SDRAM width: 16 bits, 2 Ranks
  72. 0x23, ///< 13 Module Memory Bus Width: 2 channels, 64 bit channel bus width
  73. 0x00, ///< 14 Module Thermal Sensor
  74. 0x00, ///< 15 Extended Module Type
  75. 0x00, ///< 16 Reserved - must be coded as 0x00
  76. 0x00, ///< 17 Timebases
  77. 0x09, ///< 18 SDRAM Minimum Cycle Time (tCKmin): tCKmin = 1.071ns (LPDDR3-1867)
  78. 0xFF, ///< 19 SDRAM Minimum Cycle Time (tCKmax)
  79. 0xD4, ///< 20 CAS Latencies Supported, First Byte (tCK): 14, 12, 10, 8
  80. 0x00, ///< 21 CAS Latencies Supported, Second Byte
  81. 0x00, ///< 22 CAS Latencies Supported, Third Byte
  82. 0x00, ///< 23 CAS Latencies Supported, Fourth Byte
  83. 0x78, ///< 24 Minimum CAS Latency Time (tAAmin) = 14.994 ns
  84. 0x00, ///< 25 Read and Write Latency Set Options
  85. 0x90, ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
  86. 0xA8, ///< 27 Minimum Row Precharge Delay Time for all banks (tRPab)
  87. 0x90, ///< 28 Minimum Row Precharge Delay Time per bank (tRPpb)
  88. 0x10, ///< 29 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte
  89. 0x04, ///< 30 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte
  90. 0xE0, ///< 31 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
  91. 0x01, ///< 32 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
  92. 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
  93. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
  94. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
  95. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit Mapping
  96. 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit Mapping
  97. 0, 0, ///< 78 - 79
  98. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
  99. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
  100. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
  101. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
  102. 0x00, ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb)
  103. 0x00, ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
  104. 0x00, ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
  105. 0xFA, ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)
  106. 0x7F, ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax): 32.002 ns
  107. 0xCA, ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin): 1.071 ns (LPDDR-1867)
  108. 0x00, ///< 126 CRC A
  109. 0x00, ///< 127 CRC B
  110. 0, 0, ///< 128 - 129
  111. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
  112. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
  113. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
  114. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
  115. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
  116. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
  117. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
  118. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
  119. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
  120. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
  121. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
  122. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
  123. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
  124. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
  125. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
  126. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
  127. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
  128. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
  129. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
  130. 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
  131. 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
  132. 0x00, ///< 322 Module Manufacturing Location
  133. 0x00, ///< 323 Module Manufacturing Date Year
  134. 0x00, ///< 324 Module Manufacturing Date Week
  135. 0x55, ///< 325 Module Serial Number A
  136. 0x00, ///< 326 Module Serial Number B
  137. 0x00, ///< 327 Module Serial Number C
  138. 0x00, ///< 328 Module Serial Number D
  139. 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
  140. 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
  141. 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
  142. 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
  143. 0x00, ///< 349 Module Revision Code
  144. 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
  145. 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
  146. 0x00, ///< 352 DRAM Stepping
  147. 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359
  148. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
  149. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
  150. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
  151. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
  152. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
  153. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
  154. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
  155. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
  156. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449
  157. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
  158. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
  159. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
  160. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
  161. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
  162. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
  163. 0, 0 ///< 510 - 511
  164. };
  165. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp16SpdSize = sizeof (mSkylakeRvp16Spd);
  166. //Hynix H9CCNNNBJTMLAR-NUD, DDP, LPDDR3, 8Gb die
  167. //1867
  168. GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd110[] = {
  169. 0x91, ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
  170. 0x20, ///< 1 SPD Revision
  171. 0xF1, ///< 2 DRAM Device Type
  172. 0x03, ///< 3 Module Type
  173. 0x05, ///< 4 SDRAM Density and Banks, 8Gb
  174. 0x19, ///< 5 SDRAM Addressing: 15 Rows, 10 Columns
  175. 0x05, ///< 6 Module Nominal Voltage
  176. 0x0B, ///< 7 Module Organization: 32 bits, 2 Ranks
  177. 0x03, ///< 8 Module Memory Bus Width
  178. 0x11, ///< 9 Fine Timebase (FTB) Dividend / Divisor
  179. 0x01, ///< 10 Medium Timebase (MTB) Dividend
  180. 0x08, ///< 11 Medium Timebase (MTB) Divisor
  181. 0x09, ///< 12 SDRAM Minimum Cycle Time (tCKmin): tCKmin = 1.071 ns (LPDDR3-1867)
  182. 0x00, ///< 13 Reserved0
  183. 0x50, ///< 14 CAS Latencies supported (tCK): 14, 12, 10, 8 (LSB)
  184. 0x05, ///< 15 CAS Latencies supported (tCK): 14, 12, 10, 8 (LSB)
  185. 0x78, ///< 16 Minimum CAS Latency (tAAmin) = 14.994 ns
  186. 0x78, ///< 17 Minimum Write Recovery Time (tWRmin)
  187. 0x90, ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
  188. 0x50, ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
  189. 0x90, ///< 20 Minimum Row Precharge Delay Time (tRPmin)
  190. 0x11, ///< 21 Upper Nibbles for tRAS and tRC
  191. 0x50, ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
  192. 0xE0, ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
  193. 0x90, ///< 24 Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte
  194. 0x06, ///< 25 Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte
  195. 0x3C, ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
  196. 0x3C, ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
  197. 0x01, ///< 28 Upper Nibble for tFAW
  198. 0x90, ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)
  199. 0x00, ///< 30 SDRAM Optional Features
  200. 0x00, ///< 31 SDRAMThermalAndRefreshOptions
  201. 0x00, ///< 32 ModuleThermalSensor
  202. 0x00, ///< 33 SDRAM Device Type
  203. 0xCA, ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin): 1.071 ns (LPDDR3-1867)
  204. 0xFA, ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)
  205. 0x00, ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
  206. 0x00, ///< 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
  207. 0x00, ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
  208. 0xA8, ///< 39 Row precharge time for all banks (tRPab)
  209. 0x00, ///< 40 FTB for Row precharge time for all banks (tRPab)
  210. 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49
  211. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
  212. 0, 0, ///< 60 - 61
  213. 0x00, ///< 62 Reference Raw Card Used
  214. 0x00, ///< 63 Address Mapping from Edge Connector to DRAM
  215. 0x00, ///< 64 ThermalHeatSpreaderSolution
  216. 0, 0, 0, 0, 0, ///< 65 - 69
  217. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
  218. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
  219. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
  220. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
  221. 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116
  222. 0x00, ///< 117 Module Manufacturer ID Code, Least Significant Byte
  223. 0x00, ///< 118 Module Manufacturer ID Code, Most Significant Byte
  224. 0x00, ///< 119 Module Manufacturing Location
  225. 0x00, ///< 120 Module Manufacturing Date Year
  226. 0x00, ///< 121 Module Manufacturing Date creation work week
  227. 0x55, ///< 122 Module Serial Number A
  228. 0x00, ///< 123 Module Serial Number B
  229. 0x00, ///< 124 Module Serial Number C
  230. 0x00, ///< 125 Module Serial Number D
  231. 0x00, ///< 126 CRC A
  232. 0x00 ///< 127 CRC B
  233. };
  234. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3Spd110Size = sizeof (mSkylakeRvp3Spd110);
  235. //
  236. // Micron MT52L512M32D2PF 78b DDP LPDDR3, 8Gb die (256Mx32), x32
  237. //
  238. GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mKblRSpdLpddr32133[] = {
  239. 0x91, ///< 0 128 SPD bytes used, 256 total, CRC covers 0..116
  240. 0x20, ///< 1 SPD Revision 2.0
  241. 0xF1, ///< 2 DRAM Type: LPDDR3 SDRAM
  242. 0x03, ///< 3 Module Type: SO-DIMM
  243. 0x05, ///< 4 8 Banks, 8 Gb SDRAM density
  244. 0x19, ///< 5 SDRAM Addressing: 15 Rows, 10 Columns
  245. 0x05, ///< 6 Module Nominal Voltage VDD: 1.2v
  246. 0x0B, ///< 7 SDRAM width: 32 bits, 2 Ranks
  247. 0x03, ///< 8 SDRAM bus width: 64 bits, no ECC
  248. 0x11, ///< 9 Fine Timebase (FTB) granularity: 1 ps
  249. 0x01, ///< 10 Medium Timebase (MTB) : 0.125 ns
  250. 0x08, ///< 11 Medium Timebase Divisor
  251. 0x08, ///< 12 tCKmin = 0.938 ns (LPDDR3-2133)
  252. 0x00, ///< 13 Reserved
  253. 0x50, ///< 14 CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (LSB)
  254. 0x15, ///< 15 CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (MSB)
  255. 0x78, ///< 16 Minimum CAS Latency (tAAmin) = 15.008 ns
  256. 0x78, ///< 17 tWR = 15 ns
  257. 0x90, ///< 18 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
  258. 0x50, ///< 19 tRRD = 10 ns
  259. 0x90, ///< 20 Minimum row precharge time (tRPmin) = 18 ns
  260. 0x11, ///< 21 Upper nibbles for tRAS and tRC
  261. 0x50, ///< 22 tRASmin = 42 ns
  262. 0xE0, ///< 23 tRCmin = (tRASmin + tRPmin) = 60 ns
  263. 0x90, ///< 24 tRFCmin = (tRFCab) = 210 ns (8Gb)
  264. 0x06, ///< 25 tRFCmin MSB
  265. 0x3C, ///< 26 tWTRmin = 7.5 ns
  266. 0x3C, ///< 27 tRTPmin = 7.5 ns
  267. 0x01, ///< 28 tFAWmin upper nibble
  268. 0x90, ///< 29 tFAWmin = 50 ns
  269. 0x00, ///< 30 SDRAM Optional Features - none
  270. 0x00, ///< 31 SDRAM Thermal / Refresh options - none
  271. 0x00, ///< 32 ModuleThermalSensor
  272. 0x00, ///< 33 SDRAM Device Type
  273. 0xC2, ///< 34 FTB for tCKmin = 0.938 ns (LPDDR3-2133)
  274. 0x08, ///< 35 FTB for tAAmin = 15.008 ns (LPDDR3-2133)
  275. 0x00, ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
  276. 0x00, ///< 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
  277. 0x00, ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
  278. 0xA8, ///< 39 Row precharge time for all banks (tRPab)= 21 ns
  279. 0x00, ///< 40 FTB for Row precharge time for all banks (tRPab) = 0
  280. 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49
  281. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
  282. 0, 0, ///< 60 - 61
  283. 0x00, ///< 62 Reference Raw Card Used
  284. 0x00, ///< 63 Rank1 Mapping: Standard
  285. 0x00, ///< 64 ThermalHeatSpreaderSolution
  286. 0, 0, 0, 0, 0, ///< 65 - 69
  287. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
  288. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
  289. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
  290. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
  291. 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116
  292. 0x00, ///< 117 Module Manufacturer ID Code, Least Significant Byte
  293. 0x00, ///< 118 Module Manufacturer ID Code, Most Significant Byte
  294. 0x00, ///< 119 Module Manufacturing Location
  295. 0x00, ///< 120 Module Manufacturing Date Year
  296. 0x00, ///< 121 Module Manufacturing Date creation work week
  297. 0x55, ///< 122 Module ID: Module Serial Number
  298. 0x00, ///< 123 Module Serial Number B
  299. 0x00, ///< 124 Module Serial Number C
  300. 0x00, ///< 125 Module Serial Number D
  301. 0x00, ///< 126 CRC A
  302. 0x00 ///< 127 CRC B
  303. };
  304. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mKblRSpdLpddr32133Size = sizeof (mKblRSpdLpddr32133);
  305. GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSpdLpddr32133[] = {
  306. 0x24, ///< 0 Number of Serial PD Bytes Written / SPD Device Size
  307. 0x01, ///< 1 SPD Revision
  308. 0x0F, ///< 2 DRAM Device Type
  309. 0x0E, ///< 3 Module Type
  310. 0x15, ///< 4 SDRAM Density and Banks: 8 Banks, 8 Gb SDRAM density
  311. 0x19, ///< 5 SDRAM Addressing: 15 Rows, 10 Columns
  312. 0x90, ///< 6 SDRAM Package Type: QDP, 1 Channel per die, Signal Loading Matrix 1
  313. 0x00, ///< 7 SDRAM Optional Features
  314. 0x00, ///< 8 SDRAM Thermal and Refresh Options
  315. 0x00, ///< 9 Other SDRAM Optional Features
  316. 0x00, ///< 10 Reserved - must be coded as 0x00
  317. 0x0B, ///< 11 Module Nominal Voltage, VDD
  318. 0x0B, ///< 12 Module Organization, SDRAM width: 32 bits, 2 Ranks
  319. 0x03, ///< 13 Module Memory Bus Width: 2 channels, 64 bit channel bus width
  320. 0x00, ///< 14 Module Thermal Sensor
  321. 0x00, ///< 15 Extended Module Type
  322. 0x00, ///< 16 Reserved - must be coded as 0x00
  323. 0x00, ///< 17 Timebases
  324. 0x08, ///< 18 SDRAM Minimum Cycle Time (tCKmin)
  325. 0xFF, ///< 19 SDRAM Minimum Cycle Time (tCKmax)
  326. 0xD4, ///< 20 CAS Latencies Supported, First Byte
  327. 0x01, ///< 21 CAS Latencies Supported, Second Byte
  328. 0x00, ///< 22 CAS Latencies Supported, Third Byte
  329. 0x00, ///< 23 CAS Latencies Supported, Fourth Byte
  330. 0x78, ///< 24 Minimum CAS Latency Time (tAAmin)
  331. 0x00, ///< 25 Read and Write Latency Set Options
  332. 0x90, ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
  333. 0xA8, ///< 27 Minimum Row Precharge Delay Time for all banks (tRPab)
  334. 0x90, ///< 28 Minimum Row Precharge Delay Time per bank (tRPpb)
  335. 0x90, ///< 29 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte
  336. 0x06, ///< 30 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte
  337. 0xD0, ///< 31 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
  338. 0x02, ///< 32 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
  339. 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
  340. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
  341. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
  342. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit Mapping
  343. 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit Mapping
  344. 0, 0, ///< 78 - 79
  345. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
  346. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
  347. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
  348. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
  349. 0x00, ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb)
  350. 0x00, ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
  351. 0x00, ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
  352. 0x08, ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
  353. 0x7F, ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
  354. 0xC2, ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
  355. 0x00, ///< 126 CRC A
  356. 0x00, ///< 127 CRC B
  357. 0, 0, ///< 128 - 129
  358. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
  359. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
  360. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
  361. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
  362. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
  363. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
  364. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
  365. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
  366. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
  367. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
  368. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
  369. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
  370. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
  371. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
  372. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
  373. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
  374. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
  375. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
  376. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
  377. 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
  378. 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
  379. 0x00, ///< 322 Module Manufacturing Location
  380. 0x00, ///< 323 Module Manufacturing Date Year
  381. 0x00, ///< 324 Module Manufacturing Date Week
  382. 0x55, ///< 325 Module Serial Number A
  383. 0x00, ///< 326 Module Serial Number B
  384. 0x00, ///< 327 Module Serial Number C
  385. 0x00, ///< 328 Module Serial Number D
  386. 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
  387. 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
  388. 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
  389. 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
  390. 0x00, ///< 349 Module Revision Code
  391. 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
  392. 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
  393. 0x00, ///< 352 DRAM Stepping
  394. 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359
  395. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
  396. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
  397. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
  398. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
  399. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
  400. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
  401. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
  402. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
  403. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449
  404. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
  405. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
  406. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
  407. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
  408. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
  409. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
  410. 0, 0 ///< 510 - 511
  411. };
  412. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSpdLpddr32133Size = sizeof (mSpdLpddr32133);
  413. #endif // _KABYLAKE_RVP3_SPD_TABLE_H_