SmmSiliconAcpiEnableLib.c 4.4 KB

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  1. /** @file
  2. Platform Hook Library instances
  3. Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Base.h>
  7. #include <Uefi.h>
  8. #include <PiDxe.h>
  9. #include <Library/BaseLib.h>
  10. #include <Library/IoLib.h>
  11. #include <Library/BoardAcpiEnableLib.h>
  12. #include <Library/PcdLib.h>
  13. #include <Library/DebugLib.h>
  14. #include <PchAccess.h>
  15. #include <Library/MmPciLib.h>
  16. #include <Library/PchCycleDecodingLib.h>
  17. /**
  18. Clear Port 80h
  19. SMI handler to enable ACPI mode
  20. Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI
  21. Disables the SW SMI Timer.
  22. ACPI events are disabled and ACPI event status is cleared.
  23. SCI mode is then enabled.
  24. Clear SLP SMI status
  25. Enable SLP SMI
  26. Disable SW SMI Timer
  27. Clear all ACPI event status and disable all ACPI events
  28. Disable PM sources except power button
  29. Clear status bits
  30. Disable GPE0 sources
  31. Clear status bits
  32. Disable GPE1 sources
  33. Clear status bits
  34. Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
  35. Enable SCI
  36. **/
  37. EFI_STATUS
  38. EFIAPI
  39. SiliconEnableAcpi (
  40. IN BOOLEAN EnableSci
  41. )
  42. {
  43. UINT32 OutputValue;
  44. UINT32 SmiEn;
  45. UINT32 SmiSts;
  46. UINT32 ULKMC;
  47. UINTN LpcBaseAddress;
  48. UINT16 AcpiBaseAddr;
  49. UINT32 Pm1Cnt;
  50. LpcBaseAddress = MmPciBase (
  51. DEFAULT_PCI_BUS_NUMBER_PCH,
  52. PCI_DEVICE_NUMBER_PCH_LPC,
  53. PCI_FUNCTION_NUMBER_PCH_LPC
  54. );
  55. //
  56. // Get the ACPI Base Address
  57. //
  58. PchAcpiBaseGet (&AcpiBaseAddr);
  59. //
  60. // BIOS must also ensure that CF9GR is cleared and locked before handing control to the
  61. // OS in order to prevent the host from issuing global resets and resetting ME
  62. //
  63. // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
  64. // MmioWrite32 (
  65. // PmcBaseAddress + R_PCH_PMC_ETR3),
  66. // PmInit);
  67. //
  68. // Clear Port 80h
  69. //
  70. IoWrite8 (0x80, 0);
  71. //
  72. // Disable SW SMI Timer and clean the status
  73. //
  74. SmiEn = IoRead32 (AcpiBaseAddr + R_PCH_SMI_EN);
  75. SmiEn &= ~(B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB);
  76. IoWrite32 (AcpiBaseAddr + R_PCH_SMI_EN, SmiEn);
  77. SmiSts = IoRead32 (AcpiBaseAddr + R_PCH_SMI_STS);
  78. SmiSts |= B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB;
  79. IoWrite32 (AcpiBaseAddr + R_PCH_SMI_STS, SmiSts);
  80. //
  81. // Disable port 60/64 SMI trap if they are enabled
  82. //
  83. ULKMC = MmioRead32 (LpcBaseAddress + R_PCH_LPC_ULKMC) & ~(B_PCH_LPC_ULKMC_60REN | B_PCH_LPC_ULKMC_60WEN | B_PCH_LPC_ULKMC_64REN | B_PCH_LPC_ULKMC_64WEN | B_PCH_LPC_ULKMC_A20PASSEN);
  84. MmioWrite32 (LpcBaseAddress + R_PCH_LPC_ULKMC, ULKMC);
  85. //
  86. // Disable PM sources except power button
  87. //
  88. IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
  89. //
  90. // Clear PM status except Power Button status for RapidStart Resume
  91. //
  92. IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xFEFF);
  93. //
  94. // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
  95. //
  96. IoWrite8 (R_PCH_RTC_INDEX_ALT, R_PCH_RTC_REGD);
  97. IoWrite8 (R_PCH_RTC_TARGET_ALT, 0x0);
  98. //
  99. // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
  100. //
  101. OutputValue = IoRead32 (AcpiBaseAddr + 0x38);
  102. OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition));
  103. IoWrite32 (AcpiBaseAddr + 0x38, OutputValue);
  104. //
  105. // Enable SCI
  106. //
  107. if (EnableSci) {
  108. Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
  109. Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
  110. IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
  111. }
  112. return EFI_SUCCESS;
  113. }
  114. EFI_STATUS
  115. EFIAPI
  116. SiliconDisableAcpi (
  117. IN BOOLEAN DisableSci
  118. )
  119. {
  120. UINT16 AcpiBaseAddr;
  121. UINT32 Pm1Cnt;
  122. //
  123. // Get the ACPI Base Address
  124. //
  125. PchAcpiBaseGet (&AcpiBaseAddr);
  126. //
  127. // Disable SCI
  128. //
  129. if (DisableSci) {
  130. Pm1Cnt = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT);
  131. Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SCI_EN;
  132. IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
  133. }
  134. return EFI_SUCCESS;
  135. }