GlobalNvsAreaDef.h 8.5 KB

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  1. /** @file
  2. ACPI DSDT table
  3. Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. // Define a Global region of ACPI NVS Region that may be used for any
  7. // type of implementation. The starting offset and size will be fixed
  8. // up by the System BIOS during POST. Note that the Size must be a word
  9. // in size to be fixed up correctly.
  10. #ifndef _GLOBAL_NVS_AREA_DEF_H_
  11. #define _GLOBAL_NVS_AREA_DEF_H_
  12. #pragma pack (push,1)
  13. typedef struct {
  14. //
  15. // Miscellaneous Dynamic Registers:
  16. //
  17. UINT16 OperatingSystem; ///< Offset 0 Operating System
  18. UINT8 SmiFunction; ///< Offset 2 SMI Function Call (ASL to SMI via I/O Trap)
  19. UINT32 Port80DebugValue; ///< Offset 3 Port 80 Debug Port Value
  20. UINT8 PowerState; ///< Offset 7 Power State (AC Mode = 1)
  21. //
  22. // Thermal Policy Registers:
  23. //
  24. UINT8 EnableDigitalThermalSensor; ///< Offset 8 Digital Thermal Sensor Enable
  25. UINT8 DigitalThermalSensorSmiFunction; ///< Offset 9 DTS SMI Function Call
  26. //
  27. // CPU Identification Registers:
  28. //
  29. UINT8 ApicEnable; ///< Offset 10 APIC Enabled by SBIOS (APIC Enabled = 1)
  30. UINT8 ThreadCount; ///< Offset 11 Number of Enabled Threads
  31. //
  32. // PCIe Hot Plug
  33. //
  34. UINT8 PcieOSCControl; ///< Offset 12 PCIE OSC Control
  35. UINT8 NativePCIESupport; ///< Offset 13 Native PCIE Setup Value
  36. //
  37. // Global Variables
  38. //
  39. UINT8 DisplaySupportFlag; ///< Offset 14 _DOS Display Support Flag.
  40. UINT8 InterruptModeFlag; ///< Offset 15 Global IOAPIC/8259 Interrupt Mode Flag.
  41. UINT8 L01Counter; ///< Offset 16 Global L01 Counter.
  42. UINT8 LtrEnable[24]; ///< Offset 17 Latency Tolerance Reporting Enable
  43. ///< Offset 18 Latency Tolerance Reporting Enable
  44. ///< Offset 19 Latency Tolerance Reporting Enable
  45. ///< Offset 20 Latency Tolerance Reporting Enable
  46. ///< Offset 21 Latency Tolerance Reporting Enable
  47. ///< Offset 22 Latency Tolerance Reporting Enable
  48. ///< Offset 23 Latency Tolerance Reporting Enable
  49. ///< Offset 24 Latency Tolerance Reporting Enable
  50. ///< Offset 25 Latency Tolerance Reporting Enable
  51. ///< Offset 26 Latency Tolerance Reporting Enable
  52. ///< Offset 27 Latency Tolerance Reporting Enable
  53. ///< Offset 28 Latency Tolerance Reporting Enable
  54. ///< Offset 29 Latency Tolerance Reporting Enable
  55. ///< Offset 30 Latency Tolerance Reporting Enable
  56. ///< Offset 31 Latency Tolerance Reporting Enable
  57. ///< Offset 32 Latency Tolerance Reporting Enable
  58. ///< Offset 33 Latency Tolerance Reporting Enable
  59. ///< Offset 34 Latency Tolerance Reporting Enable
  60. ///< Offset 35 Latency Tolerance Reporting Enable
  61. ///< Offset 36 Latency Tolerance Reporting Enable
  62. ///< Offset 37 Latency Tolerance Reporting Enable
  63. ///< Offset 38 Latency Tolerance Reporting Enable
  64. ///< Offset 39 Latency Tolerance Reporting Enable
  65. ///< Offset 40 Latency Tolerance Reporting Enable
  66. UINT8 ObffEnable[24]; ///< Offset 41 Optimized Buffer Flush and Fill
  67. ///< Offset 42 Optimized Buffer Flush and Fill
  68. ///< Offset 43 Optimized Buffer Flush and Fill
  69. ///< Offset 44 Optimized Buffer Flush and Fill
  70. ///< Offset 45 Optimized Buffer Flush and Fill
  71. ///< Offset 46 Optimized Buffer Flush and Fill
  72. ///< Offset 47 Optimized Buffer Flush and Fill
  73. ///< Offset 48 Optimized Buffer Flush and Fill
  74. ///< Offset 49 Optimized Buffer Flush and Fill
  75. ///< Offset 50 Optimized Buffer Flush and Fill
  76. ///< Offset 51 Optimized Buffer Flush and Fill
  77. ///< Offset 52 Optimized Buffer Flush and Fill
  78. ///< Offset 53 Optimized Buffer Flush and Fill
  79. ///< Offset 54 Optimized Buffer Flush and Fill
  80. ///< Offset 55 Optimized Buffer Flush and Fill
  81. ///< Offset 56 Optimized Buffer Flush and Fill
  82. ///< Offset 57 Optimized Buffer Flush and Fill
  83. ///< Offset 58 Optimized Buffer Flush and Fill
  84. ///< Offset 59 Optimized Buffer Flush and Fill
  85. ///< Offset 60 Optimized Buffer Flush and Fill
  86. ///< Offset 61 Optimized Buffer Flush and Fill
  87. ///< Offset 62 Optimized Buffer Flush and Fill
  88. ///< Offset 63 Optimized Buffer Flush and Fill
  89. ///< Offset 64 Optimized Buffer Flush and Fill
  90. UINT8 Rtd3Support; ///< Offset 65 Runtime D3 support.
  91. UINT8 LowPowerS0Idle; ///< Offset 66 Low Power S0 Idle Enable
  92. UINT8 VirtualGpioButtonSxBitmask; ///< Offset 67 Virtual GPIO button Notify Sleep State Change
  93. UINT8 PstateCapping; ///< Offset 68 P-state Capping
  94. UINT8 Ps2MouseEnable; ///< Offset 69 Ps2 Mouse Enable
  95. UINT8 Ps2KbMsEnable; ///< Offset 70 Ps2 Keyboard and Mouse Enable
  96. //
  97. // Driver Mode
  98. //
  99. UINT32 GpioIrqRoute; ///< Offset 71 GPIO IRQ
  100. UINT8 PL1LimitCS; ///< Offset 75 set PL1 limit when entering CS
  101. UINT16 PL1LimitCSValue; ///< Offset 76 PL1 limit value
  102. UINT8 TenSecondPowerButtonEnable; ///< Offset 78 10sec Power button support
  103. UINT8 PciDelayOptimizationEcr; ///< Offset 79 Pci Delay Optimization Ecr
  104. UINT8 TbtSupport; ///< Offset 80 Thunderbolt(TM) support
  105. UINT8 TbtNativeOsHotPlug; ///< Offset 81 TbtNativeOsHotPlug
  106. UINT8 TbtSelector; ///< Offset 82 Thunderbolt(TM) Root port selector
  107. UINT8 TbtSelector1; ///< Offset 83 Thunderbolt(TM) Root port selector
  108. } EFI_GLOBAL_NVS_AREA;
  109. #pragma pack(pop)
  110. #endif