PeiPchPolicyUpdatePreMem.c 12 KB

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  1. /** @file
  2. This file is SampleCode of the library for Intel PCH PEI Policy initialization.
  3. Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "PeiPchPolicyUpdate.h"
  7. #include <Library/BaseMemoryLib.h>
  8. #include <Library/MemoryAllocationLib.h>
  9. #include <Library/HobLib.h>
  10. #include <Guid/GlobalVariable.h>
  11. #include <Library/PchInfoLib.h>
  12. #include <Library/PchPcrLib.h>
  13. #include <Library/PchHsioLib.h>
  14. #include <Library/PchPcieRpLib.h>
  15. #include <PchHsioPtssTables.h>
  16. #include <Library/DebugLib.h>
  17. VOID
  18. InstallPlatformHsioPtssTable (
  19. IN OUT FSPM_UPD *FspmUpd
  20. )
  21. {
  22. HSIO_PTSS_TABLES *UnknowPtssTables;
  23. HSIO_PTSS_TABLES *SpecificPtssTables;
  24. HSIO_PTSS_TABLES *PtssTables;
  25. UINT8 PtssTableIndex;
  26. UINT32 UnknowTableSize;
  27. UINT32 SpecificTableSize;
  28. UINT32 TableSize;
  29. UINT32 Entry;
  30. UINT8 LaneNum;
  31. UINT8 Index;
  32. UINT8 MaxSataPorts;
  33. UINT8 MaxPciePorts;
  34. UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS];
  35. UINT8 PciePort;
  36. UINTN RpBase;
  37. UINTN RpDevice;
  38. UINTN RpFunction;
  39. UINT32 StrapFuseCfg;
  40. UINT8 PcieControllerCfg;
  41. EFI_STATUS Status;
  42. UnknowPtssTables = NULL;
  43. UnknowTableSize = 0;
  44. SpecificPtssTables = NULL;
  45. SpecificTableSize = 0;
  46. if (GetPchGeneration () == SklPch) {
  47. switch (PchStepping ()) {
  48. case PchLpB0:
  49. case PchLpB1:
  50. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1);
  51. UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size);
  52. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1);
  53. SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size);
  54. break;
  55. case PchLpC0:
  56. case PchLpC1:
  57. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2);
  58. UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size);
  59. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2);
  60. SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size);
  61. break;
  62. case PchHB0:
  63. case PchHC0:
  64. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1);
  65. UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size);
  66. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1);
  67. SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size);
  68. break;
  69. case PchHD0:
  70. case PchHD1:
  71. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
  72. UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
  73. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
  74. SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
  75. break;
  76. default:
  77. UnknowPtssTables = NULL;
  78. UnknowTableSize = 0;
  79. SpecificPtssTables = NULL;
  80. SpecificTableSize = 0;
  81. DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
  82. }
  83. } else {
  84. switch (PchStepping ()) {
  85. case KblPchHA0:
  86. UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2);
  87. UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size);
  88. SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2);
  89. SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size);
  90. break;
  91. default:
  92. UnknowPtssTables = NULL;
  93. UnknowTableSize = 0;
  94. SpecificPtssTables = NULL;
  95. SpecificTableSize = 0;
  96. DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));
  97. }
  98. }
  99. PtssTableIndex = 0;
  100. MaxSataPorts = GetPchMaxSataPortNum ();
  101. MaxPciePorts = GetPchMaxPciePortNum ();
  102. ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal));
  103. //Populate PCIe topology based on lane configuration
  104. for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) {
  105. Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction);
  106. ASSERT_EFI_ERROR (Status);
  107. RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction);
  108. StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG);
  109. PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC);
  110. DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg));
  111. }
  112. for (Index = 0; Index < MaxPciePorts; Index++) {
  113. DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index]));
  114. }
  115. //Case 1: BoardId is known, Topology is known/unknown
  116. //Case 1a: SATA
  117. PtssTables = SpecificPtssTables;
  118. TableSize = SpecificTableSize;
  119. for (Index = 0; Index < MaxSataPorts; Index++) {
  120. if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
  121. for (Entry = 0; Entry < TableSize; Entry++) {
  122. if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
  123. (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
  124. )
  125. {
  126. PtssTableIndex++;
  127. if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
  128. (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
  129. FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE;
  130. FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
  131. } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) {
  132. if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
  133. FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE;
  134. FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
  135. }
  136. if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
  137. FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE;
  138. FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
  139. }
  140. } else {
  141. ASSERT (FALSE);
  142. }
  143. }
  144. }
  145. }
  146. }
  147. //Case 1b: PCIe
  148. for (Index = 0; Index < MaxPciePorts; Index++) {
  149. if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
  150. for (Entry = 0; Entry < TableSize; Entry++) {
  151. if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
  152. (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
  153. (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
  154. PtssTableIndex++;
  155. if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
  156. (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
  157. FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE;
  158. FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
  159. } else {
  160. ASSERT (FALSE);
  161. }
  162. }
  163. }
  164. }
  165. }
  166. //Case 2: BoardId is unknown, Topology is known/unknown
  167. if (PtssTableIndex == 0) {
  168. DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n"));
  169. PtssTables = UnknowPtssTables;
  170. TableSize = UnknowTableSize;
  171. for (Index = 0; Index < MaxSataPorts; Index++) {
  172. if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
  173. for (Entry = 0; Entry < TableSize; Entry++) {
  174. if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
  175. (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA)
  176. )
  177. {
  178. if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) &&
  179. (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {
  180. FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE;
  181. FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;
  182. } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) {
  183. if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) {
  184. FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE;
  185. FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);
  186. }
  187. if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) {
  188. FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE;
  189. FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);
  190. }
  191. } else {
  192. ASSERT (FALSE);
  193. }
  194. }
  195. }
  196. }
  197. }
  198. for (Index = 0; Index < MaxPciePorts; Index++) {
  199. if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) {
  200. for (Entry = 0; Entry < TableSize; Entry++) {
  201. if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) &&
  202. (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) &&
  203. (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) {
  204. if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) &&
  205. (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) {
  206. FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE;
  207. FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);
  208. } else {
  209. ASSERT (FALSE);
  210. }
  211. }
  212. }
  213. }
  214. }
  215. }
  216. }
  217. /**
  218. Performs FSP PCH PEI Policy pre mem initialization.
  219. @param[in][out] FspmUpd Pointer to FSP UPD Data.
  220. @retval EFI_SUCCESS FSP UPD Data is updated.
  221. @retval EFI_NOT_FOUND Fail to locate required PPI.
  222. @retval Other FSP UPD Data update process fail.
  223. **/
  224. EFI_STATUS
  225. EFIAPI
  226. PeiFspPchPolicyUpdatePreMem (
  227. IN OUT FSPM_UPD *FspmUpd
  228. )
  229. {
  230. InstallPlatformHsioPtssTable (FspmUpd);
  231. return EFI_SUCCESS;
  232. }