PeiDTbtInitLib.c 19 KB

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  1. /**@file
  2. Thunderbolt(TM) Pei Library
  3. Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Library/PeiServicesLib.h>
  7. #include <Library/MemoryAllocationLib.h>
  8. #include <Library/BaseMemoryLib.h>
  9. #include <Library/DebugLib.h>
  10. #include <Library/GpioLib.h>
  11. #include <GpioPinsSklLp.h>
  12. #include <GpioPinsSklH.h>
  13. #include <Library/TimerLib.h>
  14. #include <Library/IoLib.h>
  15. #include <Library/MmPciLib.h>
  16. #include <Library/HobLib.h>
  17. #include <Library/PcdLib.h>
  18. #include <Library/GpioExpanderLib.h>
  19. #include <Ppi/ReadOnlyVariable2.h>
  20. #include <Base.h>
  21. #include <Library/TbtCommonLib.h>
  22. #include <TbtBoardInfo.h>
  23. #include <IndustryStandard/Pci22.h>
  24. #include <Library/PchCycleDecodingLib.h>
  25. #include <Ppi/PeiTbtPolicy.h>
  26. #include <Library/PciSegmentLib.h>
  27. #include <Library/PeiTbtPolicyLib.h>
  28. #include <Library/PchPmcLib.h>
  29. #include <Private/Library/PeiDTbtInitLib.h>
  30. /**
  31. Is host router (For dTBT) or End Point (For iTBT) present before sleep
  32. @param[in] ControllerType - DTBT_CONTROLLER or ITBT_CONTROLLER
  33. @param[in] Controller - Controller begin offset of CMOS
  34. @Retval TRUE There is a TBT HostRouter presented before sleep
  35. @Retval FALSE There is no TBT HostRouter presented before sleep
  36. BOOLEAN
  37. IsHostRouterPresentBeforeSleep(
  38. IN UINT8 ControllerType,
  39. IN UINT8 Controller
  40. )
  41. {
  42. UINT8 SavedState;
  43. SavedState = (UINT8)GetTbtHostRouterStatus();
  44. if (ControllerType == DTBT_CONTROLLER){
  45. return ((SavedState & (DTBT_SAVE_STATE_OFFSET << Controller)) == (DTBT_SAVE_STATE_OFFSET << Controller));
  46. } else {
  47. if (ControllerType == ITBT_CONTROLLER) {
  48. return ((SavedState & (ITBT_SAVE_STATE_OFFSET << Controller)) == (ITBT_SAVE_STATE_OFFSET << Controller));
  49. }
  50. }
  51. return 0;
  52. }
  53. **/
  54. /**
  55. Execute TBT PCIE2TBT_SX_EXIT_TBT_CONNECTED Mail Box Command for S4 mode with PreBootAclEnable
  56. @param[in] Bus Bus number for Host Router (DTBT)
  57. @param[in] Device Device number for Host Router (DTBT)
  58. @param[in] Function Function number for Host Router (DTBT)
  59. @param[in] Timeout Time out with 100 ms garnularity
  60. @Retval true if command executes succesfully
  61. **/
  62. BOOLEAN
  63. TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(
  64. IN UINT8 Bus,
  65. IN UINT8 Device,
  66. IN UINT8 Function,
  67. IN UINT32 Timeout
  68. )
  69. {
  70. UINT64 Pcie2Tbt;
  71. UINT64 Tbt2Pcie;
  72. UINT32 RegisterValue;
  73. BOOLEAN ReturnFlag;
  74. UINT32 Command;
  75. GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
  76. GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt)
  77. // If PreBootAcl is Enable, we need to enable DATA bit while sending SX EXIT MAIL BOX Command
  78. Command = (1 << 8) | PCIE2TBT_SX_EXIT_TBT_CONNECTED;
  79. PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B);
  80. ReturnFlag = InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterValue);
  81. PciSegmentWrite32(Pcie2Tbt, 0);
  82. return ReturnFlag;
  83. }
  84. /**
  85. Set the Sleep Mode if the HR is up.
  86. @param[in] Bus Bus number for Host Router (DTBT)
  87. @param[in] Device Device number for Host Router (DTBT)
  88. @param[in] Function Function number for Host Router (DTBT)
  89. **/
  90. VOID
  91. TbtSetSxMode(
  92. IN UINT8 Bus,
  93. IN UINT8 Device,
  94. IN UINT8 Function,
  95. IN UINT8 TbtBootOn
  96. )
  97. {
  98. UINT64 TbtUsDevId;
  99. UINT64 Tbt2Pcie;
  100. UINT32 RegVal;
  101. UINT32 MaxLoopCount;
  102. UINTN Delay;
  103. UINT8 RetCode;
  104. EFI_BOOT_MODE BootMode;
  105. EFI_STATUS Status;
  106. TbtUsDevId = PCI_SEGMENT_LIB_ADDRESS(0, Bus, Device, Function, 0);
  107. GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie)
  108. MaxLoopCount = TBT_5S_TIMEOUT; // Wait 5 sec
  109. Delay = 100 * 1000;
  110. RetCode = 0x62;
  111. Status = PeiServicesGetBootMode(&BootMode);
  112. ASSERT_EFI_ERROR(Status);
  113. if ((BootMode == BOOT_ON_S4_RESUME) && (TbtBootOn == 2)) {
  114. MaxLoopCount = TBT_3S_TIMEOUT;
  115. if (!TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(Bus, Device, Function, MaxLoopCount)) {
  116. //
  117. // Nothing to wait, HR is not responsive
  118. //
  119. return;
  120. }
  121. }
  122. else {
  123. if (!TbtSetPcie2TbtCommand(PCIE2TBT_SX_EXIT_TBT_CONNECTED, Bus, Device, Function, MaxLoopCount)) {
  124. //
  125. // Nothing to wait, HR is not responsive
  126. //
  127. return;
  128. }
  129. }
  130. DEBUG((DEBUG_INFO, "Wait for Dev ID != 0xFF\n"));
  131. while (MaxLoopCount-- > 0) {
  132. //
  133. // Check what HR still here
  134. //
  135. RegVal = PciSegmentRead32(Tbt2Pcie);
  136. if (0xFFFFFFFF == RegVal) {
  137. RetCode = 0x6F;
  138. break;
  139. }
  140. //
  141. // Check completion of TBT link
  142. //
  143. RegVal = PciSegmentRead32(TbtUsDevId);
  144. if (0xFFFFFFFF != RegVal) {
  145. RetCode = 0x61;
  146. break;
  147. }
  148. MicroSecondDelay(Delay);
  149. }
  150. DEBUG((DEBUG_INFO, "Return code = 0x%x\n", RetCode));
  151. }
  152. /**
  153. set tPCH25 Timing to 10 ms for DTBT.
  154. @param[in] PEI_TBT_POLICY PeiTbtConfig
  155. @retval EFI_SUCCESS The function completes successfully
  156. @retval EFI_UNSUPPORTED dTBT is not supported.
  157. **/
  158. EFI_STATUS
  159. EFIAPI
  160. DTbtSetTPch25Timing (
  161. IN PEI_TBT_POLICY *PeiTbtConfig
  162. )
  163. {
  164. DEBUG ((DEBUG_INFO, "DTbtSetTPch25Timing call Inside\n"));
  165. UINT32 PchPwrmBase;
  166. //
  167. //During boot, reboot and wake tPCH25 Timing should be set to 10 ms
  168. //
  169. PchPwrmBaseGet (&PchPwrmBase);
  170. MmioOr32 (
  171. (UINTN) (PchPwrmBase + R_PCH_PWRM_CFG),
  172. (BIT0 | BIT1)
  173. );
  174. DEBUG((DEBUG_INFO, "DTbtSetTPch25Timing call Return\n"));
  175. return EFI_SUCCESS;
  176. }
  177. /**
  178. Do ForcePower for DTBT Controller
  179. @param[in] PEI_TBT_POLICY PeiTbtConfig
  180. @retval EFI_SUCCESS The function completes successfully
  181. @retval EFI_UNSUPPORTED dTBT is not supported.
  182. **/
  183. EFI_STATUS
  184. EFIAPI
  185. DTbtForcePower (
  186. IN PEI_TBT_POLICY *PeiTbtConfig
  187. )
  188. {
  189. DEBUG ((DEBUG_INFO, "DTbtForcePower call Inside\n"));
  190. if (PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr) {
  191. DEBUG((DEBUG_INFO, "ForcePwrGpio.GpioPad = %x \n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad));
  192. ForceDtbtPower(PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioAccessType,PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.Expander, PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad, PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioLevel);
  193. DEBUG((DEBUG_INFO, "ForceDtbtPower asserted \n"));
  194. MicroSecondDelay(PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly * 1000);
  195. DEBUG((DEBUG_INFO, "Delay after ForceDtbtPower = 0x%x ms \n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly));
  196. }
  197. DEBUG ((DEBUG_INFO, "DTbtForcePower call Return\n"));
  198. return EFI_SUCCESS;
  199. }
  200. /**
  201. Clear VGA Registers for DTBT.
  202. @param[in] PEI_TBT_POLICY PeiTbtConfig
  203. @retval EFI_SUCCESS The function completes successfully
  204. @retval EFI_UNSUPPORTED dTBT is not supported.
  205. **/
  206. EFI_STATUS
  207. EFIAPI
  208. DTbtClearVgaRegisters (
  209. IN PEI_TBT_POLICY *PeiTbtConfig
  210. )
  211. {
  212. UINTN RpDev;
  213. UINTN RpFunc;
  214. EFI_STATUS Status;
  215. UINT64 BridngeBaseAddress;
  216. UINT16 Data16;
  217. DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Inside\n"));
  218. Status = EFI_SUCCESS;
  219. Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
  220. ASSERT_EFI_ERROR(Status);
  221. //
  222. // VGA Enable and VGA 16-bit decode registers of Bridge control register of Root port where
  223. // Host router resides should be cleaned
  224. //
  225. BridngeBaseAddress = PCI_SEGMENT_LIB_ADDRESS(0, 0, (UINT32)RpDev, (UINT32)RpFunc, 0);
  226. Data16 = PciSegmentRead16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGISTER_OFFSET);
  227. Data16 &= (~(EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16));
  228. PciSegmentWrite16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGISTER_OFFSET, Data16);
  229. DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Return\n"));
  230. return Status;
  231. }
  232. /**
  233. Exectue Mail box command "Boot On".
  234. @param[in] PEI_TBT_POLICY PeiTbtConfig
  235. @retval EFI_SUCCESS The function completes successfully
  236. @retval EFI_UNSUPPORTED dTBT is not supported.
  237. **/
  238. EFI_STATUS
  239. EFIAPI
  240. DTbtBootOn(
  241. IN PEI_TBT_POLICY *PeiTbtConfig
  242. )
  243. {
  244. EFI_STATUS Status;
  245. UINT32 OrgBusNumberConfiguration;
  246. UINTN RpDev;
  247. UINTN RpFunc;
  248. DEBUG((DEBUG_INFO, "DTbtBootOn call Inside\n"));
  249. Status = EFI_SUCCESS;
  250. Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
  251. ASSERT_EFI_ERROR(Status);
  252. OrgBusNumberConfiguration = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
  253. //
  254. // Set Sec/Sub buses to 0xF0
  255. //
  256. PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
  257. //
  258. //When Thunderbolt(TM) boot [TbtBootOn] is enabled in bios setup we need to do the below:
  259. //Bios should send "Boot On" message through PCIE2TBT register
  260. //The Boot On command as described above would include the command and acknowledge from FW (with the default timeout in BIOS),
  261. //once the Boot On command is completed it is guaranteed that the AlpineRidge(AR) device is there and the PCI tunneling was done by FW,
  262. //next step from BIOS is enumeration using SMI
  263. //
  264. if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) {
  265. //
  266. // Exectue Mail box command "Boot On / Pre-Boot ACL"
  267. //
  268. //Command may be executed only during boot/reboot and not during Sx exit flow
  269. if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn == 1) {
  270. if (!TbtSetPcie2TbtCommand(PCIE2TBT_BOOT_ON, 0xF0, 0, 0, TBT_5S_TIMEOUT)) {
  271. //
  272. // Nothing to wait, HR is not responsive
  273. //
  274. DEBUG((DEBUG_INFO, "<TbtPei> DTbtBootOn - Boot On message sent failed \n"));
  275. }
  276. }
  277. if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn == 2) {
  278. if (!TbtSetPcie2TbtCommand(PCIE2TBT_PREBOOTACL, 0xF0, 0, 0, TBT_3S_TIMEOUT)) {
  279. //
  280. // Nothing to wait, HR is not responsive
  281. //
  282. DEBUG((DEBUG_INFO, "<TbtPei> DTbtBootOn - Pre-Boot ACL message sent failed \n"));
  283. }
  284. }
  285. }
  286. //
  287. // Reset Sec/Sub buses to original value
  288. //
  289. PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration);
  290. DEBUG((DEBUG_INFO, "DTbtBootOn call Return\n"));
  291. return Status;
  292. }
  293. /**
  294. Exectue Mail box command "USB On".
  295. @param[in] PEI_TBT_POLICY PeiTbtConfig
  296. @retval EFI_SUCCESS The function completes successfully
  297. @retval EFI_UNSUPPORTED dTBT is not supported.
  298. **/
  299. EFI_STATUS
  300. EFIAPI
  301. DTbtUsbOn(
  302. IN PEI_TBT_POLICY *PeiTbtConfig
  303. )
  304. {
  305. EFI_STATUS Status;
  306. UINTN RpDev;
  307. UINTN RpFunc;
  308. UINT32 OrgBusNumberConfiguration;
  309. UINT64 TbtBaseAddress;
  310. UINT32 MaxWaitIter;
  311. UINT32 RegVal;
  312. EFI_BOOT_MODE BootMode;
  313. DEBUG((DEBUG_INFO, "DTbtUsbOn call Inside\n"));
  314. Status = EFI_SUCCESS;
  315. Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
  316. ASSERT_EFI_ERROR(Status);
  317. OrgBusNumberConfiguration = PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
  318. //
  319. // Set Sec/Sub buses to 0xF0
  320. //
  321. PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
  322. //
  323. //When Thunderbolt(TM) Usb boot [TbtUsbOn] is enabled in bios setup we need to do the below:
  324. //Bios should send "Usb On" message through PCIE2TBT register
  325. //The Usb On command as described above would include the command and acknowledge from FW (with the default timeout in BIOS),
  326. //once the Usb On command is completed it is guaranteed that the AlpineRidge(AR) device is there and the PCI tunneling was done by FW,
  327. //next step from BIOS is enumeration using SMI
  328. //
  329. if (PeiTbtConfig->DTbtCommonConfig.TbtUsbOn) {
  330. if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) {
  331. MaxWaitIter = 50; // Wait 5 sec
  332. TbtBaseAddress = PCI_SEGMENT_LIB_ADDRESS(0, 0xF0, 0, 0, 0);
  333. //
  334. // Driver clears the PCIe2TBT Valid bit to support two consicutive mailbox commands
  335. //
  336. PciSegmentWrite32(TbtBaseAddress + PCIE2TBT_DTBT_R, 0);
  337. DEBUG((DEBUG_INFO, "TbtBaseAddress + PCIE2TBT_DTBT_R = 0x%lx \n", TbtBaseAddress + PCIE2TBT_DTBT_R));
  338. while (MaxWaitIter-- > 0) {
  339. RegVal = PciSegmentRead32(TbtBaseAddress + TBT2PCIE_DTBT_R);
  340. if (0xFFFFFFFF == RegVal) {
  341. //
  342. // Device is not here return now
  343. //
  344. DEBUG((DEBUG_INFO, "TBT device is not present \n"));
  345. break;
  346. }
  347. if (!(RegVal & TBT2PCIE_DON_R)) {
  348. break;
  349. }
  350. MicroSecondDelay(100 * 1000);
  351. }
  352. }
  353. Status = PeiServicesGetBootMode(&BootMode);
  354. ASSERT_EFI_ERROR(Status);
  355. //
  356. // Exectue Mail box command "Usb On"
  357. //
  358. //Command may be executed only during boot/reboot and not during S3 exit flow
  359. //In case of S4 Exit send USB ON cmd only if Host Router was inactive/not present during S4 entry
  360. if ((BootMode == BOOT_ON_S4_RESUME) ) {
  361. // USB_ON cmd not required
  362. } else {
  363. if (!TbtSetPcie2TbtCommand(PCIE2TBT_USB_ON, 0xF0, 0, 0, TBT_5S_TIMEOUT)) {
  364. //
  365. // Nothing to wait, HR is not responsive
  366. //
  367. DEBUG((DEBUG_INFO, "<TbtPei> TbtBootSupport - Usb On message sent failed \n"));
  368. }
  369. }
  370. }
  371. //
  372. // Reset Sec/Sub buses to original value
  373. //
  374. PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration);
  375. DEBUG((DEBUG_INFO, "DTbtUsbOn call return\n"));
  376. return Status;
  377. }
  378. /**
  379. Exectue Mail box command "Sx Exit".
  380. @param[in] PEI_TBT_POLICY PeiTbtConfig
  381. @retval EFI_SUCCESS The function completes successfully
  382. @retval EFI_UNSUPPORTED dTBT is not supported.
  383. **/
  384. EFI_STATUS
  385. EFIAPI
  386. DTbtSxExitFlow(
  387. IN PEI_TBT_POLICY *PeiTbtConfig
  388. )
  389. {
  390. EFI_STATUS Status;
  391. UINT32 OrgBusNumberConfiguration;
  392. UINTN RpDev;
  393. UINTN RpFunc;
  394. UINT32 Count;
  395. DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Inside\n"));
  396. Status = EFI_SUCCESS;
  397. Count = 0;
  398. Status = GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc);
  399. ASSERT_EFI_ERROR(Status);
  400. OrgBusNumberConfiguration = PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET));
  401. //
  402. // Set Sec/Sub buses to 0xF0
  403. //
  404. PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000);
  405. if ( (PeiTbtConfig->DTbtCommonConfig.TbtBootOn == 2)) {
  406. //
  407. // WA: When system with TBT 3.1 device, resume SX system need to wait device ready. In document that maximum time out should be 500ms.
  408. //
  409. while (PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS(0, 0xf0, 0x0, 0x0, 0x08)) == 0xffffffff) { //End Device will be with Device Number 0x0, Function Number 0x0.
  410. MicroSecondDelay(STALL_ONE_MICRO_SECOND * 1000); // 1000usec
  411. Count++;
  412. if (Count > 10000) { //Allowing Max Delay of 10 sec for CFL-S board.
  413. break;
  414. }
  415. }
  416. //
  417. // Upon wake, if BIOS saved pre-Sx Host Router state as active (system went to sleep with
  418. // attached devices), BIOS should:
  419. // 1. Execute "Sx_Exit_TBT_Connected" mailbox command.
  420. // 2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
  421. // 3. Continue regular wake flow.
  422. //
  423. //
  424. // Exectue Mail box command and perform "wait for fast link bring-up" loop
  425. //
  426. TbtSetSxMode(0xF0, 0, 0, PeiTbtConfig->DTbtCommonConfig.TbtBootOn);
  427. }
  428. //
  429. // Reset Sec/Sub buses to original value
  430. //
  431. PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration);
  432. DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Return\n"));
  433. return Status;
  434. }
  435. /**
  436. Initialize Thunderbolt(TM)
  437. @retval EFI_SUCCESS The function completes successfully
  438. @retval others
  439. **/
  440. EFI_STATUS
  441. EFIAPI
  442. TbtInit (
  443. VOID
  444. )
  445. {
  446. EFI_STATUS Status;
  447. PEI_TBT_POLICY *PeiTbtConfig;
  448. //
  449. // Get the TBT Policy
  450. //
  451. Status = PeiServicesLocatePpi (
  452. &gPeiTbtPolicyPpiGuid,
  453. 0,
  454. NULL,
  455. (VOID **) &PeiTbtConfig
  456. );
  457. if (EFI_ERROR(Status)) {
  458. DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n"));
  459. }
  460. ASSERT_EFI_ERROR (Status);
  461. //
  462. // Exectue Mail box command "Boot On"
  463. //
  464. Status = DTbtBootOn (PeiTbtConfig);
  465. //
  466. // Exectue Mail box command "Usb On"
  467. //
  468. Status = DTbtUsbOn (PeiTbtConfig);
  469. //
  470. //During boot, reboot and wake (bits [1:0]) of PCH PM_CFG register should be
  471. //set to 11b - 10 ms (default value is 0b - 10 us)
  472. //
  473. Status = DTbtSetTPch25Timing (PeiTbtConfig);
  474. //
  475. // Configure Tbt Force Power
  476. //
  477. Status = DTbtForcePower (PeiTbtConfig);
  478. //
  479. // VGA Enable and VGA 16-bit decode registers of Bridge control register of Root port where
  480. // Host router resides should be cleaned
  481. //
  482. Status = DTbtClearVgaRegisters (PeiTbtConfig);
  483. //
  484. // Upon wake, if BIOS saved pre-Sx Host Router state as active (system went to sleep with
  485. // attached devices), BIOS should:
  486. // 1. Execute "Sx_Exit_TBT_Connected" mailbox command.
  487. // 2. If procedure above returns true, BIOS should perform "wait for fast link bring-up" loop
  488. // 3. Continue regular wake flow.
  489. //
  490. Status = DTbtSxExitFlow (PeiTbtConfig);
  491. return EFI_SUCCESS;
  492. }