TbtPolicyCommonDefinition.h 3.9 KB

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  1. /** @file
  2. TBT Policy Common definition.
  3. Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _TBT_POLICY_COMMON_H_
  7. #define _TBT_POLICY_COMMON_H_
  8. #include <Library/GpioLib.h>
  9. #include <IndustryStandard/Pci22.h>
  10. #define TYPE_PCIE 0x01
  11. #define TYPE_PEG 0x02
  12. #pragma pack(push, 1)
  13. //
  14. // dTBT Force Power GPIO Data Structure
  15. //
  16. typedef struct _DTBT_FORCE_POWER_GPIO_CONFIG {
  17. UINT8 GpioAccessType; ///< Where the GPIO comes from [a.k.a how to access the GPIO],Where the GPIO comes from. 0: Disabled; 1: PCH, 2: I/O Expander
  18. UINT8 Expander; ///< Applicable to GpioAccessType = IoExpander {TCA6424A} type
  19. GPIO_PAD GpioPad; ///< GPIO Pad Number
  20. BOOLEAN GpioLevel; ///< 0 = Active Low; 1 = Active High
  21. UINT8 Reserved[1]; ///< Reserved for DWORD alignment
  22. } DTBT_FORCE_POWER_GPIO_CONFIG;
  23. //
  24. // dTBT CIO Plug Event GPIO Data Structure
  25. //
  26. typedef struct _DTBT_CIO_PLUG_EVENT_GPIO_CONFIG {
  27. GPIO_PAD GpioPad; ///< GPIO Pad Number
  28. UINT32 AcpiGpeSignature; ///< AcpiPlatform driver will change the XTBT method to the _Lxx or _Exx that we assign in this item.
  29. BOOLEAN AcpiGpeSignaturePorting; ///< 0 = No porting required(for 2-tier GPI GPE event architecture), 1 = Porting required(for 1-tier GPI GPE event architecture)
  30. UINT8 Reserved[3]; ///< Reserved for DWORD alignment
  31. } DTBT_CIO_PLUG_EVENT_GPIO_CONFIG;
  32. //
  33. // dTBT PCIE Reset GPIO Data Structure
  34. //
  35. typedef struct _DTBT_PCIE_RESET_GPIO_CONFIG {
  36. GPIO_PAD GpioPad; ///< GPIO Pad Number
  37. BOOLEAN GpioLevel; ///< 0 = Active Low; 1 = Active High
  38. UINT8 Reserved[3]; ///< Reserved for DWORD alignment
  39. } DTBT_PCIE_RESET_GPIO_CONFIG;
  40. //
  41. // dTBT Controller Data Structure
  42. //
  43. typedef struct _DTBT_CONTROLLER_CONFIG{
  44. UINT8 DTbtControllerEn; ///< Enable/Disable DTbtController.
  45. UINT8 Type; ///< 01-Pcie RP, 02- PEG,Reserved. <Specific according to Board Design>
  46. UINT8 PcieRpNumber; ///< RP Number/ PEG Port (0,1,2) that connecet to dTBT controller. <Specific according to Board Design>
  47. DTBT_FORCE_POWER_GPIO_CONFIG ForcePwrGpio; ///< The GPIO pin that can force dTBT Power On. <Specific according to Board Design>
  48. DTBT_CIO_PLUG_EVENT_GPIO_CONFIG CioPlugEventGpio; ///< The GPIO pin that can generate Hot-Plug event. <Specific according to Board Design>
  49. DTBT_PCIE_RESET_GPIO_CONFIG PcieRstGpio; ///< The GPIO pin that is use to perform Reset when platform enters to Sx, it is required for platforms where PCI_RST pin connected to Tbt is controlled with GPIO <Specific according to Board Design>
  50. UINT8 Reserved[1]; ///< Reserved for DWORD alignment
  51. } DTBT_CONTROLLER_CONFIG;
  52. //
  53. // dTBT Controller Data Structure
  54. //
  55. typedef struct _DTBT_COMMON_CONFIG{
  56. UINT8 TbtBootOn; ///< Send BootOn Mailbox command when TbtBootOn is enabled.
  57. UINT8 TbtUsbOn; ///< Send UsbOn Mailbox command when TbtBootOn is enabled.
  58. UINT8 Gpio3ForcePwr; ///< Force GPIO to power on or not
  59. UINT16 Gpio3ForcePwrDly; ///< The delay time after do ForcePwr
  60. BOOLEAN DTbtSharedGpioConfiguration; ///< Multiple DTBT controllers share the same GPIO pin <Specific according to Board Design>
  61. BOOLEAN PcieRstSupport; ///< 0 = Not Support, 1 = Supported. it is required for platforms where PCI_RST pin connected to Tbt is controlled with GPIO
  62. UINT8 Reserved[1]; ///< Reserved for DWORD alignment
  63. } DTBT_COMMON_CONFIG;
  64. #pragma pack(pop)
  65. #endif