DxeTbtPolicy.h 3.2 KB

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  1. /** @file
  2. TBT DXE Policy
  3. Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _DXE_TBT_POLICY_H_
  7. #define _DXE_TBT_POLICY_H_
  8. #include <TbtPolicyCommonDefinition.h>
  9. #pragma pack(push, 1)
  10. #define DXE_TBT_POLICY_REVISION 1
  11. //
  12. // TBT Common Data Structure
  13. //
  14. typedef struct _TBT_COMMON_CONFIG{
  15. /**
  16. TBT Security Level
  17. <b>0: SL0 No Security</b>, 1: SL1 User Authorization, 2: SL2 Secure Connect, 3: SL3 Display Port and USB
  18. **/
  19. UINT32 SecurityMode : 3;
  20. /**
  21. BIOS W/A for Hot plug of 12V USB devices cause electrical noise on PCH GPIOs
  22. <b>0: Disabled</b>, 1: Enabled
  23. **/
  24. UINT32 Gpio5Filter : 1;
  25. /**
  26. Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
  27. <b>0: Disabled</b>, 1: Enabled
  28. **/
  29. UINT32 TbtWakeupSupport : 1;
  30. /**
  31. SMI TBT enumeration
  32. <b>0: Disabled</b>, 1: Enabled
  33. **/
  34. UINT32 TbtHotSMI : 1;
  35. /**
  36. Notify PCIe RP after Hot-Plug/Hot-Unplug occurred.
  37. <b>0: Disabled</b>, 1: Enabled
  38. **/
  39. UINT32 TbtHotNotify : 1;
  40. /**
  41. CLK REQ for all the PCIe device in TBT daisy chain.
  42. <b>0: Disabled</b>, 1: Enabled
  43. **/
  44. UINT32 TbtSetClkReq : 1;
  45. /**
  46. ASPM setting for all the PCIe device in TBT daisy chain.
  47. <b>0: Disabled</b>, 1: L0s, 2: L1, 3: L0sL1
  48. **/
  49. UINT32 TbtAspm : 2;
  50. /**
  51. LTR for for all the PCIe device in TBT daisy chain.
  52. <b>0: Disabled</b>, 1: Enabled
  53. **/
  54. UINT32 TbtLtr : 1;
  55. /**
  56. TBT Dynamic AC/DC L1.
  57. <b>0: Disabled</b>, 1: Enabled
  58. **/
  59. UINT32 TbtAcDcSwitch : 1;
  60. /**
  61. TBT RTD3 Support.
  62. <b>0: Disabled</b>, 1: Enabled
  63. **/
  64. UINT32 Rtd3Tbt : 1;
  65. /**
  66. TBT ClkReq for RTD3 Flow.
  67. <b>0: Disabled</b>, 1: Enabled
  68. **/
  69. UINT32 Rtd3TbtClkReq : 1;
  70. /**
  71. TBT Win10support for Tbt FW execution mode.
  72. <b>0: Disabled</b>, 1: Native, 2: Native + RTD3
  73. **/
  74. UINT32 Win10Support : 2;
  75. UINT32 Rsvd0 : 17; ///< Reserved bits
  76. UINT16 Rtd3TbtClkReqDelay;
  77. UINT16 Rtd3TbtOffDelay;
  78. } TBT_COMMON_CONFIG;
  79. //
  80. // dTBT Resource Data Structure
  81. //
  82. typedef struct _DTBT_RESOURCE_CONFIG{
  83. UINT8 DTbtPcieExtraBusRsvd; ///< Preserve Bus resource for PCIe RP that connect to dTBT Host Router
  84. UINT16 DTbtPcieMemRsvd; ///< Preserve MEM resource for PCIe RP that connect to dTBT Host Router
  85. UINT8 DTbtPcieMemAddrRngMax; ///< Alignment of Preserve MEM resource for PCIe RP that connect to dTBT Host Router
  86. UINT16 DTbtPciePMemRsvd; ///< Preserve PMEM resource for PCIe RP that connect to dTBT Host Router
  87. UINT8 DTbtPciePMemAddrRngMax; ///< Alignment of Preserve PMEM resource for PCIe RP that connect to dTBT Host Router
  88. UINT8 Reserved[1]; ///< Reserved for DWORD alignment
  89. } DTBT_RESOURCE_CONFIG;
  90. /**
  91. TBT DXE configuration\n
  92. <b>Revision 1</b>:
  93. - Initial version.
  94. **/
  95. typedef struct _DXE_TBT_POLICY_PROTOCOL {
  96. TBT_COMMON_CONFIG TbtCommonConfig; ///< Tbt Common Information
  97. DTBT_RESOURCE_CONFIG DTbtResourceConfig; ///< dTbt Resource Configuration
  98. } DXE_TBT_POLICY_PROTOCOL;
  99. #pragma pack(pop)
  100. #endif