TbtNvs.asl 3.7 KB

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  1. /**@file
  2. Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. //
  6. // Define TBT NVS Area operation region.
  7. //
  8. OperationRegion(BNVS,SystemMemory,TNVB,TNVL)
  9. Field(BNVS,AnyAcc,Lock,Preserve)
  10. { Offset(0), TBSF, 8, // Offset(0), Thunderbolt(TM) SMI Function Number
  11. Offset(1), SOHP, 8, // Offset(1), SMI on Hot Plug for TBT devices
  12. Offset(2), TWIN, 8, // Offset(2), TbtWin10Support
  13. Offset(3), GP5F, 8, // Offset(3), Gpio filter to detect USB Hotplug event
  14. Offset(4), NOHP, 8, // Offset(4), Notify on Hot Plug for TBT devices
  15. Offset(5), TBSE, 8, // Offset(5), Thunderbolt(TM) Root port selector
  16. Offset(6), WKFN, 8, // Offset(6), WAK Finished
  17. Offset(7), TBTS, 8, // Offset(7), Thunderbolt(TM) support
  18. Offset(8), TARS, 8, // Offset(8), TbtAcpiRemovalSupport
  19. Offset(9), FPEN, 32, // Offset(9), TbtFrcPwrEn
  20. Offset(13), FPG0, 32, // Offset(13), TbtFrcPwrGpioNo
  21. Offset(17), FP0L, 8, // Offset(17), TbtFrcPwrGpioLevel
  22. Offset(18), CPG0, 32, // Offset(18), TbtCioPlugEventGpioNo
  23. Offset(22), RSG0, 32, // Offset(22), TbtPcieRstGpioNo
  24. Offset(26), RS0L, 8, // Offset(26), TbtPcieRstGpioLevel
  25. Offset(27), DTCP, 8, // Offset(27), Current Port that has plug event
  26. Offset(28), RPS0, 8, // Offset(28), Root port Selected by the User
  27. Offset(29), RPT0, 8, // Offset(29), Root port Type
  28. Offset(30), RPS1, 8, // Offset(30), Root port Selected by the User
  29. Offset(31), RPT1, 8, // Offset(31), Root port Type
  30. Offset(32), RPN0, 8, // Offset(32), Root port Enabled by the User
  31. Offset(33), RPN1, 8, // Offset(33), Root port Enabled by the User
  32. Offset(34), FPG1, 32, // Offset(34), TbtFrcPwrGpioNo
  33. Offset(38), FP1L, 8, // Offset(38), TbtFrcPwrGpioLevel
  34. Offset(39), CPG1, 32, // Offset(39), TbtCioPlugEventGpioNo
  35. Offset(43), RSG1, 32, // Offset(43), TbtPcieRstGpioNo
  36. Offset(47), RS1L, 8, // Offset(47), TbtPcieRstGpioLevel
  37. Offset(48), CGST, 8, // Offset(48), Set if Single GPIO is used for Multi/Different Controller Hot plug support
  38. Offset(49), DTPT, 8, // Offset(49), Root Port type for which SCI Triggered
  39. Offset(50), TRWA, 8, // Offset(50), Titan Ridge Osup command
  40. Offset(51), ACDC, 8, // Offset(51), TBT Dynamic AcDc L1
  41. Offset(52), DT0E, 8, // Offset(52), DTbtController0 is enabled or not.
  42. Offset(53), DT1E, 8, // Offset(53), DTbtController1 is enabled or not.
  43. Offset(54), TASP, 8, // Offset(54), ASPM setting for all the PCIe device in TBT daisy chain.
  44. Offset(55), TL1S, 8, // Offset(55), L1 SubState for for all the PCIe device in TBT daisy chain.
  45. Offset(56), TCLK, 8, // Offset(56), CLK REQ for all the PCIe device in TBT daisy chain.
  46. Offset(57), TLTR, 8, // Offset(57), LTR for for all the PCIe device in TBT daisy chain.
  47. Offset(58), TPTM, 8, // Offset(58), PTM for for all the PCIe device in TBT daisy chain.
  48. Offset(59), TWAK, 8, // Offset(59), Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport
  49. Offset(60), TBOD, 16, // Offset(60), Rtd3TbtOffDelay TBT RTD3 Off Delay
  50. Offset(62), TSXW, 8, // Offset(62), TbtSxWakeSwitchLogicEnable Set True if TBT_WAKE_N will be routed to PCH WakeB at Sx entry point. HW logic is required.
  51. Offset(63), RTBT, 8, // Offset(63), Enable Rtd3 support for TBT. Corresponding to Rtd3Tbt in Setup.
  52. Offset(64), RTBC, 8, // Offset(64), Enable TBT RTD3 CLKREQ mask.
  53. Offset(65), TBCD, 16, // Offset(65), TBT RTD3 CLKREQ mask delay.
  54. }