Tbt.asl 45 KB

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  1. /** @file
  2. Thunderbolt ACPI methods
  3. Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #define DTBT_CONTROLLER 0x00
  7. #define DTBT_TYPE_PCH 0x01
  8. #define DTBT_TYPE_PEG 0x02
  9. #define DTBT_SMI_HANDLER_NUMBER 0xF7
  10. #define TBT_SMI_ENUMERATION_FUNCTION 21
  11. #define TBT_SMI_RESET_SWITCH_FUNCTION 22
  12. #define TBT_SMI_DISABLE_MSI_FUNCTION 23
  13. #ifndef BIT29
  14. #define BIT29 0x20000000
  15. #endif
  16. Name(LDLY, 300) //300 ms
  17. Name (TNVB, 0xFFFF0000) // TBT NVS Base address
  18. Name (TNVL, 0xAA55) // TBT NVS Length
  19. Include ("Acpi/TbtNvs.asl")
  20. External(\_SB.PCI0.RP02.L23D, MethodObj)
  21. External(\_SB.PCI0.RP03.L23D, MethodObj)
  22. External(\_SB.PCI0.RP04.L23D, MethodObj)
  23. External(\_SB.PCI0.RP05.L23D, MethodObj)
  24. External(\_SB.PCI0.RP06.L23D, MethodObj)
  25. External(\_SB.PCI0.RP07.L23D, MethodObj)
  26. External(\_SB.PCI0.RP08.L23D, MethodObj)
  27. External(\_SB.PCI0.RP09.L23D, MethodObj)
  28. External(\_SB.PCI0.RP10.L23D, MethodObj)
  29. External(\_SB.PCI0.RP11.L23D, MethodObj)
  30. External(\_SB.PCI0.RP12.L23D, MethodObj)
  31. External(\_SB.PCI0.RP13.L23D, MethodObj)
  32. External(\_SB.PCI0.RP14.L23D, MethodObj)
  33. External(\_SB.PCI0.RP15.L23D, MethodObj)
  34. External(\_SB.PCI0.RP16.L23D, MethodObj)
  35. External(\_SB.PCI0.RP17.L23D, MethodObj)
  36. External(\_SB.PCI0.RP18.L23D, MethodObj)
  37. External(\_SB.PCI0.RP19.L23D, MethodObj)
  38. External(\_SB.PCI0.RP20.L23D, MethodObj)
  39. External(\_SB.PCI0.RP21.L23D, MethodObj)
  40. External(\_SB.PCI0.RP22.L23D, MethodObj)
  41. External(\_SB.PCI0.RP23.L23D, MethodObj)
  42. External(\_SB.PCI0.RP24.L23D, MethodObj)
  43. External(\_SB.PCI0.RP01.DL23, MethodObj)
  44. External(\_SB.PCI0.RP02.DL23, MethodObj)
  45. External(\_SB.PCI0.RP03.DL23, MethodObj)
  46. External(\_SB.PCI0.RP04.DL23, MethodObj)
  47. External(\_SB.PCI0.RP05.DL23, MethodObj)
  48. External(\_SB.PCI0.RP06.DL23, MethodObj)
  49. External(\_SB.PCI0.RP07.DL23, MethodObj)
  50. External(\_SB.PCI0.RP08.DL23, MethodObj)
  51. External(\_SB.PCI0.RP09.DL23, MethodObj)
  52. External(\_SB.PCI0.RP10.DL23, MethodObj)
  53. External(\_SB.PCI0.RP11.DL23, MethodObj)
  54. External(\_SB.PCI0.RP12.DL23, MethodObj)
  55. External(\_SB.PCI0.RP13.DL23, MethodObj)
  56. External(\_SB.PCI0.RP14.DL23, MethodObj)
  57. External(\_SB.PCI0.RP15.DL23, MethodObj)
  58. External(\_SB.PCI0.RP16.DL23, MethodObj)
  59. External(\_SB.PCI0.RP17.DL23, MethodObj)
  60. External(\_SB.PCI0.RP18.DL23, MethodObj)
  61. External(\_SB.PCI0.RP19.DL23, MethodObj)
  62. External(\_SB.PCI0.RP20.DL23, MethodObj)
  63. External(\_SB.PCI0.RP21.DL23, MethodObj)
  64. External(\_SB.PCI0.RP22.DL23, MethodObj)
  65. External(\_SB.PCI0.RP23.DL23, MethodObj)
  66. External(\_SB.PCI0.RP24.DL23, MethodObj)
  67. External(\_SB.PCI0.RTEN, MethodObj)
  68. External(\_SB.PCI0.RTDS, MethodObj)
  69. External(\_SB.PCI0.RP01.PON, MethodObj)
  70. External(\_SB.PCI0.RP02.PON, MethodObj)
  71. External(\_SB.PCI0.RP03.PON, MethodObj)
  72. External(\_SB.PCI0.RP04.PON, MethodObj)
  73. External(\_SB.PCI0.RP05.PON, MethodObj)
  74. External(\_SB.PCI0.RP06.PON, MethodObj)
  75. External(\_SB.PCI0.RP07.PON, MethodObj)
  76. External(\_SB.PCI0.RP08.PON, MethodObj)
  77. External(\_SB.PCI0.RP09.PON, MethodObj)
  78. External(\_SB.PCI0.RP10.PON, MethodObj)
  79. External(\_SB.PCI0.RP11.PON, MethodObj)
  80. External(\_SB.PCI0.RP12.PON, MethodObj)
  81. External(\_SB.PCI0.RP13.PON, MethodObj)
  82. External(\_SB.PCI0.RP14.PON, MethodObj)
  83. External(\_SB.PCI0.RP15.PON, MethodObj)
  84. External(\_SB.PCI0.RP16.PON, MethodObj)
  85. External(\_SB.PCI0.RP17.PON, MethodObj)
  86. External(\_SB.PCI0.RP18.PON, MethodObj)
  87. External(\_SB.PCI0.RP19.PON, MethodObj)
  88. External(\_SB.PCI0.RP20.PON, MethodObj)
  89. External(\_SB.PCI0.RP21.PON, MethodObj)
  90. External(\_SB.PCI0.RP22.PON, MethodObj)
  91. External(\_SB.PCI0.RP23.PON, MethodObj)
  92. External(\_SB.PCI0.RP24.PON, MethodObj)
  93. External(\_SB.PCI0.PEG0.PG00._ON, MethodObj)
  94. External(\_SB.PCI0.PEG1.PG01._ON, MethodObj)
  95. External(\_SB.PCI0.PEG2.PG02._ON, MethodObj)
  96. Name(TRDO, 0) // 1 during TBT RTD3 _ON
  97. Name(TRD3, 0) // 1 during TBT RTD3 _OFF
  98. Name(TBPE, 0) // Reflects RTD3_PWR_EN value
  99. Name(TOFF, 0) // param to TBT _OFF method
  100. Method (TBON, 0, Serialized) {
  101. // TBT On process before entering Sx state.
  102. Store(1, TRDO)
  103. Switch (ToInteger(\RPS0)) { // TBT Root port Selector
  104. Case (1) {
  105. If (CondRefOf(\_SB.PCI0.RP01.PON)) {
  106. \_SB.PCI0.RP01.PON()
  107. }
  108. }
  109. Case (2) {
  110. If (CondRefOf(\_SB.PCI0.RP02.PON)) {
  111. \_SB.PCI0.RP02.PON()
  112. }
  113. }
  114. Case (3) {
  115. If (CondRefOf(\_SB.PCI0.RP03.PON)) {
  116. \_SB.PCI0.RP03.PON()
  117. }
  118. }
  119. Case (4) {
  120. If (CondRefOf(\_SB.PCI0.RP04.PON)) {
  121. \_SB.PCI0.RP04.PON()
  122. }
  123. }
  124. Case (5) {
  125. If (CondRefOf(\_SB.PCI0.RP05.PON)) {
  126. \_SB.PCI0.RP05.PON()
  127. }
  128. }
  129. Case (6) {
  130. If (CondRefOf(\_SB.PCI0.RP06.PON)) {
  131. \_SB.PCI0.RP06.PON()
  132. }
  133. }
  134. Case (7) {
  135. If (CondRefOf(\_SB.PCI0.RP07.PON)) {
  136. \_SB.PCI0.RP07.PON()
  137. }
  138. }
  139. Case (8) {
  140. If (CondRefOf(\_SB.PCI0.RP08.PON)) {
  141. \_SB.PCI0.RP08.PON()
  142. }
  143. }
  144. Case (9) {
  145. If (CondRefOf(\_SB.PCI0.RP09.PON)) {
  146. \_SB.PCI0.RP09.PON()
  147. }
  148. }
  149. Case (10) {
  150. If (CondRefOf(\_SB.PCI0.RP10.PON)) {
  151. \_SB.PCI0.RP10.PON()
  152. }
  153. }
  154. Case (11) {
  155. If (CondRefOf(\_SB.PCI0.RP11.PON)) {
  156. \_SB.PCI0.RP11.PON()
  157. }
  158. }
  159. Case (12) {
  160. If (CondRefOf(\_SB.PCI0.RP12.PON)) {
  161. \_SB.PCI0.RP12.PON()
  162. }
  163. }
  164. Case (13) {
  165. If (CondRefOf(\_SB.PCI0.RP13.PON)) {
  166. \_SB.PCI0.RP13.PON()
  167. }
  168. }
  169. Case (14) {
  170. If (CondRefOf(\_SB.PCI0.RP14.PON)) {
  171. \_SB.PCI0.RP14.PON()
  172. }
  173. }
  174. Case (15) {
  175. If (CondRefOf(\_SB.PCI0.RP15.PON)) {
  176. \_SB.PCI0.RP15.PON()
  177. }
  178. }
  179. Case (16) {
  180. If (CondRefOf(\_SB.PCI0.RP16.PON)) {
  181. \_SB.PCI0.RP16.PON()
  182. }
  183. }
  184. Case (17) {
  185. If (CondRefOf(\_SB.PCI0.RP17.PON)) {
  186. \_SB.PCI0.RP17.PON()
  187. }
  188. }
  189. Case (18) {
  190. If (CondRefOf(\_SB.PCI0.RP18.PON)) {
  191. \_SB.PCI0.RP18.PON()
  192. }
  193. }
  194. Case (19) {
  195. If (CondRefOf(\_SB.PCI0.RP19.PON)) {
  196. \_SB.PCI0.RP19.PON()
  197. }
  198. }
  199. Case (20) {
  200. If (CondRefOf(\_SB.PCI0.RP20.PON)) {
  201. \_SB.PCI0.RP20.PON()
  202. }
  203. }
  204. Case (21) {
  205. If (CondRefOf(\_SB.PCI0.RP21.PON)) {
  206. \_SB.PCI0.RP21.PON()
  207. }
  208. }
  209. Case (22) {
  210. If (CondRefOf(\_SB.PCI0.RP22.PON)) {
  211. \_SB.PCI0.RP22.PON()
  212. }
  213. }
  214. Case (23) {
  215. If (CondRefOf(\_SB.PCI0.RP23.PON)) {
  216. \_SB.PCI0.RP23.PON()
  217. }
  218. }
  219. Case (24) {
  220. If (CondRefOf(\_SB.PCI0.RP24.PON)) {
  221. \_SB.PCI0.RP24.PON()
  222. }
  223. }
  224. }//Switch(ToInteger(RPS0)) // TBT Selector
  225. Store(0, TRDO)
  226. } // End of TBON
  227. //
  228. // Name: TBTD
  229. // Description: Function to return the TBT RP# device no
  230. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  231. // Input: Arg1 -> Tbt port type value from Tbt NVS
  232. // Return: TBT RP# device no
  233. //
  234. Method(TBTD,2)
  235. {
  236. ADBG("TBTD")
  237. If (LEqual(Arg1, DTBT_TYPE_PCH)) {
  238. Switch(ToInteger(Arg0))
  239. {
  240. Case (Package () {1, 2, 3, 4, 5, 6, 7, 8})
  241. {
  242. Store(0x1C, Local0) //Device28-Function0...Function7 = 11100.000...111
  243. }
  244. Case (Package () {9, 10, 11, 12, 13, 14, 15, 16})
  245. {
  246. Store(0x1D, Local0) //Device29-Function0...Function7 = 11101.000...111
  247. }
  248. Case (Package () {17, 18, 19, 20, 21, 22, 23, 24})
  249. {
  250. Store(0x1B, Local0) //Device27-Function0...Function3 = 11011.000...011
  251. }
  252. }
  253. } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
  254. Switch(ToInteger(Arg0))
  255. {
  256. Case (Package () {1, 2, 3})
  257. {
  258. Store(0x1, Local0) //Device1-Function0...Function2 = 00001.000...010
  259. }
  260. #ifndef CPU_CFL
  261. Case (Package () {4})
  262. {
  263. Store(0x6, Local0) //Device6-Function0 = 00110.000
  264. }
  265. #endif
  266. }
  267. } Else {
  268. Store(0xFF, Local0)
  269. }
  270. ADBG("Device no")
  271. ADBG(Local0)
  272. Return(Local0)
  273. } // End of Method(TBTD,1)
  274. //
  275. // Name: TBTF
  276. // Description: Function to return the TBT RP# function no
  277. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  278. // Input: Arg1 -> Tbt port type value from Tbt NVS
  279. // Return: TBT RP# function no
  280. //
  281. Method(TBTF,2)
  282. {
  283. ADBG("TBTF")
  284. If (LEqual(Arg1, DTBT_TYPE_PCH)) {
  285. Switch(ToInteger(Arg0))
  286. {
  287. Case (1)
  288. {
  289. Store(And(\RPA1,0xF), Local0) //Device28-Function0 = 11100.000
  290. }
  291. Case (2)
  292. {
  293. Store(And(\RPA2,0xF), Local0) //Device28-Function1 = 11100.001
  294. }
  295. Case (3)
  296. {
  297. Store(And(\RPA3,0xF), Local0) //Device28-Function2 = 11100.010
  298. }
  299. Case (4)
  300. {
  301. Store(And(\RPA4,0xF), Local0) //Device28-Function3 = 11100.011
  302. }
  303. Case (5)
  304. {
  305. Store(And(\RPA5,0xF), Local0) //Device28-Function4 = 11100.100
  306. }
  307. Case (6)
  308. {
  309. Store(And(\RPA6,0xF), Local0) //Device28-Function5 = 11100.101
  310. }
  311. Case (7)
  312. {
  313. Store(And(\RPA7,0xF), Local0) //Device28-Function6 = 11100.110
  314. }
  315. Case (8)
  316. {
  317. Store(And(\RPA8,0xF), Local0) //Device28-Function7 = 11100.111
  318. }
  319. Case (9)
  320. {
  321. Store(And(\RPA9,0xF), Local0) //Device29-Function0 = 11101.000
  322. }
  323. Case (10)
  324. {
  325. Store(And(\RPAA,0xF), Local0) //Device29-Function1 = 11101.001
  326. }
  327. Case (11)
  328. {
  329. Store(And(\RPAB,0xF), Local0) //Device29-Function2 = 11101.010
  330. }
  331. Case (12)
  332. {
  333. Store(And(\RPAC,0xF), Local0) //Device29-Function3 = 11101.011
  334. }
  335. Case (13)
  336. {
  337. Store(And(\RPAD,0xF), Local0) //Device29-Function4 = 11101.100
  338. }
  339. Case (14)
  340. {
  341. Store(And(\RPAE,0xF), Local0) //Device29-Function5 = 11101.101
  342. }
  343. Case (15)
  344. {
  345. Store(And(\RPAF,0xF), Local0) //Device29-Function6 = 11101.110
  346. }
  347. Case (16)
  348. {
  349. Store(And(\RPAG,0xF), Local0) //Device29-Function7 = 11101.111
  350. }
  351. Case (17)
  352. {
  353. Store(And(\RPAH,0xF), Local0) //Device27-Function0 = 11011.000
  354. }
  355. Case (18)
  356. {
  357. Store(And(\RPAI,0xF), Local0) //Device27-Function1 = 11011.001
  358. }
  359. Case (19)
  360. {
  361. Store(And(\RPAJ,0xF), Local0) //Device27-Function2 = 11011.010
  362. }
  363. Case (20)
  364. {
  365. Store(And(\RPAK,0xF), Local0) //Device27-Function3 = 11011.011
  366. }
  367. Case (21)
  368. {
  369. Store(And(\RPAL,0xF), Local0) //Device27-Function4 = 11011.100
  370. }
  371. Case (22)
  372. {
  373. Store(And(\RPAM,0xF), Local0) //Device27-Function5 = 11011.101
  374. }
  375. Case (23)
  376. {
  377. Store(And(\RPAN,0xF), Local0) //Device27-Function6 = 11011.110
  378. }
  379. Case (24)
  380. {
  381. Store(And(\RPAO,0xF), Local0) //Device27-Function7 = 11011.111
  382. }
  383. }
  384. } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
  385. Switch(ToInteger(Arg0))
  386. {
  387. Case (1)
  388. {
  389. Store(0x0, Local0) //Device1-Function0 = 00001.000
  390. }
  391. Case (2)
  392. {
  393. Store(0x1, Local0) //Device1-Function1 = 00001.001
  394. }
  395. Case (3)
  396. {
  397. Store(0x2, Local0) //Device1-Function2 = 00001.010
  398. }
  399. #ifndef CPU_CFL
  400. Case (4)
  401. {
  402. Store(0x0, Local0) //Device6-Function0 = 00110.000
  403. }
  404. #endif
  405. }
  406. } Else {
  407. Store(0xFF, Local0)
  408. }
  409. ADBG("Function no")
  410. ADBG(Local0)
  411. Return(Local0)
  412. } // End of Method(TBTF,1)
  413. //
  414. // Name: MMRP
  415. // Description: Function to return the Pci base address of TBT rootport
  416. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  417. // Input: Arg1 -> Tbt port type value from Tbt NVS
  418. //
  419. Method(MMRP, 2, Serialized)
  420. {
  421. Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
  422. Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
  423. Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
  424. Return(Local0)
  425. } // End of Method(MMRP)
  426. //
  427. // Name: MMRP
  428. // Description: Function to return the Pci base address of TBT Up stream port
  429. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  430. // Input: Arg1 -> Tbt port type value from Tbt NVS
  431. //
  432. Method(MMTB, 2, Serialized)
  433. {
  434. ADBG("MMTB")
  435. Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
  436. Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
  437. Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
  438. OperationRegion (MMMM, SystemMemory, Local0, 0x1A)
  439. Field (MMMM, AnyAcc, NoLock, Preserve)
  440. {
  441. Offset(0x19),
  442. SBUS, 8
  443. }
  444. Store(SBUS, Local2)
  445. Store(\_SB.PCI0.GPCB(), Local0)
  446. Multiply(Local2, 0x100000, Local2)
  447. Add(Local2, Local0, Local0) // TBT HR US port
  448. ADBG("TBT-US-ADR")
  449. ADBG(Local0)
  450. Return(Local0)
  451. } // End of Method(MMTB, 1, Serialized)
  452. //
  453. // Name: FFTB
  454. // Description: Function to Check for FFFF in TBT PCIe
  455. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  456. // Input: Arg1 -> Tbt port type value from Tbt NVS
  457. // Return: 1 if TBT PCIe space has value FFFF, 0 if not
  458. //
  459. Method(FFTB, 2, Serialized)
  460. {
  461. ADBG("FFTB")
  462. Add(MMTB(Arg0, Arg1), 0x548, Local0)
  463. OperationRegion(PXVD,SystemMemory,Local0,0x08)
  464. Field(PXVD,DWordAcc, NoLock, Preserve)
  465. {
  466. TB2P, 32,
  467. P2TB, 32
  468. }
  469. Store(TB2P, Local1)
  470. If(LEqual(Local1, 0xFFFFFFFF))
  471. {
  472. ADBG("FFTb 1")
  473. Return (1)
  474. }
  475. Else
  476. {
  477. ADBG("FFTb 0")
  478. Return (0)
  479. }
  480. } // End of Method(FFTB)
  481. Name(TDMA, 0x80000000) // Address of Thunderbolt(TM) debug memory buffer, fixed up during POST
  482. Scope(\_GPE)
  483. {
  484. //
  485. //
  486. //OS up Mail Box command execution to host router upstream port each time
  487. //exiting from Sx State .Avoids intermediate
  488. //PCIe Scan by OS during resorce allocation
  489. // Arg0 : PCIe Base address
  490. // Arg1 : Controller Type 0x00 : DTBT
  491. //Developer notes: Called twice
  492. // 1. During OS INIT (booting to OS from S3-S5/Reboot)
  493. // 2. Up on Hot plug
  494. //
  495. Method(OSUP, 2, Serialized)
  496. {
  497. ADBG("OSUP")
  498. Add(Arg0, 0x540, Local0)
  499. OperationRegion(PXVD,SystemMemory,Local0,0x10)
  500. Field(PXVD,DWordAcc, NoLock, Preserve)
  501. {
  502. IT2P, 32,
  503. IP2T, 32,
  504. DT2P, 32,
  505. DP2T, 32
  506. }
  507. Store(100, Local1)
  508. Store(0x0D, DP2T) // Write OS_Up to PCIe2TBT
  509. While(LGreater(Local1, 0))
  510. {
  511. Store(Subtract(Local1, 1), Local1)
  512. Store(DT2P, Local2)
  513. If(LAnd(LEqual(Local2, 0xFFFFFFFF),LEqual(Arg1, DTBT_CONTROLLER)))// Device gone
  514. {
  515. ADBG("Dev gone")
  516. Return(2)
  517. }
  518. If(And(Local2, 1)) // Done
  519. {
  520. ADBG("Cmd acknowledged")
  521. break
  522. }
  523. Sleep(50)
  524. }
  525. If(LEqual(TRWA,1))
  526. {
  527. Store(0xC, DP2T) // Write OSUP to PCIe2TBT
  528. }
  529. Else
  530. {
  531. Store(0x0, DP2T) // Write 0 to PCIe2TBT
  532. }
  533. //Store(0x00, P2TB) // Write 0 to PCIe2TBT
  534. ADBG("End-of-OSUP")
  535. Return(1)
  536. } // End of Method(OSUP, 1, Serialized)
  537. //
  538. // Check for FFFF in TBT
  539. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  540. // Input: Arg1 -> Tbt port type value from Tbt NVS
  541. //
  542. Method(TBFF, 2, Serialized)
  543. {
  544. ADBG("TBFF")
  545. Store(MMTB(Arg0, Arg1), Local0)
  546. OperationRegion (PXVD, SystemMemory, Local0, 0x8)
  547. Field (PXVD, DWordAcc, NoLock, Preserve) {
  548. VEDI, 32, // Vendor/Device ID
  549. CMDR, 32 // CMD register
  550. }
  551. Store(VEDI, Local1)
  552. If (LEqual(Local1, 0xFFFFFFFF)) {
  553. If (LNotEqual(\TWIN, 0)) { // TBT Enumeration is Native mode?
  554. If (LEqual(CMDR, 0xFFFFFFFF)) { // Device Gone
  555. Return (2)// Notify only
  556. }
  557. Return (1)// Exit w/o notify
  558. } Else {
  559. Return (OSUP(Local0, DTBT_CONTROLLER))
  560. }
  561. } Else
  562. {
  563. ADBG("Dev Present")
  564. Return (0)
  565. }
  566. } // End of Method(TBFF, 1, Serialized)
  567. //
  568. // Secondary bus of TBT RP
  569. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  570. // Input: Arg1 -> Tbt port type value from Tbt NVS
  571. //
  572. Method(TSUB, 2, Serialized)
  573. {
  574. ADBG("TSUB")
  575. Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
  576. Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
  577. Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
  578. ADBG("ADR")
  579. ADBG(Local0)
  580. OperationRegion (MMMM, SystemMemory, Local0, 0x1A)
  581. Field (MMMM, AnyAcc, NoLock, Preserve)
  582. {
  583. Offset(0x19),
  584. SBUS, 8
  585. }
  586. ADBG("Sec Bus")
  587. ADBG(SBUS)
  588. Return(SBUS)
  589. } // End of Method(TSUB, 0, Serialized)
  590. //
  591. // Pmem of TBT RP
  592. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  593. // Input: Arg1 -> Tbt port type value from Tbt NVS
  594. //
  595. Method(TSUP, 2, Serialized)
  596. {
  597. ADBG("TSUB")
  598. Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
  599. Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
  600. Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
  601. ADBG("ADR:")
  602. ADBG(Local0)
  603. OperationRegion (MMMM, SystemMemory, Local0, 0x30)
  604. Field (MMMM, AnyAcc, NoLock, Preserve)
  605. {
  606. CMDS, 32,
  607. Offset(0x19),
  608. SBUS, 8,
  609. SBU5, 8,
  610. Offset(0x1C),
  611. SEIO, 32,
  612. MMBL, 32,
  613. PMBL, 32,
  614. }
  615. ADBG("Pmem of TBT RP:")
  616. ADBG(PMBL)
  617. Return(PMBL)
  618. } // End of Method(TSUP, 0, Serialized)
  619. //
  620. // Wait for secondary bus in TBT RP
  621. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  622. // Input: Arg1 -> Tbt port type value from Tbt NVS
  623. //
  624. Method(WSUB, 2, Serialized)
  625. {
  626. ADBG(Concatenate("WSUB=", ToHexString(Arg0)))
  627. ADBG(ToHexString(Timer))
  628. Store(0, Local0)
  629. Store(0, Local1)
  630. While(1)
  631. {
  632. Store(TSUP(Arg0, Arg1), Local1)
  633. If(LGreater(Local1, 0x1FFF1))
  634. {
  635. ADBG("WSUB-Finished")
  636. Break
  637. }
  638. Else
  639. {
  640. Add(Local0, 1, Local0)
  641. If(LGreater(Local0, 1000))
  642. {
  643. Sleep(1000)
  644. ADBG("WSUB-Deadlock")
  645. }
  646. Else
  647. {
  648. Sleep(16)
  649. }
  650. }
  651. }
  652. ADBG(Concatenate("WSUb=", ToHexString(Local1)))
  653. } // End of Method(WSUB)
  654. // Wait for _WAK finished
  655. Method(WWAK)
  656. {
  657. ADBG("WWAK")
  658. Wait(WFEV, 0xFFFF)
  659. Signal(WFEV) // Set it, to enter on next HP
  660. } // End of Method(WWAK)
  661. Method(NTFY, 2, Serialized)
  662. {
  663. ADBG("NTFY")
  664. If(LEqual(NOHP,1))
  665. {
  666. If (LEqual(Arg1, DTBT_TYPE_PCH)) {
  667. Switch(ToInteger(Arg0)) // TBT Selector
  668. {
  669. Case (1)
  670. {
  671. ADBG("Notify RP01")
  672. Notify(\_SB.PCI0.RP01,0)
  673. }
  674. Case (2)
  675. {
  676. ADBG("Notify RP02")
  677. Notify(\_SB.PCI0.RP02,0)
  678. }
  679. Case (3)
  680. {
  681. ADBG("Notify RP03")
  682. Notify(\_SB.PCI0.RP03,0)
  683. }
  684. Case (4)
  685. {
  686. ADBG("Notify RP04")
  687. Notify(\_SB.PCI0.RP04,0)
  688. }
  689. Case (5)
  690. {
  691. ADBG("Notify RP05")
  692. Notify(\_SB.PCI0.RP05,0)
  693. }
  694. Case (6)
  695. {
  696. ADBG("Notify RP06")
  697. Notify(\_SB.PCI0.RP06,0)
  698. }
  699. Case (7)
  700. {
  701. ADBG("Notify RP07")
  702. Notify(\_SB.PCI0.RP07,0)
  703. }
  704. Case (8)
  705. {
  706. ADBG("Notify RP08")
  707. Notify(\_SB.PCI0.RP08,0)
  708. }
  709. Case (9)
  710. {
  711. ADBG("Notify RP09")
  712. Notify(\_SB.PCI0.RP09,0)
  713. }
  714. Case (10)
  715. {
  716. ADBG("Notify RP10")
  717. Notify(\_SB.PCI0.RP10,0)
  718. }
  719. Case (11)
  720. {
  721. ADBG("Notify RP11")
  722. Notify(\_SB.PCI0.RP11,0)
  723. }
  724. Case (12)
  725. {
  726. ADBG("Notify RP12")
  727. Notify(\_SB.PCI0.RP12,0)
  728. }
  729. Case (13)
  730. {
  731. ADBG("Notify RP13")
  732. Notify(\_SB.PCI0.RP13,0)
  733. }
  734. Case (14)
  735. {
  736. ADBG("Notify RP14")
  737. Notify(\_SB.PCI0.RP14,0)
  738. }
  739. Case (15)
  740. {
  741. ADBG("Notify RP15")
  742. Notify(\_SB.PCI0.RP15,0)
  743. }
  744. Case (16)
  745. {
  746. ADBG("Notify RP16")
  747. Notify(\_SB.PCI0.RP16,0)
  748. }
  749. Case (17)
  750. {
  751. ADBG("Notify RP17")
  752. Notify(\_SB.PCI0.RP17,0)
  753. }
  754. Case (18)
  755. {
  756. ADBG("Notify RP18")
  757. Notify(\_SB.PCI0.RP18,0)
  758. }
  759. Case (19)
  760. {
  761. ADBG("Notify RP19")
  762. Notify(\_SB.PCI0.RP19,0)
  763. }
  764. Case (20)
  765. {
  766. ADBG("Notify RP20")
  767. Notify(\_SB.PCI0.RP20,0)
  768. }
  769. Case (21)
  770. {
  771. ADBG("Notify RP21")
  772. Notify(\_SB.PCI0.RP21,0)
  773. }
  774. Case (22)
  775. {
  776. ADBG("Notify RP22")
  777. Notify(\_SB.PCI0.RP22,0)
  778. }
  779. Case (23)
  780. {
  781. ADBG("Notify RP23")
  782. Notify(\_SB.PCI0.RP23,0)
  783. }
  784. Case (24)
  785. {
  786. ADBG("Notify RP24")
  787. Notify(\_SB.PCI0.RP24,0)
  788. }
  789. }//Switch(ToInteger(TBSS)) // TBT Selector
  790. } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
  791. Switch(ToInteger(Arg0))
  792. {
  793. Case (1)
  794. {
  795. ADBG("Notify PEG0")
  796. Notify(\_SB.PCI0.PEG0,0)
  797. }
  798. Case (2)
  799. {
  800. ADBG("Notify PEG1")
  801. Notify(\_SB.PCI0.PEG1,0)
  802. }
  803. Case (3)
  804. {
  805. ADBG("Notify PEG2")
  806. Notify(\_SB.PCI0.PEG2,0)
  807. }
  808. #ifndef CPU_CFL
  809. Case (4)
  810. {
  811. ADBG("Notify PEG3")
  812. Notify(\_SB.PCI0.PEG3,0)
  813. }
  814. #endif
  815. }
  816. }//Switch(ToInteger(TBSS)) // TBT Selector
  817. }//If(NOHP())
  818. P8XH(0,0xC2)
  819. P8XH(1,0xC2)
  820. }// End of Method(NTFY)
  821. //
  822. // TBT BIOS, GPIO 5 filtering,
  823. // Hot plug of 12V USB devices, into TBT host router, cause electrical noise on PCH GPIOs,
  824. // This noise cause false hot-plug events, and negatively influence BIOS assisted hot-plug.
  825. // SKL-PCH GPIO does not implement Glitch Filter logic (refer to GPIO HAS) on any GPIO pad. Native functions have to implement their own digital glitch-filter logic
  826. // if needed. As HW filter was not implemented on SKL PCH, because of that SW workaround should be implemented in BIOS.
  827. // Register 0x544(Bios mailbox) bit 0 definition:
  828. // if BIOS reads bit as 1, BIOS will clear the bit and continue normal flow, if bit is 0 BIOS will exit from method
  829. //
  830. Method(GNIS,2, Serialized)
  831. {
  832. ADBG("GNIS")
  833. If(LEqual(GP5F, 0))
  834. {
  835. ADBG("GNIS_Dis=0")
  836. Return(0)
  837. }
  838. //
  839. // BIOS mailbox command for GPIO filter
  840. //
  841. Add(MMTB(Arg0, Arg1), 0x544, Local0)
  842. OperationRegion(PXVD,SystemMemory,Local0,0x08)
  843. Field(PXVD,DWordAcc, NoLock, Preserve)
  844. {
  845. HPFI, 1,
  846. Offset(0x4),
  847. TB2P, 32
  848. }
  849. Store(TB2P, Local1)
  850. ADBG(Concatenate("TB2P=", ToHexString(Local1)))
  851. If(LEqual(Local1, 0xFFFFFFFF)) // Disconnect?
  852. {
  853. ADBG("GNIS=0")
  854. Return(0)
  855. }
  856. Store(HPFI, Local2)
  857. ADBG(Concatenate("HPFI=", ToHexString(Local2)))
  858. If(LEqual(Local2, 0x01))
  859. {
  860. Store(0x00, HPFI)
  861. ADBG("GNIS=0")
  862. Return(0)
  863. }
  864. // Any other values treated as a GPIO noise
  865. ADBG("GNIS=1")
  866. Return(1)
  867. }
  868. Method(CHKP,2, Serialized)
  869. {
  870. Add(MMTB(Arg0, Arg1), 0x544, Local0)
  871. OperationRegion(PXVE,SystemMemory,Local0,0x08)
  872. Field(PXVE,DWordAcc, NoLock, Preserve)
  873. {
  874. HPFI, 1,
  875. Offset(0x4),
  876. TB2P, 32
  877. }
  878. Store(TB2P, Local1)
  879. And(Local1,BIT29,Local1)
  880. ADBG(Concatenate("Local1=", ToHexString(Local1)))
  881. //ADBG(Concatenate("BIT29=", ToHexString(LAnd(Local1,BIT29))))
  882. If(LEqual(Local1, BIT29))
  883. {
  884. Return(1)
  885. }
  886. Else
  887. {
  888. Return(0)
  889. }
  890. }
  891. //
  892. // Method to Handle enumerate PCIe structure through
  893. // SMI for Thunderbolt(TM) devices
  894. //
  895. Method(XTBT,2, Serialized)
  896. {
  897. ADBG("XTBT")
  898. ADBG("RP :")
  899. ADBG(Arg0)
  900. Store(Arg0, DTCP) // Root port to enumerate
  901. Store(Arg1, DTPT) // Root port Type
  902. If(LEqual(Arg0, RPS0)) {
  903. Store (1, Local0)
  904. } ElseIf (LEqual(Arg0, RPS1)) {
  905. Store (2, Local0)
  906. } Else {
  907. Store (0, Local0)
  908. Return ()
  909. }
  910. If (TRDO) {
  911. ADBG("Durng TBT_ON")
  912. Return ()
  913. }
  914. If (TRD3) {
  915. ADBG("During TBT_OFF")
  916. Return ()
  917. }
  918. WWAK()
  919. WSUB(Arg0, Arg1)
  920. If(GNIS(Arg0, Arg1))
  921. {
  922. Return()
  923. }
  924. OperationRegion(SPRT,SystemIO, 0xB2,2)
  925. Field (SPRT, ByteAcc, Lock, Preserve)
  926. {
  927. SSMP, 8
  928. }
  929. ADBG("TBT-HP-Handler")
  930. Acquire(OSUM, 0xFFFF)
  931. Store(TBFF(Arg0, Arg1), Local1)
  932. If(LEqual(Local1, 1))// Only HR
  933. {
  934. Sleep(16)
  935. Release(OSUM)
  936. ADBG("OS_Up_Received")
  937. Return ()
  938. }
  939. If(LEqual(Local1, 2)) // Disconnect
  940. {
  941. NTFY(Arg0, Arg1)
  942. Sleep(16)
  943. Release(OSUM)
  944. ADBG("Disconnect")
  945. Return ()
  946. }
  947. // HR and EP
  948. If(LEqual(SOHP, 1))
  949. {
  950. // Trigger SMI to enumerate PCIe Structure
  951. ADBG("TBT SW SMI")
  952. Store(21, TBSF)
  953. Store(0xF7, SSMP)
  954. }
  955. NTFY(Arg0, Arg1)
  956. Sleep(16)
  957. Release(OSUM)
  958. ADBG("End-of-XTBT")
  959. } // End of Method(XTBT)
  960. //
  961. // Calling Method to Handle enumerate PCIe structure through
  962. // SMI for Thunderbolt(TM) devices for Tier 1 GPIOs
  963. // Used in Two ways ,
  964. // If CIO GPIO(1 Tier) is Different for the Controllers, this will be used as 1 Tier GPIO Handler for 1st controller
  965. // If CIO GPIO(1 Tier) is Same for all the controllers, this will be used as 1 Tier GPIO Handler for All the controllers
  966. //
  967. Method(ATBT)
  968. {
  969. ADBG("ATBT")
  970. //
  971. // Calling Method to Handle enumerate PCIe structure through
  972. //
  973. If(LEqual(CGST,0)) { // If GPIO is Different for each controller
  974. If(LEqual(RPN0,1))
  975. {
  976. XTBT(RPS0, RPT0)
  977. }
  978. } Else {
  979. If(LEqual(RPN0,1))
  980. {
  981. XTBT(RPS0, RPT0)
  982. }
  983. ElseIf(LEqual(RPN1,1))
  984. {
  985. XTBT(RPS1, RPT1)
  986. }
  987. }
  988. ADBG("End-of-ATBT")
  989. } // End of Method(ATBT)
  990. Method(BTBT)
  991. {
  992. ADBG("BTBT")
  993. //
  994. // Calling Method to Handle enumerate PCIe structure through
  995. //
  996. If(LEqual(CGST,0)) { // If GPIO is Different for each controller
  997. If(LEqual(RPN1,1))
  998. {
  999. XTBT(RPS1, RPT1)
  1000. }
  1001. }
  1002. ADBG("End-of-BTBT")
  1003. } // End of Method(BTBT)
  1004. //
  1005. // Method to call OSPU Mail box command
  1006. // Arg0 : Controller type 0x00 : Discrete 0x80 : Integrated TBT
  1007. // Arg1 : TBT RP Selector / DMA
  1008. // Arg2 : TBT Type (PCH or PEG)
  1009. //
  1010. Method(TINI, 3, Serialized)
  1011. {
  1012. ADBG("TINI")
  1013. If(Lequal (Arg0, DTBT_CONTROLLER))
  1014. {
  1015. //ADBG("DTBT")
  1016. Store(MMRP(Arg1, Arg2), Local0)
  1017. OperationRegion(RP_X,SystemMemory,Local0,0x20)
  1018. Field(RP_X,DWordAcc, NoLock, Preserve)
  1019. {
  1020. REG0, 32,
  1021. REG1, 32,
  1022. REG2, 32,
  1023. REG3, 32,
  1024. REG4, 32,
  1025. REG5, 32,
  1026. REG6, 32,
  1027. REG7, 32
  1028. }
  1029. Store(REG6, Local1)
  1030. Store(0x00F0F000, REG6)
  1031. Store(MMTB(Arg1, Arg2), Local2)
  1032. OSUP(Local2, DTBT_CONTROLLER)
  1033. Store(Local1, REG6)
  1034. }
  1035. ADBG("End-of-TINI")
  1036. }
  1037. } // End of Scope (\_GPE)
  1038. Scope (\_SB)
  1039. {
  1040. //
  1041. // The code needs to be executed for TBT Hotplug Handler event (2-tier GPI GPE event architecture) is presented here
  1042. //
  1043. Method(THDR, 3, Serialized)
  1044. {
  1045. ADBG("THDR")
  1046. \_SB.CAGS(Arg0)
  1047. \_GPE.XTBT(Arg1, Arg2)
  1048. } // End of Method(THDR, 3, Serialized)
  1049. } // End of Scope(\_SB)
  1050. Scope (\_SB)
  1051. {
  1052. //
  1053. // Name: CGWR [Combined GPIO Write]
  1054. // Description: Function to write into GPIO
  1055. // Input: Arg0 -> GpioPad / Expander pin
  1056. // Arg1 -> Value
  1057. // Return: Nothing
  1058. //
  1059. Method(CGWR, 2, Serialized)
  1060. {
  1061. // PCH
  1062. If (CondRefOf(\_SB.SGOV))
  1063. {
  1064. \_SB.SGOV(Arg0, Arg1)
  1065. }
  1066. } // End of Method(CGWR, 4, Serialized)
  1067. //
  1068. // Name: CGRD [Combined GPIO Read]
  1069. // Description: Function to read from GPIO
  1070. // Input: Arg0 -> GpioPad / Expander pin
  1071. // Arg1 -> 0: GPO [GPIO TX State]
  1072. // 1: GPI [GPIO RX State]
  1073. // Return: Value
  1074. //
  1075. Method(CGRD, 2, Serialized)
  1076. {
  1077. Store(1, Local0)
  1078. // PCH
  1079. If (LEqual(Arg1, 0))
  1080. {
  1081. // GPIO TX State
  1082. If (CondRefOf(\_SB.GGOV))
  1083. {
  1084. Store(\_SB.GGOV(Arg0), Local0)
  1085. }
  1086. }
  1087. ElseIf (LEqual(Arg1, 1))
  1088. {
  1089. // GPIO RX State
  1090. If (CondRefOf(\_SB.GGIV))
  1091. {
  1092. Store(\_SB.GGIV(Arg0), Local0)
  1093. }
  1094. }
  1095. Return(Local0)
  1096. } // End of Method(CGRD, 4, Serialized)
  1097. //
  1098. // Name: WRGP [GPIO Write]
  1099. // Description: Function to write into GPIO
  1100. // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo
  1101. // Arg1 -> Value
  1102. // Return: Nothing
  1103. //
  1104. Method(WRGP, 2, Serialized)
  1105. {
  1106. Store(Arg0, Local0)
  1107. Store(Arg0, Local1)
  1108. And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00)
  1109. ShiftRight(Local1, 32, Local1) // High 32 bits (63:32)
  1110. If (LEqual(And(Local0, 0xFF), 1))
  1111. {
  1112. // PCH
  1113. \_SB.CGWR(Local1, Arg1)
  1114. }
  1115. } // End of Method(WRGP, 2, Serialized)
  1116. //
  1117. // Name: RDGP [GPIO Read]
  1118. // Description: Function to write into GPIO
  1119. // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo
  1120. // Arg1 -> In case of PCH Gpio Read {GPIO TX(0)/RX(1) State indicator}
  1121. // Return: Value
  1122. //
  1123. Method(RDGP, 2, Serialized)
  1124. {
  1125. Store(1, Local7)
  1126. Store(Arg0, Local0)
  1127. Store(Arg0, Local1)
  1128. And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00)
  1129. ShiftRight(Local1, 32, Local1) // High 32 bits (63:32)
  1130. If (LEqual(And(Local0, 0xFF), 1))
  1131. {
  1132. // PCH
  1133. Store(\_SB.CGRD(Local1, Arg1), Local7)
  1134. }
  1135. Return(Local7)
  1136. } // End of Method(RDGP, 2, Serialized)
  1137. } // End of Scope(\_SB)
  1138. Scope(\_SB)
  1139. {
  1140. // Asserts/De-asserts TBT force power
  1141. Method(TBFP, 2)
  1142. {
  1143. If(Arg0)
  1144. {
  1145. // Implementation dependent way to assert TBT force power
  1146. If(LEqual(Arg1, 1)) {
  1147. CGWR(FPG0, FP0L)
  1148. }
  1149. Else {
  1150. CGWR(FPG1, FP1L)
  1151. }
  1152. }
  1153. Else
  1154. {
  1155. // Implementation dependent way to de-assert TBT force power
  1156. If(LEqual(Arg1, 1)) {
  1157. CGWR(FPG0, LNot(FP0L))
  1158. }
  1159. Else {
  1160. CGWR(FPG1, LNot(FP1L))
  1161. }
  1162. }
  1163. }
  1164. // WMI ACPI device to control TBT force power
  1165. Device(WMTF)
  1166. {
  1167. // pnp0c14 is pnp id assigned to WMI mapper
  1168. Name(_HID, "PNP0C14")
  1169. Name(_UID, "TBFP")
  1170. Name(_WDG, Buffer() {
  1171. // {86CCFD48-205E-4A77-9C48-2021CBEDE341}
  1172. 0x48, 0xFD, 0xCC, 0x86,
  1173. 0x5E, 0x20,
  1174. 0x77, 0x4A,
  1175. 0x9C, 0x48,
  1176. 0x20, 0x21, 0xCB, 0xED, 0xE3, 0x41,
  1177. 84, 70, // Object Id (TF)
  1178. 1, // Instance Count
  1179. 0x02 // Flags (WMIACPI_REGFLAG_METHOD)
  1180. })
  1181. // Set TBT force power
  1182. // Arg2 is force power value
  1183. Method(WMTF, 3)
  1184. {
  1185. CreateByteField(Arg2,0,FP)
  1186. If(FP)
  1187. {
  1188. TBFP(1, 1)
  1189. }
  1190. Else
  1191. {
  1192. TBFP(0, 1)
  1193. }
  1194. }
  1195. }
  1196. } // End of Scope(\_SB)
  1197. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 1),LEqual(RPS1, 1))))
  1198. {
  1199. Scope(\_SB.PCI0.RP01)
  1200. {
  1201. Device(HRUS)// Host router Upstream port
  1202. {
  1203. Name(_ADR, 0x00000000)
  1204. Method(_RMV)
  1205. {
  1206. Return(TARS)
  1207. } // end _RMV
  1208. }
  1209. }//End of Scope(\_SB.PCI0.RP01)
  1210. }
  1211. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 2),LEqual(RPS1, 2))))
  1212. {
  1213. Scope(\_SB.PCI0.RP02)
  1214. {
  1215. Device(HRUS)// Host router Upstream port
  1216. {
  1217. Name(_ADR, 0x00000000)
  1218. Method(_RMV)
  1219. {
  1220. Return(TARS)
  1221. } // end _RMV
  1222. }
  1223. }//End of Scope(\_SB.PCI0.RP02)
  1224. }
  1225. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 3),LEqual(RPS1, 3))))
  1226. {
  1227. Scope(\_SB.PCI0.RP03)
  1228. {
  1229. Device(HRUS)// Host router Upstream port
  1230. {
  1231. Name(_ADR, 0x00000000)
  1232. Method(_RMV)
  1233. {
  1234. Return(TARS)
  1235. } // end _RMV
  1236. }
  1237. }//End of Scope(\_SB.PCI0.RP03)
  1238. }
  1239. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 4),LEqual(RPS1, 4))))
  1240. {
  1241. Scope(\_SB.PCI0.RP04)
  1242. {
  1243. Device(HRUS)// Host router Upstream port
  1244. {
  1245. Name(_ADR, 0x00000000)
  1246. Method(_RMV)
  1247. {
  1248. Return(TARS)
  1249. } // end _RMV
  1250. }
  1251. }//End of Scope(\_SB.PCI0.RP04)
  1252. }
  1253. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 5),LEqual(RPS1, 5))))
  1254. {
  1255. Scope(\_SB.PCI0.RP05)
  1256. {
  1257. Device(HRUS)// Host router Upstream port
  1258. {
  1259. Name(_ADR, 0x00000000)
  1260. Method(_RMV)
  1261. {
  1262. Return(TARS)
  1263. } // end _RMV
  1264. }
  1265. }//End of Scope(\_SB.PCI0.RP05)
  1266. }
  1267. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 6),LEqual(RPS1, 6))))
  1268. {
  1269. Scope(\_SB.PCI0.RP06)
  1270. {
  1271. Device(HRUS)// Host router Upstream port
  1272. {
  1273. Name(_ADR, 0x00000000)
  1274. Method(_RMV)
  1275. {
  1276. Return(TARS)
  1277. } // end _RMV
  1278. }
  1279. }//End of Scope(\_SB.PCI0.RP06)
  1280. }
  1281. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 7),LEqual(RPS1, 7))))
  1282. {
  1283. Scope(\_SB.PCI0.RP07)
  1284. {
  1285. Device(HRUS)// Host router Upstream port
  1286. {
  1287. Name(_ADR, 0x00000000)
  1288. Method(_RMV)
  1289. {
  1290. Return(TARS)
  1291. } // end _RMV
  1292. }
  1293. }//End of Scope(\_SB.PCI0.RP07)
  1294. }
  1295. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 8),LEqual(RPS1, 8))))
  1296. {
  1297. Scope(\_SB.PCI0.RP08)
  1298. {
  1299. Device(HRUS)// Host router Upstream port
  1300. {
  1301. Name(_ADR, 0x00000000)
  1302. Method(_RMV)
  1303. {
  1304. Return(TARS)
  1305. } // end _RMV
  1306. }
  1307. }//End of Scope(\_SB.PCI0.RP08)
  1308. }
  1309. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 9),LEqual(RPS1, 9))))
  1310. {
  1311. Scope(\_SB.PCI0.RP09)
  1312. {
  1313. Device(HRUS)// Host router Upstream port
  1314. {
  1315. Name(_ADR, 0x00000000)
  1316. Method(_RMV)
  1317. {
  1318. Return(TARS)
  1319. } // end _RMV
  1320. }
  1321. }//End of Scope(\_SB.PCI0.RP09)
  1322. }
  1323. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 10),LEqual(RPS1, 10))))
  1324. {
  1325. Scope(\_SB.PCI0.RP10)
  1326. {
  1327. Device(HRUS)// Host router Upstream port
  1328. {
  1329. Name(_ADR, 0x00000000)
  1330. Method(_RMV)
  1331. {
  1332. Return(TARS)
  1333. } // end _RMV
  1334. }
  1335. }//End of Scope(\_SB.PCI0.RP10)
  1336. }
  1337. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 11),LEqual(RPS1, 11))))
  1338. {
  1339. Scope(\_SB.PCI0.RP11)
  1340. {
  1341. Device(HRUS)// Host router Upstream port
  1342. {
  1343. Name(_ADR, 0x00000000)
  1344. Method(_RMV)
  1345. {
  1346. Return(TARS)
  1347. } // end _RMV
  1348. }
  1349. }//End of Scope(\_SB.PCI0.RP11)
  1350. }
  1351. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 12),LEqual(RPS1, 12))))
  1352. {
  1353. Scope(\_SB.PCI0.RP12)
  1354. {
  1355. Device(HRUS)// Host router Upstream port
  1356. {
  1357. Name(_ADR, 0x00000000)
  1358. Method(_RMV)
  1359. {
  1360. Return(TARS)
  1361. } // end _RMV
  1362. }
  1363. }//End of Scope(\_SB.PCI0.RP12)
  1364. }
  1365. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 13),LEqual(RPS1, 13))))
  1366. {
  1367. Scope(\_SB.PCI0.RP13)
  1368. {
  1369. Device(HRUS)// Host router Upstream port
  1370. {
  1371. Name(_ADR, 0x00000000)
  1372. Method(_RMV)
  1373. {
  1374. Return(TARS)
  1375. } // end _RMV
  1376. }
  1377. }//End of Scope(\_SB.PCI0.RP13)
  1378. }
  1379. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 14),LEqual(RPS1, 14))))
  1380. {
  1381. Scope(\_SB.PCI0.RP14)
  1382. {
  1383. Device(HRUS)// Host router Upstream port
  1384. {
  1385. Name(_ADR, 0x00000000)
  1386. Method(_RMV)
  1387. {
  1388. Return(TARS)
  1389. } // end _RMV
  1390. }
  1391. }//End of Scope(\_SB.PCI0.RP14)
  1392. }
  1393. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 15),LEqual(RPS1, 15))))
  1394. {
  1395. Scope(\_SB.PCI0.RP15)
  1396. {
  1397. Device(HRUS)// Host router Upstream port
  1398. {
  1399. Name(_ADR, 0x00000000)
  1400. Method(_RMV)
  1401. {
  1402. Return(TARS)
  1403. } // end _RMV
  1404. }
  1405. }//End of Scope(\_SB.PCI0.RP15)
  1406. }
  1407. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 16),LEqual(RPS1, 16))))
  1408. {
  1409. Scope(\_SB.PCI0.RP16)
  1410. {
  1411. Device(HRUS)// Host router Upstream port
  1412. {
  1413. Name(_ADR, 0x00000000)
  1414. Method(_RMV)
  1415. {
  1416. Return(TARS)
  1417. } // end _RMV
  1418. }
  1419. }//End of Scope(\_SB.PCI0.RP16)
  1420. }
  1421. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 17),LEqual(RPS1, 17))))
  1422. {
  1423. Scope(\_SB.PCI0.RP17)
  1424. {
  1425. Device(HRUS)// Host router Upstream port
  1426. {
  1427. Name(_ADR, 0x00000000)
  1428. Method(_RMV)
  1429. {
  1430. Return(TARS)
  1431. } // end _RMV
  1432. }
  1433. }//End of Scope(\_SB.PCI0.RP17)
  1434. }
  1435. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 18),LEqual(RPS1, 18))))
  1436. {
  1437. Scope(\_SB.PCI0.RP18)
  1438. {
  1439. Device(HRUS)// Host router Upstream port
  1440. {
  1441. Name(_ADR, 0x00000000)
  1442. Method(_RMV)
  1443. {
  1444. Return(TARS)
  1445. } // end _RMV
  1446. }
  1447. }//End of Scope(\_SB.PCI0.RP18)
  1448. }
  1449. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 19),LEqual(RPS1, 19))))
  1450. {
  1451. Scope(\_SB.PCI0.RP19)
  1452. {
  1453. Device(HRUS)// Host router Upstream port
  1454. {
  1455. Name(_ADR, 0x00000000)
  1456. Method(_RMV)
  1457. {
  1458. Return(TARS)
  1459. } // end _RMV
  1460. }
  1461. }//End of Scope(\_SB.PCI0.RP19)
  1462. }
  1463. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 20),LEqual(RPS1, 20))))
  1464. {
  1465. Scope(\_SB.PCI0.RP20)
  1466. {
  1467. Device(HRUS)// Host router Upstream port
  1468. {
  1469. Name(_ADR, 0x00000000)
  1470. Method(_RMV)
  1471. {
  1472. Return(TARS)
  1473. } // end _RMV
  1474. }
  1475. }//End of Scope(\_SB.PCI0.RP20)
  1476. }
  1477. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 21),LEqual(RPS1, 21))))
  1478. {
  1479. Scope(\_SB.PCI0.PEG0)
  1480. {
  1481. Device(HRUS)// Host router Upstream port
  1482. {
  1483. Name(_ADR, 0x00000000)
  1484. Method(_RMV)
  1485. {
  1486. Return(TARS)
  1487. } // end _RMV
  1488. }
  1489. }//End of Scope(\_SB.PCI0.PEG0)
  1490. }
  1491. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 22),LEqual(RPS1, 22))))
  1492. {
  1493. Scope(\_SB.PCI0.PEG1)
  1494. {
  1495. Device(HRUS)// Host router Upstream port
  1496. {
  1497. Name(_ADR, 0x00000000)
  1498. Method(_RMV)
  1499. {
  1500. Return(TARS)
  1501. } // end _RMV
  1502. }
  1503. }//End of Scope(\_SB.PCI0.PEG1)
  1504. }
  1505. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 23),LEqual(RPS1, 23))))
  1506. {
  1507. Scope(\_SB.PCI0.PEG2)
  1508. {
  1509. Device(HRUS)// Host router Upstream port
  1510. {
  1511. Name(_ADR, 0x00000000)
  1512. Method(_RMV)
  1513. {
  1514. Return(TARS)
  1515. } // end _RMV
  1516. }
  1517. }//End of Scope(\_SB.PCI0.PEG2)
  1518. }
  1519. Scope(\_SB)
  1520. {
  1521. //
  1522. // Name: PERB
  1523. // Description: Function to read a Byte from PCIE-MMIO
  1524. // Input: Arg0 -> PCIE base address
  1525. // Arg1 -> Bus
  1526. // Arg2 -> Device
  1527. // Arg3 -> Function
  1528. // Arg4 -> Register offset
  1529. // Return: Byte data read from PCIE-MMIO
  1530. //
  1531. Method(PERB,5,Serialized)
  1532. {
  1533. ADBG("PERB")
  1534. Store(Arg0, Local7)
  1535. Or(Local7, ShiftLeft(Arg1, 20), Local7)
  1536. Or(Local7, ShiftLeft(Arg2, 15), Local7)
  1537. Or(Local7, ShiftLeft(Arg3, 12), Local7)
  1538. Or(Local7, Arg4, Local7)
  1539. OperationRegion(PCI0, SystemMemory, Local7, 1)
  1540. Field(PCI0, ByteAcc,NoLock,Preserve)
  1541. {
  1542. TEMP, 8
  1543. }
  1544. Return(TEMP)
  1545. } // End of Method(PERB,5,Serialized)
  1546. //
  1547. // Name: PEWB
  1548. // Description: Function to write a Byte into PCIE-MMIO
  1549. // Input: Arg0 -> PCIE base address
  1550. // Arg1 -> Bus
  1551. // Arg2 -> Device
  1552. // Arg3 -> Function
  1553. // Arg4 -> Register offset
  1554. // Arg5 -> Data
  1555. // Return: Nothing
  1556. //
  1557. Method(PEWB,6,Serialized)
  1558. {
  1559. ADBG("PEWB")
  1560. Store(Arg0, Local7)
  1561. Or(Local7, ShiftLeft(Arg1, 20), Local7)
  1562. Or(Local7, ShiftLeft(Arg2, 15), Local7)
  1563. Or(Local7, ShiftLeft(Arg3, 12), Local7)
  1564. Or(Local7, Arg4, Local7)
  1565. OperationRegion(PCI0, SystemMemory, Local7, 1)
  1566. Field(PCI0, ByteAcc,NoLock,Preserve)
  1567. {
  1568. TEMP, 8
  1569. }
  1570. Store(Arg5,TEMP)
  1571. } // End of Method(PEWB,6,Serialized)
  1572. //
  1573. // Name: PERW
  1574. // Description: Function to read a Word from PCIE-MMIO
  1575. // Input: Arg0 -> PCIE base address
  1576. // Arg1 -> Bus
  1577. // Arg2 -> Device
  1578. // Arg3 -> Function
  1579. // Arg4 -> Register offset
  1580. // Return: Word data read from PCIE-MMIO
  1581. //
  1582. Method(PERW,5,Serialized)
  1583. {
  1584. ADBG("PERW")
  1585. Store(Arg0, Local7)
  1586. Or(Local7, ShiftLeft(Arg1, 20), Local7)
  1587. Or(Local7, ShiftLeft(Arg2, 15), Local7)
  1588. Or(Local7, ShiftLeft(Arg3, 12), Local7)
  1589. Or(Local7, Arg4, Local7)
  1590. OperationRegion(PCI0, SystemMemory, Local7, 2)
  1591. Field(PCI0, ByteAcc,NoLock,Preserve)
  1592. {
  1593. TEMP, 16
  1594. }
  1595. Return(TEMP)
  1596. } // End of Method(PERW,5,Serialized)
  1597. //
  1598. // Name: PEWW
  1599. // Description: Function to write a Word into PCIE-MMIO
  1600. // Input: Arg0 -> PCIE base address
  1601. // Arg1 -> Bus
  1602. // Arg2 -> Device
  1603. // Arg3 -> Function
  1604. // Arg4 -> Register offset
  1605. // Arg5 -> Data
  1606. // Return: Nothing
  1607. //
  1608. Method(PEWW,6,Serialized)
  1609. {
  1610. ADBG("PEWW")
  1611. Store(Arg0, Local7)
  1612. Or(Local7, ShiftLeft(Arg1, 20), Local7)
  1613. Or(Local7, ShiftLeft(Arg2, 15), Local7)
  1614. Or(Local7, ShiftLeft(Arg3, 12), Local7)
  1615. Or(Local7, Arg4, Local7)
  1616. OperationRegion(PCI0, SystemMemory, Local7, 2)
  1617. Field(PCI0, ByteAcc,NoLock,Preserve)
  1618. {
  1619. TEMP, 16
  1620. }
  1621. Store(Arg5,TEMP)
  1622. } // End of Method(PEWW,6,Serialized)
  1623. //
  1624. // Name: PERD
  1625. // Description: Function to read a Dword from PCIE-MMIO
  1626. // Input: Arg0 -> PCIE base address
  1627. // Arg1 -> Bus
  1628. // Arg2 -> Device
  1629. // Arg3 -> Function
  1630. // Arg4 -> Register offset
  1631. // Return: Dword data read from PCIE-MMIO
  1632. //
  1633. Method(PERD,5,Serialized)
  1634. {
  1635. ADBG("PERD")
  1636. Store(Arg0, Local7)
  1637. Or(Local7, ShiftLeft(Arg1, 20), Local7)
  1638. Or(Local7, ShiftLeft(Arg2, 15), Local7)
  1639. Or(Local7, ShiftLeft(Arg3, 12), Local7)
  1640. Or(Local7, Arg4, Local7)
  1641. OperationRegion(PCI0, SystemMemory, Local7, 4)
  1642. Field(PCI0, ByteAcc,NoLock,Preserve)
  1643. {
  1644. TEMP, 32
  1645. }
  1646. Return(TEMP)
  1647. } // End of Method(PERD,5,Serialized)
  1648. //
  1649. // Name: PEWD
  1650. // Description: Function to write a Dword into PCIE-MMIO
  1651. // Input: Arg0 -> PCIE base address
  1652. // Arg1 -> Bus
  1653. // Arg2 -> Device
  1654. // Arg3 -> Function
  1655. // Arg4 -> Register offset
  1656. // Arg5 -> Data
  1657. // Return: Nothing
  1658. //
  1659. Method(PEWD,6,Serialized)
  1660. {
  1661. ADBG("PEWD")
  1662. Store(Arg0, Local7)
  1663. Or(Local7, ShiftLeft(Arg1, 20), Local7)
  1664. Or(Local7, ShiftLeft(Arg2, 15), Local7)
  1665. Or(Local7, ShiftLeft(Arg3, 12), Local7)
  1666. Or(Local7, Arg4, Local7)
  1667. OperationRegion(PCI0, SystemMemory, Local7, 4)
  1668. Field(PCI0, ByteAcc,NoLock,Preserve)
  1669. {
  1670. TEMP, 32
  1671. }
  1672. Store(Arg5,TEMP)
  1673. } // End of Method(PEWD,6,Serialized)
  1674. //
  1675. // Name: STDC
  1676. // Description: Function to get Standard Capability Register Offset
  1677. // Input: Arg0 -> PCIE base address
  1678. // Arg1 -> Bus
  1679. // Arg2 -> Device
  1680. // Arg3 -> Function
  1681. // Arg4 -> Capability ID
  1682. // Return: Capability Register Offset data
  1683. //
  1684. Method(STDC,5,Serialized)
  1685. {
  1686. ADBG("STDC")
  1687. //Check for Referenced device is present or not
  1688. Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x00), Local7) //Vendor ID register
  1689. If(LEqual(Local7, 0xFFFF))
  1690. {
  1691. ADBG("Referenced device is not present")
  1692. Return(0)
  1693. }
  1694. Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x06), Local0) //Device Status register
  1695. If (LEqual(And(Local0, 16), 0)) //Bit4 - Capabilities List
  1696. {
  1697. //No Capabilities linked list is available
  1698. ADBG("No Capabilities linked list is available")
  1699. Return(0)
  1700. }
  1701. //Local1 is for storing CapabilityID
  1702. //Local2 is for storing CapabilityPtr
  1703. Store(PERB(Arg0, Arg1, Arg2, Arg3, 0x34), Local2) //CapabilityPtr
  1704. While(1)
  1705. {
  1706. And(Local2, 0xFC, Local2) //Each capability must be DWORD aligned
  1707. If(LEqual(Local2, 0)) //A pointer value of 00h is used to indicate the last capability in the list
  1708. {
  1709. ADBG("Capability ID is not found")
  1710. Return(0)
  1711. }
  1712. Store(PERB(Arg0, Arg1, Arg2, Arg3, Local2), Local1) //CapabilityID
  1713. If(LEqual(Arg4, Local1)) //CapabilityID match
  1714. {
  1715. ADBG("Capability ID is found")
  1716. ADBG("Capability Offset : ")
  1717. ADBG(Local2)
  1718. Return(Local2)
  1719. }
  1720. Store(PERB(Arg0, Arg1, Arg2, Arg3, Add(Local2, 1)), Local2) //CapabilityPtr
  1721. Return(0)
  1722. }
  1723. } // End of Method(STDC,5,Serialized)
  1724. } // End Scope(\_SB)