Rtd3SptPcieTbt.asl 12 KB

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  1. /** @file
  2. ACPI RTD3 SSDT table for SPT PCIe
  3. Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #define PID_ICC 0xDC
  7. #define R_PCH_PCR_ICC_MSKCKRQ 0x100C ///< Mask Control CLKREQ
  8. External(PCRA,MethodObj)
  9. External(PCRO,MethodObj)
  10. External(\MMRP, MethodObj)
  11. External(\MMTB, MethodObj)
  12. External(\TRDO, IntObj)
  13. External(\TRD3, IntObj)
  14. External(\TBPE, IntObj)
  15. External(\TOFF, IntObj)
  16. External(\TBSE, IntObj)
  17. External(\TBOD, IntObj)
  18. External(\TBRP, IntObj)
  19. External(\TBHR, IntObj)
  20. External(\RTBC, IntObj)
  21. External(\TBCD, IntObj)
  22. Name(G2SD, 0) // Go2Sx done, set by GO2S, cleaned by _ON
  23. Name(WKEN, 0)
  24. Method(_S0W, 0)
  25. {
  26. /// This method returns the lowest D-state supported by PCIe root port during S0 state
  27. ///- PMEs can be generated from D3hot for ULT
  28. Return(4)
  29. /** @defgroup pcie_s0W PCIE _S0W **/
  30. } // End _S0W
  31. Method (_DSD, 0) {
  32. Return (
  33. Package () {
  34. ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"),
  35. Package () {
  36. Package (2) {"HotPlugSupportInD3", 1},
  37. }
  38. }
  39. ) // End of Return ()
  40. }
  41. Method(_DSW, 3)
  42. {
  43. /// This method is used to enable/disable wake from PCIe (WKEN)
  44. If (LGreaterEqual(Arg1, 1)) { /// If entering Sx, need to disable WAKE# from generating runtime PME
  45. /// Also set 2 to TOFF.
  46. Store(0, WKEN)
  47. Store (2, TOFF)
  48. } Else { /// If Staying in S0
  49. If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake
  50. { ///- Set PME
  51. Store(1, WKEN)
  52. Store (1, TOFF)
  53. } Else { ///- Disable runtime PME, either because staying in D0 or disabling wake
  54. Store(0, WKEN)
  55. Store(0, TOFF)
  56. }
  57. }
  58. /** @defgroup pcie_dsw PCIE _DSW **/
  59. } // End _DSW
  60. PowerResource(PXP, 0, 0)
  61. {
  62. /// Define the PowerResource for PCIe slot
  63. /// Method: _STA(), _ON(), _OFF()
  64. /** @defgroup pcie_pxp PCIE Power Resource **/
  65. Method(_STA, 0)
  66. {
  67. Return(PSTA())
  68. } /** @defgroup pcie_sta PCIE _STA method **/
  69. Method(_ON) /// Turn on core power to PCIe Slot
  70. {
  71. Store(1, TRDO)
  72. PON()
  73. Store(0, TRDO)
  74. } /** @defgroup pcie_on PCIE _ON method **/
  75. Method(_OFF) /// Turn off core power to PCIe Slot
  76. {
  77. Store(1, TRD3)
  78. POFF()
  79. Store(0, TRD3)
  80. } // End of Method_OFF
  81. } // End PXP
  82. Method(PSTA, 0)
  83. {
  84. /// Returns the status of PCIe slot core power
  85. // detect power pin status
  86. if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) {
  87. if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
  88. if(LEqual(\_SB.GGOV(DeRefOf(Index(PWRG, 2))),DeRefOf(Index(PWRG, 3)))){
  89. Return (1)
  90. } Else {
  91. Return (0)
  92. }
  93. } // GPIO mode
  94. if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode
  95. if(LEqual(\_SB.PCI0.GEXP.GEPS(DeRefOf(Index(PWRG, 1)),DeRefOf(Index(PWRG, 2))),DeRefOf(Index(PWRG, 3)))){
  96. Return (1)
  97. } Else {
  98. Return (0)
  99. }
  100. } // IOEX mode
  101. }
  102. // detect reset pin status
  103. if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) {
  104. if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
  105. if(LEqual(\_SB.GGOV(DeRefOf(Index(RSTG, 2))),DeRefOf(Index(RSTG, 3)))){
  106. Return (1)
  107. } Else {
  108. Return (0)
  109. }
  110. } // GPIO mode
  111. if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode
  112. if(LEqual(\_SB.PCI0.GEXP.GEPS(DeRefOf(Index(RSTG, 1)),DeRefOf(Index(RSTG, 2))),DeRefOf(Index(RSTG, 3)))){
  113. Return (1)
  114. } Else {
  115. Return (0)
  116. }
  117. } // IOEX mode
  118. }
  119. Return (0)
  120. } /** @defgroup pcie_sta PCIE _STA method **/
  121. Method (SXEX, 0, Serialized) {
  122. Store(\MMTB(TBSE), Local7)
  123. OperationRegion(TBDI, SystemMemory, Local7, 0x550)// TBT HR PCICFG MMIO
  124. Field(TBDI,DWordAcc, NoLock, Preserve) {
  125. DIVI, 32,
  126. CMDR, 32,
  127. Offset(0x548),
  128. TB2P, 32,
  129. P2TB, 32
  130. }
  131. Store(100, Local1)
  132. Store(0x09, P2TB) // Write SX_EXIT_TBT_CONNECTED to PCIe2TBT
  133. While (LGreater(Local1, 0)) {
  134. Store(Subtract(Local1, 1), Local1)
  135. Store(TB2P, Local2)
  136. If (LEqual(Local2, 0xFFFFFFFF)) { // Device gone
  137. Return()
  138. }
  139. If (And(Local2, 1)) { // Done
  140. break
  141. }
  142. Sleep(5)
  143. }
  144. Store(0x0, P2TB) // Write 0 to PCIe2TBT
  145. // Fast Link bring-up flow
  146. Store(500, Local1)
  147. While (LGreater(Local1, 0)) {
  148. Store(Subtract(Local1, 1), Local1)
  149. Store(TB2P, Local2)
  150. If (LEqual(Local2, 0xFFFFFFFF)) {// Device gone
  151. Return()
  152. }
  153. If (LNotEqual(DIVI, 0xFFFFFFFF)) {
  154. break
  155. }
  156. Sleep(10)
  157. }
  158. } // End of Method(SXEX, 0, Serialized)
  159. Method(PON) /// Turn on core power to PCIe Slot
  160. {
  161. Store(\MMRP(\TBSE), Local7)
  162. OperationRegion(L23P,SystemMemory,Local7,0xE4)
  163. Field(L23P,WordAcc, NoLock, Preserve)
  164. {
  165. Offset(0xA4),// PMCSR
  166. PSD0, 2, // PowerState
  167. Offset(0xE2),// 0xE2, RPPGEN - Root Port Power Gating Enable
  168. , 2,
  169. L2TE, 1, // 2, L23_Rdy Entry Request (L23ER)
  170. L2TR, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
  171. }
  172. Store(\MMTB(\TBSE), Local6)
  173. OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR PCICFG MMIO
  174. Field(TBDI,DWordAcc, NoLock, Preserve) {
  175. DIVI, 32,
  176. CMDR, 32,
  177. Offset(0xA4),
  178. TBPS, 2, // PowerState of TBT
  179. Offset(0x548),
  180. TB2P, 32,
  181. P2TB, 32
  182. }
  183. Store(0, TOFF)
  184. // Check RTD3 power enable, if already ON, no need to execute sx_exit
  185. If (TBPE) {
  186. Return()
  187. }
  188. Store(0,G2SD)
  189. If (\RTBC) {
  190. /// de-assert CLK_REQ MSK
  191. if(LNotEqual(DeRefOf(Index(SCLK, 0)),0)) { // if power gating enabled
  192. PCRA(PID_ICC,R_PCH_PCR_ICC_MSKCKRQ,Not(DeRefOf(Index(SCLK, 1)))) // And ~SCLK to clear bit
  193. }
  194. Sleep(\TBCD)
  195. }
  196. /// Turn ON Power for PCIe Slot
  197. if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enabled
  198. if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
  199. \_SB.SGOV(DeRefOf(Index(PWRG, 2)),DeRefOf(Index(PWRG, 3)))
  200. Store(1, TBPE)
  201. Sleep(PEP0) /// Sleep for programmable delay
  202. }
  203. if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode
  204. \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(PWRG, 1)),DeRefOf(Index(PWRG, 2)),DeRefOf(Index(PWRG, 3)))
  205. Store(1, TBPE)
  206. Sleep(PEP0) /// Sleep for programmable delay
  207. }
  208. }
  209. /// De-Assert Reset Pin
  210. if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { // if reset pin enabled
  211. if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
  212. \_SB.SGOV(DeRefOf(Index(RSTG, 2)),DeRefOf(Index(RSTG, 3)))
  213. }
  214. if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode
  215. \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(RSTG, 1)),DeRefOf(Index(RSTG, 2)),DeRefOf(Index(RSTG, 3)))
  216. }
  217. }
  218. /// Clear DLSULPPGE, then set L23_Rdy to Detect Transition (L23R2DT)
  219. Store(0, DPGE)
  220. Store(1, L2TR)
  221. Sleep(16)
  222. Store(0, Local0)
  223. /// Wait up to 12 ms for transition to Detect
  224. While(L2TR) {
  225. If(Lgreater(Local0, 4)) // Debug - Wait for 5 ms
  226. {
  227. Break
  228. }
  229. Sleep(16)
  230. Increment(Local0)
  231. }
  232. /// Once in Detect, wait up to 124 ms for Link Active (typically happens in under 70ms)
  233. /// Worst case per PCIe spec from Detect to Link Active is:
  234. /// 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config (24+2+2+2+2)
  235. Store(1, DPGE)
  236. Store(0, Local0)
  237. While(LEqual(LASX,0)) {
  238. If(Lgreater(Local0, 8))
  239. {
  240. Break
  241. }
  242. Sleep(16)
  243. Increment(Local0)
  244. }
  245. Store(0, LEDM) /// Set PCIEDBG.DMIL1EDM (324[3]) = 0
  246. // TBT special sleep.
  247. Store(PSD0, Local1)
  248. Store(0, PSD0)// D0
  249. Store(20, Local2) // Poll for TBT, up to 200 ms
  250. While (LGreater(Local2, 0)) {
  251. Store(Subtract(Local2, 1), Local2)
  252. Store(TB2P, Local3)
  253. If (LNotEqual(Local3, 0xFFFFFFFF)) { // Done
  254. break
  255. }
  256. Sleep(10)
  257. }
  258. If (LLessEqual(Local2, 0)) {
  259. }
  260. SXEX()
  261. Store(Local1, PSD0) // Back to Local1
  262. } /** @defgroup pcie_on PCIE _ON method **/
  263. Method(POFF) { /// Turn off core power to PCIe Slot
  264. If (LEqual(TOFF, 0)) {
  265. Return()
  266. }
  267. Store(\MMRP(\TBSE), Local7)
  268. OperationRegion(L23P, SystemMemory, Local7, 0xE4)
  269. Field(L23P,WordAcc, NoLock, Preserve)
  270. {
  271. Offset(0xA4),// PMCSR
  272. PSD0, 2, // PowerState
  273. Offset(0xE2),// 0xE2, RPPGEN - Root Port Power Gating Enable
  274. , 2,
  275. L2TE, 1, // 2, L23_Rdy Entry Request (L23ER)
  276. L2TR, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)
  277. }
  278. Store(\MMTB(TBSE), Local6)
  279. OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR PCICFG MMIO
  280. Field(TBDI,DWordAcc, NoLock, Preserve) {
  281. DIVI, 32,
  282. CMDR, 32,
  283. Offset(0xA4),
  284. TBPS, 2, // PowerState of TBT
  285. Offset(0x548),
  286. TB2P, 32,
  287. P2TB, 32
  288. }
  289. Store(PSD0, Local1)
  290. Store(0, PSD0)// D0
  291. Store(P2TB, Local3)
  292. If (Lgreater(TOFF, 1)) {
  293. Sleep(10)
  294. Store(Local1, PSD0) // Back to Local1
  295. Return()
  296. }
  297. Store(0, TOFF)
  298. Store(Local1, PSD0) // Back to Local1
  299. /// Set L23_Rdy Entry Request (L23ER)
  300. Store(1, L2TE)
  301. Sleep(16)
  302. Store(0, Local0)
  303. While(L2TE) {
  304. If(Lgreater(Local0, 4)) /// Debug - Wait for 5 ms
  305. {
  306. Break
  307. }
  308. Sleep(16)
  309. Increment(Local0)
  310. }
  311. Store(1, LEDM) /// PCIEDBG.DMIL1EDM (324[3]) = 1
  312. /// Assert Reset Pin
  313. if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { // if reset pin enabled
  314. if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode
  315. \_SB.SGOV(DeRefOf(Index(RSTG, 2)),Xor(DeRefOf(Index(RSTG, 3)),1))
  316. }
  317. if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode
  318. \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(RSTG, 1)),DeRefOf(Index(RSTG, 2)),Xor(DeRefOf(Index(RSTG, 3)),1))
  319. }
  320. }
  321. If (\RTBC) {
  322. /// assert CLK_REQ MSK
  323. if(LNotEqual(DeRefOf(Index(SCLK, 0)),0)) { // if power gating enabled
  324. PCRO(PID_ICC,R_PCH_PCR_ICC_MSKCKRQ,DeRefOf(Index(SCLK, 1))) // Or SCLK to set bit
  325. Sleep(16)
  326. }
  327. }
  328. /// Power OFF for TBT
  329. if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enabled
  330. if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode
  331. \_SB.SGOV(DeRefOf(Index(PWRG, 2)),Xor(DeRefOf(Index(PWRG, 3)),1))
  332. }
  333. if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode
  334. \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(PWRG, 1)),DeRefOf(Index(PWRG, 2)),Xor(DeRefOf(Index(PWRG, 3)),1))
  335. }
  336. }
  337. Store(0, TBPE)
  338. Store(1, LDIS) /// Set Link Disable
  339. Store(0, LDIS) /// Toggle link disable
  340. /// enable WAKE
  341. If (WKEN) {
  342. If (LNotEqual(DeRefOf(Index(WAKG, 0)),0)) { // if power gating enabled
  343. If (LEqual(DeRefOf(Index(WAKG, 0)),1)) { // GPIO mode
  344. \_SB.SGOV(DeRefOf(Index(WAKG, 2)),DeRefOf(Index(WAKG, 3)))
  345. \_SB.SHPO(DeRefOf(Index(WAKG, 2)), 0) // set gpio ownership to ACPI(0=ACPI mode, 1=GPIO mode)
  346. }
  347. If (LEqual(DeRefOf(Index(WAKG, 0)),2)) { // IOEX mode
  348. \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(WAKG, 1)),DeRefOf(Index(WAKG, 2)),DeRefOf(Index(WAKG, 3)))
  349. }
  350. }
  351. }
  352. Sleep(\TBOD)
  353. /** @defgroup pcie_off PCIE _OFF method **/
  354. } // End of Method_OFF
  355. Name(_PR0, Package(){PXP})
  356. Name(_PR3, Package(){PXP})