CPU.asl 11 KB

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  1. /** @file
  2. ACPI DSDT table
  3. Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. Scope(\_PR)
  7. {
  8. Processor(PR00, // Unique name for Processor 0.
  9. 1, // Unique ID for Processor 0.
  10. 0x1810, // P_BLK address = ACPIBASE + 10h.
  11. 6) // P_BLK length = 6 bytes.
  12. {}
  13. Processor(PR01, // Unique name for Processor 1.
  14. 2, // Unique ID for Processor 1.
  15. 0x1810, // P_BLK address = ACPIBASE + 10h.
  16. 6) // P_BLK length = 6 bytes.
  17. {}
  18. Processor(PR02, // Unique name for Processor 2.
  19. 3, // Unique ID for Processor 2.
  20. 0x1810, // P_BLK address = ACPIBASE + 10h.
  21. 6) // P_BLK length = 6 bytes.
  22. {}
  23. Processor(PR03, // Unique name for Processor 3.
  24. 4, // Unique ID for Processor 3.
  25. 0x1810, // P_BLK address = ACPIBASE + 10h.
  26. 6) // P_BLK length = 6 bytes.
  27. {}
  28. Processor(PR04, // Unique name for Processor 4.
  29. 5, // Unique ID for Processor 4.
  30. 0x1810, // P_BLK address = ACPIBASE + 10h.
  31. 6) // P_BLK length = 6 bytes.
  32. {}
  33. Processor(PR05, // Unique name for Processor 5.
  34. 6, // Unique ID for Processor 5.
  35. 0x1810, // P_BLK address = ACPIBASE + 10h.
  36. 6) // P_BLK length = 6 bytes.
  37. {}
  38. Processor(PR06, // Unique name for Processor 6.
  39. 7, // Unique ID for Processor 6.
  40. 0x1810, // P_BLK address = ACPIBASE + 10h.
  41. 6) // P_BLK length = 6 bytes.
  42. {}
  43. Processor(PR07, // Unique name for Processor 7.
  44. 8, // Unique ID for Processor 7.
  45. 0x1810, // P_BLK address = ACPIBASE + 10h.
  46. 6) // P_BLK length = 6 bytes.
  47. {}
  48. Processor(PR08, // Unique name for Processor 8.
  49. 9, // Unique ID for Processor 8.
  50. 0x1810, // P_BLK address = ACPIBASE + 10h.
  51. 6) // P_BLK length = 6 bytes.
  52. {}
  53. Processor(PR09, // Unique name for Processor 9.
  54. 10, // Unique ID for Processor 9.
  55. 0x1810, // P_BLK address = ACPIBASE + 10h.
  56. 6) // P_BLK length = 6 bytes.
  57. {}
  58. Processor(PR10, // Unique name for Processor 10.
  59. 11, // Unique ID for Processor 10.
  60. 0x1810, // P_BLK address = ACPIBASE + 10h.
  61. 6) // P_BLK length = 6 bytes.
  62. {}
  63. Processor(PR11, // Unique name for Processor 11.
  64. 12, // Unique ID for Processor 11.
  65. 0x1810, // P_BLK address = ACPIBASE + 10h.
  66. 6) // P_BLK length = 6 bytes.
  67. {}
  68. Processor(PR12, // Unique name for Processor 12.
  69. 13, // Unique ID for Processor 12.
  70. 0x1810, // P_BLK address = ACPIBASE + 10h.
  71. 6) // P_BLK length = 6 bytes.
  72. {}
  73. Processor(PR13, // Unique name for Processor 13.
  74. 14, // Unique ID for Processor 13.
  75. 0x1810, // P_BLK address = ACPIBASE + 10h.
  76. 6) // P_BLK length = 6 bytes.
  77. {}
  78. Processor(PR14, // Unique name for Processor 14.
  79. 15, // Unique ID for Processor 14.
  80. 0x1810, // P_BLK address = ACPIBASE + 10h.
  81. 6) // P_BLK length = 6 bytes.
  82. {}
  83. Processor(PR15, // Unique name for Processor 15.
  84. 16, // Unique ID for Processor 15.
  85. 0x1810, // P_BLK address = ACPIBASE + 10h.
  86. 6) // P_BLK length = 6 bytes.
  87. {}
  88. } // End Scope(\_PR)
  89. //
  90. // _CPC (Continuous Performance Control) Package declaration
  91. // Package
  92. // {
  93. // NumEntries, // Integer
  94. // Revision, // Integer
  95. // HighestPerformance, // Generic Register Descriptor
  96. // NominalPerformance, // Generic Register Descriptor
  97. // LowestNonlinearPerformance, // Generic Register Descriptor
  98. // LowestPerformance, // Generic Register Descriptor
  99. // GuaranteedPerformanceRegister, // Generic Register Descriptor
  100. // DesiredPerformanceRegister, // Generic Register Descriptor
  101. // MinimumPerformanceRegister, // Generic Register Descriptor
  102. // MaximumPerformanceRegister, // Generic Register Descriptor
  103. // PerformanceReductionToleranceRegister,// Generic Register Descriptor
  104. // TimeWindowRegister, // Generic Register Descriptor
  105. // CounterWraparoundTime, // Generic Register Descriptor
  106. // NominalCounterRegister, // Generic Register Descriptor
  107. // DeliveredCounterRegister, // Generic Register Descriptor
  108. // PerformanceLimitedRegister, // Generic Register Descriptor
  109. // EnableRegister // Generic Register Descriptor
  110. // }
  111. //
  112. Scope(\_PR.PR00)
  113. {
  114. Name(CPC2, Package()
  115. {
  116. 21, // Number of entries
  117. 02, // Revision
  118. //
  119. // Describe processor capabilities
  120. //
  121. ResourceTemplate() {Register(FFixedHW, 8, 0, 0x771, 4)}, // HighestPerformance
  122. ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)}, // Nominal Performance - Maximum Non Turbo Ratio
  123. ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest nonlinear Performance
  124. ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, // LowestPerformance
  125. ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, // Guaranteed Performance
  126. ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired PerformanceRegister
  127. ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum PerformanceRegister
  128. ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum PerformanceRegister
  129. ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Performance ReductionToleranceRegister (Null)
  130. ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time window register(Null)
  131. ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter wrap around time(Null)
  132. ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference counter register (PPERF)
  133. ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered counter register (APERF)
  134. ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performance limited register
  135. ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable register
  136. 1, // Autonomous selection enable register (Exclusively autonomous)
  137. ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, // Autonomous activity window register
  138. ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, // Autonomous energy performance preference register
  139. 0 // Reference performance (not supported)
  140. })
  141. Name(CPOC, Package()
  142. {
  143. 21, // Number of entries
  144. 02, // Revision
  145. //
  146. // Describe processor capabilities
  147. //
  148. 255, // HighestPerformance
  149. ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)}, // Nominal Performance - Maximum Non Turbo Ratio
  150. ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest nonlinear Performance
  151. ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, // LowestPerformance
  152. ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, // Guaranteed Performance
  153. ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired PerformanceRegister
  154. ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum PerformanceRegister
  155. ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum PerformanceRegister
  156. ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Performance ReductionToleranceRegister (Null)
  157. ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time window register(Null)
  158. ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter wrap around time(Null)
  159. ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference counter register (PPERF)
  160. ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered counter register (APERF)
  161. ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performance limited register
  162. ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable register
  163. 1, // Autonomous selection enable register (Exclusively autonomous)
  164. ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, // Autonomous activity window register
  165. ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, // Autonomous energy performance preference register
  166. 0 // Reference performance (not supported)
  167. })
  168. }// end Scope(\_PR.PR00)
  169. #ifndef SPS_SUPPORT // SPS is using Processor Aggregator Device different way
  170. Scope(\_SB)
  171. {
  172. // The Processor Aggregator Device provides a control point that enables the platform to perform
  173. // specific processor configuration and control that applies to all processors in the platform.
  174. Device (PAGD)
  175. {
  176. Name (_HID, "ACPI000C") // Processor Aggregator Device
  177. // _STA (Status)
  178. //
  179. // This object returns the current status of a device.
  180. //
  181. // Arguments: (0)
  182. // None
  183. // Return Value:
  184. // An Integer containing a device status bitmap:
  185. // Bit 0 - Set if the device is present.
  186. // Bit 1 - Set if the device is enabled and decoding its resources.
  187. // Bit 2 - Set if the device should be shown in the UI.
  188. // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics).
  189. // Bit 4 - Set if the battery is present.
  190. // Bits 5-31 - Reserved (must be cleared).
  191. //
  192. Method(_STA)
  193. {
  194. If(\_OSI("Processor Aggregator Device")){
  195. Return (0x0F) // Processor Aggregator Device is supported by this OS.
  196. } Else {
  197. Return (0) // No support in this OS.
  198. }
  199. }
  200. // _PUR (Processor Utilization Request)
  201. //
  202. // The _PUR object is an optional object that may be declared under the Processor Aggregator Device
  203. // and provides a means for the platform to indicate to OSPM the number of logical processors
  204. // to be idled. OSPM evaluates the _PUR object as a result of the processing of a Notify event
  205. // on the Processor Aggregator device object of type 0x80.
  206. //
  207. // Arguments: (0)
  208. // None
  209. // Return Value:
  210. // Package
  211. //
  212. Name (_PUR, Package() // Requests a number of logical processors to be placed in an idle state.
  213. {
  214. 1, // RevisionID, Integer: Current value is 1
  215. 0 // NumProcessors, Integer
  216. })
  217. } // end Device(PAGD)
  218. }// end Scope(\_SB)
  219. #endif // ndef SPS_SUPPORT