DwEmmc.h 6.7 KB

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  1. /** @file
  2. *
  3. * WARNING:
  4. * This driver fails to follow the UEFI driver model without a good
  5. * reason, and only remains in the tree because it is still used by
  6. * a small number of platforms. It will be removed when no longer used.
  7. *
  8. * Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
  9. *
  10. * SPDX-License-Identifier: BSD-2-Clause-Patent
  11. *
  12. **/
  13. #ifndef __DWEMMC_H__
  14. #define __DWEMMC_H__
  15. #include <Protocol/EmbeddedGpio.h>
  16. // DW MMC Registers
  17. #define DWEMMC_CTRL ((PcdDwDxeBaseAddress) + 0x000)
  18. #define DWEMMC_PWREN ((PcdDwDxeBaseAddress) + 0x004)
  19. #define DWEMMC_CLKDIV ((PcdDwDxeBaseAddress) + 0x008)
  20. #define DWEMMC_CLKSRC ((PcdDwDxeBaseAddress) + 0x00c)
  21. #define DWEMMC_CLKENA ((PcdDwDxeBaseAddress) + 0x010)
  22. #define DWEMMC_TMOUT ((PcdDwDxeBaseAddress) + 0x014)
  23. #define DWEMMC_CTYPE ((PcdDwDxeBaseAddress) + 0x018)
  24. #define DWEMMC_BLKSIZ ((PcdDwDxeBaseAddress) + 0x01c)
  25. #define DWEMMC_BYTCNT ((PcdDwDxeBaseAddress) + 0x020)
  26. #define DWEMMC_INTMASK ((PcdDwDxeBaseAddress) + 0x024)
  27. #define DWEMMC_CMDARG ((PcdDwDxeBaseAddress) + 0x028)
  28. #define DWEMMC_CMD ((PcdDwDxeBaseAddress) + 0x02c)
  29. #define DWEMMC_RESP0 ((PcdDwDxeBaseAddress) + 0x030)
  30. #define DWEMMC_RESP1 ((PcdDwDxeBaseAddress) + 0x034)
  31. #define DWEMMC_RESP2 ((PcdDwDxeBaseAddress) + 0x038)
  32. #define DWEMMC_RESP3 ((PcdDwDxeBaseAddress) + 0x03c)
  33. #define DWEMMC_RINTSTS ((PcdDwDxeBaseAddress) + 0x044)
  34. #define DWEMMC_STATUS ((PcdDwDxeBaseAddress) + 0x048)
  35. #define DWEMMC_FIFOTH ((PcdDwDxeBaseAddress) + 0x04c)
  36. #define DWEMMC_TCBCNT ((PcdDwDxeBaseAddress) + 0x05c)
  37. #define DWEMMC_TBBCNT ((PcdDwDxeBaseAddress) + 0x060)
  38. #define DWEMMC_DEBNCE ((PcdDwDxeBaseAddress) + 0x064)
  39. #define DWEMMC_HCON ((PcdDwDxeBaseAddress) + 0x070)
  40. #define DWEMMC_UHSREG ((PcdDwDxeBaseAddress) + 0x074)
  41. #define DWEMMC_BMOD ((PcdDwDxeBaseAddress) + 0x080)
  42. #define DWEMMC_DBADDR ((PcdDwDxeBaseAddress) + 0x088)
  43. #define DWEMMC_IDSTS ((PcdDwDxeBaseAddress) + 0x08c)
  44. #define DWEMMC_IDINTEN ((PcdDwDxeBaseAddress) + 0x090)
  45. #define DWEMMC_DSCADDR ((PcdDwDxeBaseAddress) + 0x094)
  46. #define DWEMMC_BUFADDR ((PcdDwDxeBaseAddress) + 0x098)
  47. #define DWEMMC_CARDTHRCTL ((PcdDwDxeBaseAddress) + 0X100)
  48. #define DWEMMC_DATA ((PcdDwDxeBaseAddress) + 0X200)
  49. #define CMD_UPDATE_CLK 0x80202000
  50. #define CMD_START_BIT (1 << 31)
  51. #define MMC_8BIT_MODE (1 << 16)
  52. #define BIT_CMD_RESPONSE_EXPECT (1 << 6)
  53. #define BIT_CMD_LONG_RESPONSE (1 << 7)
  54. #define BIT_CMD_CHECK_RESPONSE_CRC (1 << 8)
  55. #define BIT_CMD_DATA_EXPECTED (1 << 9)
  56. #define BIT_CMD_READ (0 << 10)
  57. #define BIT_CMD_WRITE (1 << 10)
  58. #define BIT_CMD_BLOCK_TRANSFER (0 << 11)
  59. #define BIT_CMD_STREAM_TRANSFER (1 << 11)
  60. #define BIT_CMD_SEND_AUTO_STOP (1 << 12)
  61. #define BIT_CMD_WAIT_PRVDATA_COMPLETE (1 << 13)
  62. #define BIT_CMD_STOP_ABORT_CMD (1 << 14)
  63. #define BIT_CMD_SEND_INIT (1 << 15)
  64. #define BIT_CMD_UPDATE_CLOCK_ONLY (1 << 21)
  65. #define BIT_CMD_READ_CEATA_DEVICE (1 << 22)
  66. #define BIT_CMD_CCS_EXPECTED (1 << 23)
  67. #define BIT_CMD_ENABLE_BOOT (1 << 24)
  68. #define BIT_CMD_EXPECT_BOOT_ACK (1 << 25)
  69. #define BIT_CMD_DISABLE_BOOT (1 << 26)
  70. #define BIT_CMD_MANDATORY_BOOT (0 << 27)
  71. #define BIT_CMD_ALTERNATE_BOOT (1 << 27)
  72. #define BIT_CMD_VOLT_SWITCH (1 << 28)
  73. #define BIT_CMD_USE_HOLD_REG (1 << 29)
  74. #define BIT_CMD_START (1 << 31)
  75. #define DWEMMC_INT_EBE (1 << 15) /* End-bit Err */
  76. #define DWEMMC_INT_SBE (1 << 13) /* Start-bit Err */
  77. #define DWEMMC_INT_HLE (1 << 12) /* Hardware-lock Err */
  78. #define DWEMMC_INT_FRUN (1 << 11) /* FIFO UN/OV RUN */
  79. #define DWEMMC_INT_DRT (1 << 9) /* Data timeout */
  80. #define DWEMMC_INT_RTO (1 << 8) /* Response timeout */
  81. #define DWEMMC_INT_DCRC (1 << 7) /* Data CRC err */
  82. #define DWEMMC_INT_RCRC (1 << 6) /* Response CRC err */
  83. #define DWEMMC_INT_RXDR (1 << 5)
  84. #define DWEMMC_INT_TXDR (1 << 4)
  85. #define DWEMMC_INT_DTO (1 << 3) /* Data trans over */
  86. #define DWEMMC_INT_CMD_DONE (1 << 2)
  87. #define DWEMMC_INT_RE (1 << 1)
  88. #define DWEMMC_IDMAC_DES0_DIC (1 << 1)
  89. #define DWEMMC_IDMAC_DES0_LD (1 << 2)
  90. #define DWEMMC_IDMAC_DES0_FS (1 << 3)
  91. #define DWEMMC_IDMAC_DES0_CH (1 << 4)
  92. #define DWEMMC_IDMAC_DES0_ER (1 << 5)
  93. #define DWEMMC_IDMAC_DES0_CES (1 << 30)
  94. #define DWEMMC_IDMAC_DES0_OWN (1 << 31)
  95. #define DWEMMC_IDMAC_DES1_BS1(x) ((x) & 0x1fff)
  96. #define DWEMMC_IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13)
  97. #define DWEMMC_IDMAC_SWRESET (1 << 0)
  98. #define DWEMMC_IDMAC_FB (1 << 1)
  99. #define DWEMMC_IDMAC_ENABLE (1 << 7)
  100. #define EMMC_FIX_RCA 6
  101. /* bits in MMC0_CTRL */
  102. #define DWEMMC_CTRL_RESET (1 << 0)
  103. #define DWEMMC_CTRL_FIFO_RESET (1 << 1)
  104. #define DWEMMC_CTRL_DMA_RESET (1 << 2)
  105. #define DWEMMC_CTRL_INT_EN (1 << 4)
  106. #define DWEMMC_CTRL_DMA_EN (1 << 5)
  107. #define DWEMMC_CTRL_IDMAC_EN (1 << 25)
  108. #define DWEMMC_CTRL_RESET_ALL (DWEMMC_CTRL_RESET | DWEMMC_CTRL_FIFO_RESET | DWEMMC_CTRL_DMA_RESET)
  109. #define DWEMMC_STS_DATA_BUSY (1 << 9)
  110. #define DWEMMC_FIFO_TWMARK(x) (x & 0xfff)
  111. #define DWEMMC_FIFO_RWMARK(x) ((x & 0x1ff) << 16)
  112. #define DWEMMC_DMA_BURST_SIZE(x) ((x & 0x7) << 28)
  113. #define DWEMMC_CARD_RD_THR(x) ((x & 0xfff) << 16)
  114. #define DWEMMC_CARD_RD_THR_EN (1 << 0)
  115. #define DWEMMC_GET_HDATA_WIDTH(x) (((x) >> 7) & 0x7)
  116. #endif // __DWEMMC_H__