TbtCommonLib.h 7.3 KB

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  1. /**@file
  2. Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef _TBT_COMMON_LIB_H_
  6. #define _TBT_COMMON_LIB_H_
  7. #include <Library/BaseLib.h>
  8. #include <Library/PciSegmentLib.h>
  9. #include <Library/GpioExpanderLib.h>
  10. #define DTBT_CONTROLLER 0x00
  11. #define DTBT_TYPE_PCH 0x01
  12. #define DTBT_TYPE_PEG 0x02
  13. #define TBT2PCIE_DTBT_R 0x548
  14. #define PCIE2TBT_DTBT_R 0x54C
  15. //
  16. // Thunderbolt FW OS capability
  17. //
  18. #define NO_OS_NATIVE_SUPPORT 0
  19. #define OS_NATIVE_SUPPORT_ONLY 1
  20. #define OS_NATIVE_SUPPORT_RTD3 2
  21. #define DTBT_SAVE_STATE_OFFSET BIT0 // Bits 0-3 is for DTBT (only bit 0 is in use)
  22. /**
  23. Get Tbt2Pcie Register Offset
  24. @retval Register Register Variable
  25. **/
  26. #define GET_TBT2PCIE_REGISTER_ADDRESS(Segment, Bus, Device, Function, RegisterAddress) \
  27. RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, TBT2PCIE_DTBT_R); \
  28. /**
  29. Get Pcie2Tbt Register Offset
  30. @retval Register Register Variable
  31. **/
  32. #define GET_PCIE2TBT_REGISTER_ADDRESS(Segment, Bus, Device, Function, RegisterAddress) \
  33. RegisterAddress = PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, PCIE2TBT_DTBT_R); \
  34. #define PCIE2TBT_VLD_B BIT0
  35. #define TBT2PCIE_DON_R BIT0
  36. #define TBT_MAIL_BOX_DELAY (100*1000)
  37. #define TBT_5S_TIMEOUT 50
  38. #define TBT_1S_TIMEOUT 10
  39. #define TBT_3S_TIMEOUT 30
  40. #define PCIE2TBT_GO2SX (0x02 << 1)
  41. #define PCIE2TBT_GO2SX_NO_WAKE (0x03 << 1)
  42. #define PCIE2TBT_SX_EXIT_TBT_CONNECTED (0x04 << 1)
  43. #define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED (0x05 << 1)
  44. #define PCIE2TBT_OS_UP (0x06 << 1)
  45. #define PCIE2TBT_SET_SECURITY_LEVEL (0x08 << 1)
  46. #define PCIE2TBT_GET_SECURITY_LEVEL (0x09 << 1)
  47. #define PCIE2TBT_CM_AUTH_MODE_ENTER (0x10 << 1)
  48. #define PCIE2TBT_CM_AUTH_MODE_EXIT (0x11 << 1)
  49. #define PCIE2TBT_BOOT_ON (0x18 << 1)
  50. #define PCIE2TBT_BOOT_OFF (0x19 << 1)
  51. #define PCIE2TBT_USB_ON (0x19 << 1)
  52. #define PCIE2TBT_GET_ENUMERATION_METHOD (0x1A << 1)
  53. #define PCIE2TBT_SET_ENUMERATION_METHOD (0x1B << 1)
  54. #define PCIE2TBT_POWER_CYCLE (0x1C << 1)
  55. #define PCIE2TBT_PREBOOTACL (0x1E << 1)
  56. #define CONNECT_TOPOLOGY_COMMAND (0x1F << 1)
  57. #define RESET_HR_BIT BIT0
  58. #define ENUMERATE_HR_BIT BIT1
  59. #define AUTO 0x0
  60. //
  61. //Thunder Bolt Device IDs
  62. //
  63. //
  64. // Alpine Ridge HR device IDs
  65. //
  66. #define AR_HR_2C 0x1576
  67. #define AR_HR_4C 0x1578
  68. #define AR_XHC 0x15B5
  69. #define AR_XHC_4C 0x15B6
  70. #define AR_HR_LP 0x15C0
  71. //
  72. // Alpine Ridge C0 HR device IDs
  73. //
  74. #define AR_HR_C0_2C 0x15DA
  75. #define AR_HR_C0_4C 0x15D3
  76. //
  77. // Titan Ridge HR device IDs
  78. //
  79. #define TR_HR_2C 0x15E7
  80. #define TR_HR_4C 0x15EA
  81. //
  82. //End of Thunderbolt(TM) Device IDs
  83. //
  84. typedef struct _DEV_ID {
  85. UINT8 Segment;
  86. UINT8 Bus;
  87. UINT8 Dev;
  88. UINT8 Fun;
  89. } DEV_ID;
  90. //@todo Seems to only be used by Platform/TBT/Smm/TbtSmm.inf
  91. //@todo should refactor this to only be present in that driver
  92. //@todo also definitions like this should never be in a .h file anyway
  93. //@todo this is a quick hack to get things compiling for now
  94. #ifdef __GNUC__
  95. #pragma GCC diagnostic warning "-Wunused-variable"
  96. #endif
  97. /**
  98. Based on the Security Mode Selection, BIOS drives FORCE_PWR.
  99. @param[in] GpioNumber
  100. @param[in] Value
  101. **/
  102. VOID
  103. ForceDtbtPower(
  104. IN UINT8 GpioAccessType,
  105. IN UINT8 Expander,
  106. IN UINT32 GpioNumber,
  107. IN BOOLEAN Value
  108. );
  109. /**
  110. Get Security Level.
  111. @param[in] Bus Bus number for Host Router (DTBT)
  112. @param[in] Device Device number for Host Router (DTBT)
  113. @param[in] Function Function number for Host Router (DTBT)
  114. @param[in] Timeout Time out with 100 ms garnularity
  115. **/
  116. UINT8
  117. GetSecLevel (
  118. IN UINT8 Bus,
  119. IN UINT8 Device,
  120. IN UINT8 Function,
  121. IN UINT8 Command,
  122. IN UINT32 Timeout
  123. );
  124. /**
  125. Set Security Level.
  126. @param[in] Data Security State
  127. @param[in] Bus Bus number for Host Router (DTBT)
  128. @param[in] Device Device number for Host Router (DTBT)
  129. @param[in] Function Function number for Host Router (DTBT)
  130. @param[in] Timeout Time out with 100 ms garnularity
  131. **/
  132. BOOLEAN
  133. SetSecLevel (
  134. IN UINT8 Data,
  135. IN UINT8 Bus,
  136. IN UINT8 Device,
  137. IN UINT8 Function,
  138. IN UINT8 Command,
  139. IN UINT32 Timeout
  140. );
  141. /**
  142. Execute TBT Mail Box Command
  143. @param[in] Command TBT Command
  144. @param[in] Bus Bus number for Host Router (DTBT)
  145. @param[in] Device Device number for Host Router (DTBT)
  146. @param[in] Function Function number for Host Router (DTBT)
  147. @param[in] Timeout Time out with 100 ms garnularity
  148. @Retval true if command executes succesfully
  149. **/
  150. BOOLEAN
  151. TbtSetPcie2TbtCommand(
  152. IN UINT8 Command,
  153. IN UINT8 Bus,
  154. IN UINT8 Device,
  155. IN UINT8 Function,
  156. IN UINT32 Timeout
  157. );
  158. /**
  159. Check connected TBT controller is supported or not by DeviceID
  160. @param[in] DeviceID DeviceID of of TBT controller
  161. @retval TRUE Valid DeviceID
  162. @retval FALSE Invalid DeviceID
  163. **/
  164. BOOLEAN
  165. IsTbtHostRouter (
  166. IN UINT16 DeviceID
  167. );
  168. /**
  169. Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Port physical Number
  170. @param[in] RpNumber Root port physical number. (0-based)
  171. @param[out] RpDev Return corresponding root port device number.
  172. @param[out] RpFun Return corresponding root port function number.
  173. @retval EFI_SUCCESS Root port device and function is retrieved
  174. **/
  175. EFI_STATUS
  176. EFIAPI
  177. GetDTbtRpDevFun(
  178. IN BOOLEAN Type,
  179. IN UINTN RpNumber,
  180. OUT UINTN *RpDev,
  181. OUT UINTN *RpFunc
  182. );
  183. /**
  184. Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
  185. @param[in] CommandOffsetAddress Tbt2Pcie Register Address
  186. @param[in] TimeOut Time out with 100 ms garnularity
  187. @param[in] Tbt2PcieDone Wait condition (wait for Bit to Clear/Set)
  188. @param[out] *Tbt2PcieValue Function Register value
  189. **/
  190. BOOLEAN
  191. InternalWaitforCommandCompletion (
  192. IN UINT64 CommandOffsetAddress,
  193. IN UINT32 TimeOut,
  194. IN BOOLEAN Tbt2PcieDone,
  195. OUT UINT32 *Tbt2PcieValue
  196. );
  197. VOID
  198. GetRootporttoSetResourcesforTbt (
  199. IN UINTN RpIndex,
  200. OUT UINT8 *RsvdExtraBusNum,
  201. OUT UINT16 *RsvdPcieMegaMem,
  202. OUT UINT8 *PcieMemAddrRngMax,
  203. OUT UINT16 *RsvdPciePMegaMem,
  204. OUT UINT8 *PciePMemAddrRngMax,
  205. OUT BOOLEAN *SetResourceforTbt
  206. );
  207. #endif