PciHotPlug.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351
  1. /** @file
  2. Performs specific PCI-EXPRESS device resource configuration.
  3. Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. //
  7. // Statements that include other files
  8. //
  9. #include "PciHotPlug.h"
  10. #include <Ppi/SiPolicy.h>
  11. #include <TbtBoardInfo.h>
  12. #include <Library/PchPcieRpLib.h>
  13. #include <Library/TbtCommonLib.h>
  14. #define PCIE_NUM (20)
  15. #define PEG_NUM (3)
  16. #define PADDING_BUS (1)
  17. #define PADDING_NONPREFETCH_MEM (1)
  18. #define PADDING_PREFETCH_MEM (1)
  19. #define PADDING_IO (1)
  20. #define PADDING_NUM (PADDING_BUS + PADDING_NONPREFETCH_MEM + PADDING_PREFETCH_MEM + PADDING_IO)
  21. GLOBAL_REMOVE_IF_UNREFERENCED EFI_HPC_LOCATION mPcieLocation[PCIE_NUM + PEG_NUM];
  22. GLOBAL_REMOVE_IF_UNREFERENCED UINTN mHpcCount = 0;
  23. GLOBAL_REMOVE_IF_UNREFERENCED PCIE_HOT_PLUG_DEVICE_PATH mHotplugPcieDevicePathTemplate = {
  24. ACPI,
  25. PCI(0xFF, 0xFF), // Dummy Device no & Function no
  26. END
  27. };
  28. /**
  29. Entry point for the driver.
  30. This routine reads the PlatformType GPI on FWH and produces a protocol
  31. to be consumed by the chipset driver to effect those settings.
  32. @param[in] ImageHandle An image handle.
  33. @param[in] SystemTable A pointer to the system table.
  34. @retval EFI_SUCCESS.
  35. **/
  36. EFI_STATUS
  37. EFIAPI
  38. PciHotPlug (
  39. IN EFI_HANDLE ImageHandle,
  40. IN EFI_SYSTEM_TABLE *SystemTable
  41. )
  42. {
  43. EFI_STATUS Status;
  44. PCI_HOT_PLUG_INSTANCE *PciHotPlug;
  45. UINTN Index;
  46. UINTN RpDev;
  47. UINTN RpFunc;
  48. PCIE_HOT_PLUG_DEVICE_PATH *HotplugPcieDevicePath;
  49. UINT32 PcieRootPortHpeData = 0;
  50. DEBUG ((DEBUG_INFO, "PciHotPlug Entry\n"));
  51. PcieRootPortHpeData = PcdGet32 (PcdPchPcieRootPortHpe);
  52. //
  53. // PCH Rootports Hotplug device path creation
  54. //
  55. for (Index = 0; Index < PCIE_NUM; Index++) {
  56. if (((PcieRootPortHpeData >> Index) & BIT0) == BIT0) { // Check the Rootport no's hotplug is set
  57. Status = GetPchPcieRpDevFun (Index, &RpDev, &RpFunc); // Get the actual device/function no corresponding to the Rootport no provided
  58. ASSERT_EFI_ERROR (Status);
  59. HotplugPcieDevicePath = NULL;
  60. HotplugPcieDevicePath = AllocatePool (sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
  61. ASSERT (HotplugPcieDevicePath != NULL);
  62. if (HotplugPcieDevicePath == NULL) {
  63. return EFI_OUT_OF_RESOURCES;
  64. }
  65. CopyMem (HotplugPcieDevicePath, &mHotplugPcieDevicePathTemplate, sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
  66. HotplugPcieDevicePath->PciRootPortNode.Device = (UINT8) RpDev; // Update real Device no
  67. HotplugPcieDevicePath->PciRootPortNode.Function = (UINT8) RpFunc; // Update real Function no
  68. mPcieLocation[mHpcCount].HpcDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
  69. mPcieLocation[mHpcCount].HpbDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
  70. mHpcCount++;
  71. DEBUG ((DEBUG_INFO, "(%02d) PciHotPlug (PCH RP#) : Bus 0x00, Device 0x%x, Function 0x%x is added to the Hotplug Device Path list \n", mHpcCount, RpDev, RpFunc));
  72. }
  73. }
  74. PciHotPlug = AllocatePool (sizeof (PCI_HOT_PLUG_INSTANCE));
  75. ASSERT (PciHotPlug != NULL);
  76. if (PciHotPlug == NULL) {
  77. return EFI_OUT_OF_RESOURCES;
  78. }
  79. //
  80. // Initialize driver private data.
  81. //
  82. ZeroMem (PciHotPlug, sizeof (PCI_HOT_PLUG_INSTANCE));
  83. PciHotPlug->Signature = PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE;
  84. PciHotPlug->HotPlugInitProtocol.GetRootHpcList = GetRootHpcList;
  85. PciHotPlug->HotPlugInitProtocol.InitializeRootHpc = InitializeRootHpc;
  86. PciHotPlug->HotPlugInitProtocol.GetResourcePadding = GetResourcePadding;
  87. Status = gBS->InstallProtocolInterface (
  88. &PciHotPlug->Handle,
  89. &gEfiPciHotPlugInitProtocolGuid,
  90. EFI_NATIVE_INTERFACE,
  91. &PciHotPlug->HotPlugInitProtocol
  92. );
  93. ASSERT_EFI_ERROR (Status);
  94. return EFI_SUCCESS;
  95. }
  96. /**
  97. This procedure returns a list of Root Hot Plug controllers that require
  98. initialization during boot process
  99. @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
  100. @param[out] HpcCount The number of Root HPCs returned.
  101. @param[out] HpcList The list of Root HPCs. HpcCount defines the number of elements in this list.
  102. @retval EFI_SUCCESS.
  103. **/
  104. EFI_STATUS
  105. EFIAPI
  106. GetRootHpcList (
  107. IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
  108. OUT UINTN *HpcCount,
  109. OUT EFI_HPC_LOCATION **HpcList
  110. )
  111. {
  112. *HpcCount = mHpcCount;
  113. *HpcList = mPcieLocation;
  114. return EFI_SUCCESS;
  115. }
  116. /**
  117. This procedure Initializes one Root Hot Plug Controller
  118. This process may casue initialization of its subordinate buses
  119. @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
  120. @param[in] HpcDevicePath The Device Path to the HPC that is being initialized.
  121. @param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
  122. @param[in] Event The event that should be signaled when the Hot Plug Controller initialization is complete. Set to NULL if the caller wants to wait until the entire initialization process is complete. The event must be of the type EFI_EVT_SIGNAL.
  123. @param[out] HpcState The state of the Hot Plug Controller hardware. The type EFI_Hpc_STATE is defined in section 3.1.
  124. @retval EFI_SUCCESS.
  125. **/
  126. EFI_STATUS
  127. EFIAPI
  128. InitializeRootHpc (
  129. IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
  130. IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
  131. IN UINT64 HpcPciAddress,
  132. IN EFI_EVENT Event, OPTIONAL
  133. OUT EFI_HPC_STATE *HpcState
  134. )
  135. {
  136. if (Event) {
  137. gBS->SignalEvent (Event);
  138. }
  139. *HpcState = EFI_HPC_STATE_INITIALIZED;
  140. return EFI_SUCCESS;
  141. }
  142. /**
  143. Returns the resource padding required by the PCI bus that is controlled by the specified Hot Plug Controller.
  144. @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol. initialized.
  145. @param[in] HpcDevicePath The Device Path to the Hot Plug Controller.
  146. @param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
  147. @param[out] HpcState The state of the Hot Plug Controller hardware. The type EFI_HPC_STATE is defined in section 3.1.
  148. @param[out] Padding This is the amount of resource padding required by the PCI bus under the control of the specified Hpc. Since the caller does not know the size of this buffer, this buffer is allocated by the callee and freed by the caller.
  149. @param[out] Attribute Describes how padding is accounted for.
  150. @retval EFI_SUCCESS.
  151. **/
  152. EFI_STATUS
  153. EFIAPI
  154. GetResourcePadding (
  155. IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
  156. IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
  157. IN UINT64 HpcPciAddress,
  158. OUT EFI_HPC_STATE *HpcState,
  159. OUT VOID **Padding,
  160. OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes
  161. )
  162. {
  163. EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource;
  164. EFI_STATUS Status;
  165. UINT8 RsvdExtraBusNum = 0;
  166. UINT16 RsvdPcieMegaMem = 10;
  167. UINT8 PcieMemAddrRngMax = 0;
  168. UINT16 RsvdPciePMegaMem = 10;
  169. UINT8 PciePMemAddrRngMax = 0;
  170. UINT8 RsvdTbtExtraBusNum = 0;
  171. UINT16 RsvdTbtPcieMegaMem = 10;
  172. UINT8 TbtPcieMemAddrRngMax = 0;
  173. UINT16 RsvdTbtPciePMegaMem = 10;
  174. UINT8 TbtPciePMemAddrRngMax = 0;
  175. UINT8 RsvdPcieKiloIo = 4;
  176. BOOLEAN SetResourceforTbt = FALSE;
  177. UINTN RpIndex;
  178. UINTN RpDev;
  179. UINTN RpFunc;
  180. DEBUG ((DEBUG_INFO, "GetResourcePadding : Start \n"));
  181. PaddingResource = AllocatePool (PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
  182. ASSERT (PaddingResource != NULL);
  183. if (PaddingResource == NULL) {
  184. return EFI_OUT_OF_RESOURCES;
  185. }
  186. *Padding = (VOID *) PaddingResource;
  187. RpDev = (UINTN) ((HpcPciAddress >> 16) & 0xFF);
  188. RpFunc = (UINTN) ((HpcPciAddress >> 8) & 0xFF);
  189. // Get the actual Rootport no corresponding to the device/function no provided
  190. if (RpDev == SA_PEG_DEV_NUM) {
  191. // PEG
  192. RpIndex = PCIE_NUM + RpFunc;
  193. DEBUG ((DEBUG_INFO, "GetResourcePadding : PEG Rootport no %02d Bus 0x00, Device 0x%x, Function 0x%x \n", (RpIndex-PCIE_NUM), RpDev, RpFunc));
  194. } else {
  195. // PCH
  196. Status = GetPchPcieRpNumber (RpDev, RpFunc, &RpIndex);
  197. DEBUG ((DEBUG_INFO, "GetResourcePadding : PCH Rootport no %02d Bus 0x00, Device 0x%x, Function 0x%x \n", RpIndex, RpDev, RpFunc));
  198. }
  199. GetRootporttoSetResourcesforTbt(RpIndex, &RsvdTbtExtraBusNum, &RsvdTbtPcieMegaMem ,&TbtPcieMemAddrRngMax ,&RsvdTbtPciePMegaMem ,&TbtPciePMemAddrRngMax, &SetResourceforTbt);
  200. if (SetResourceforTbt) {
  201. RsvdExtraBusNum = RsvdTbtExtraBusNum;
  202. RsvdPcieMegaMem = RsvdTbtPcieMegaMem;
  203. PcieMemAddrRngMax = TbtPcieMemAddrRngMax;
  204. RsvdPciePMegaMem = RsvdTbtPciePMegaMem;
  205. PciePMemAddrRngMax = TbtPciePMemAddrRngMax;
  206. }
  207. //
  208. // Padding for bus
  209. //
  210. ZeroMem (PaddingResource, PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
  211. *Attributes = EfiPaddingPciBus;
  212. PaddingResource->Desc = 0x8A;
  213. PaddingResource->Len = 0x2B;
  214. PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
  215. PaddingResource->GenFlag = 0x0;
  216. PaddingResource->SpecificFlag = 0;
  217. PaddingResource->AddrRangeMin = 0;
  218. PaddingResource->AddrRangeMax = 0;
  219. PaddingResource->AddrLen = RsvdExtraBusNum;
  220. //
  221. // Padding for non-prefetchable memory
  222. //
  223. PaddingResource++;
  224. PaddingResource->Desc = 0x8A;
  225. PaddingResource->Len = 0x2B;
  226. PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
  227. PaddingResource->GenFlag = 0x0;
  228. if (SetResourceforTbt) {
  229. PaddingResource->AddrSpaceGranularity = 32;
  230. } else {
  231. PaddingResource->AddrSpaceGranularity = 32;
  232. }
  233. PaddingResource->SpecificFlag = 0;
  234. //
  235. // Pad non-prefetchable
  236. //
  237. PaddingResource->AddrRangeMin = 0;
  238. PaddingResource->AddrLen = RsvdPcieMegaMem * 0x100000;
  239. if (SetResourceforTbt) {
  240. PaddingResource->AddrRangeMax = (1 << PcieMemAddrRngMax) - 1;
  241. } else {
  242. PaddingResource->AddrRangeMax = 1;
  243. }
  244. //
  245. // Padding for prefetchable memory
  246. //
  247. PaddingResource++;
  248. PaddingResource->Desc = 0x8A;
  249. PaddingResource->Len = 0x2B;
  250. PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
  251. PaddingResource->GenFlag = 0x0;
  252. if (SetResourceforTbt) {
  253. PaddingResource->AddrSpaceGranularity = 32;
  254. } else {
  255. PaddingResource->AddrSpaceGranularity = 32;
  256. }
  257. PaddingResource->SpecificFlag = 06;
  258. //
  259. // Padding for prefetchable memory
  260. //
  261. PaddingResource->AddrRangeMin = 0;
  262. if (SetResourceforTbt) {
  263. PaddingResource->AddrLen = RsvdPciePMegaMem * 0x100000;
  264. } else {
  265. PaddingResource->AddrLen = RsvdPcieMegaMem * 0x100000;
  266. }
  267. //
  268. // Pad 16 MB of MEM
  269. //
  270. if (SetResourceforTbt) {
  271. PaddingResource->AddrRangeMax = (1 << PciePMemAddrRngMax) - 1;
  272. } else {
  273. PaddingResource->AddrRangeMax = 1;
  274. }
  275. //
  276. // Alignment
  277. //
  278. // Padding for I/O
  279. //
  280. PaddingResource++;
  281. PaddingResource->Desc = 0x8A;
  282. PaddingResource->Len = 0x2B;
  283. PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
  284. PaddingResource->GenFlag = 0x0;
  285. PaddingResource->SpecificFlag = 0;
  286. PaddingResource->AddrRangeMin = 0;
  287. PaddingResource->AddrLen = RsvdPcieKiloIo * 0x400;
  288. //
  289. // Pad 4K of IO
  290. //
  291. PaddingResource->AddrRangeMax = 1;
  292. //
  293. // Alignment
  294. //
  295. // Terminate the entries.
  296. //
  297. PaddingResource++;
  298. ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Desc = ACPI_END_TAG_DESCRIPTOR;
  299. ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Checksum = 0x0;
  300. *HpcState = EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED;
  301. return EFI_SUCCESS;
  302. }