Platform.asl 32 KB

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  1. /** @file
  2. ACPI DSDT table
  3. Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #define TRAP_TYPE_DTS 0x02
  7. #define TRAP_TYPE_IGD 0x03
  8. #define TRAP_TYPE_BGD 0x04 // BIOS Guard
  9. // Define the following External variables to prevent a WARNING when
  10. // using ASL.EXE and an ERROR when using IASL.EXE.
  11. External(\PC00, IntObj) // PR00 _PDC Flags
  12. External(\PC01)
  13. External(\PC02)
  14. External(\PC03)
  15. External(\PC04)
  16. External(\PC05)
  17. External(\PC06)
  18. External(\PC07)
  19. External(\PC08)
  20. External(\PC09)
  21. External(\PC10)
  22. External(\PC11)
  23. External(\PC12)
  24. External(\PC13)
  25. External(\PC14)
  26. External(\PC15)
  27. External(\_PR.CFGD)
  28. External(\SGMD)
  29. //
  30. // DTS externals
  31. //
  32. External(\_PR.DTSF)
  33. External(\_PR.DTSE)
  34. External(\_PR.TRPD)
  35. External(\_PR.TRPF)
  36. External(\_PR.DSAE)
  37. //
  38. // SGX
  39. //
  40. External(\_PR.EPCS)
  41. External(\_PR.EMNA)
  42. External(\_PR.ELNG)
  43. External(\_SB.PCI0.GFX0.TCHE) // Technology enabled indicator
  44. External(\_SB.PCI0.GFX0.STAT) // State Indicator
  45. External(\_SB.TPM.PTS, MethodObj)
  46. External(\_SB.PCI0.PAUD.PUAM, MethodObj) //PUAM - PowerResource User Absent Mode
  47. External(\_SB.PCI0.XHC.DUAM, MethodObj) //DUAM - Device User Absent Mode for XHCI controller
  48. External(\_SB.PCI0.I2C4.GEXP.INVC, MethodObj)
  49. External(\_SB.PCI0.GFX0.IUEH, MethodObj)
  50. #define CONVERTIBLE_BUTTON 6
  51. #define DOCK_INDICATOR 7
  52. Name(ECUP, 1) // EC State indicator: 1- Normal Mode 0- Low Power Mode
  53. Mutex(EHLD, 0) // EC Hold indicator: 0- No one accessing the EC Power State 1- Someone else is accessing the EC Power State
  54. External(TBTD, MethodObj)
  55. External(TBTF, MethodObj)
  56. External(MMRP, MethodObj)
  57. External(MMTB, MethodObj)
  58. External(TBFF, MethodObj)
  59. External(FFTB, MethodObj)
  60. External(SXTB, MethodObj)
  61. // Interrupt specific registers
  62. include("Itss.asl")
  63. // Create a Global MUTEX.
  64. Mutex(MUTX,0)
  65. // OS Up mutex
  66. Mutex(OSUM, 0)
  67. // _WAK Finished Event
  68. Event(WFEV)
  69. // Define Port 80 as an ACPI Operating Region to use for debugging. Please
  70. // note that the Intel CRBs have the ability to ouput an entire DWord to
  71. // Port 80h for debugging purposes, so the model implemented here may not be
  72. // able to be used on OEM Designs.
  73. OperationRegion(PRT0,SystemIO,0x80,4)
  74. Field(PRT0,DwordAcc,Lock,Preserve)
  75. {
  76. P80H, 32
  77. }
  78. // Port 80h Update:
  79. // Update 8 bits of the 32-bit Port 80h.
  80. //
  81. // Arguments:
  82. // Arg0: 0 = Write Port 80h, Bits 7:0 Only.
  83. // 1 = Write Port 80h, Bits 15:8 Only.
  84. // 2 = Write Port 80h, Bits 23:16 Only.
  85. // 3 = Write Port 80h, Bits 31:24 Only.
  86. // Arg1: 8-bit Value to write
  87. //
  88. // Return Value:
  89. // None
  90. Method(D8XH,2,Serialized)
  91. {
  92. If(LEqual(Arg0,0)) // Write Port 80h, Bits 7:0.
  93. {
  94. Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D)
  95. }
  96. If(LEqual(Arg0,1)) // Write Port 80h, Bits 15:8.
  97. {
  98. Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D)
  99. }
  100. If(LEqual(Arg0,2)) // Write Port 80h, Bits 23:16.
  101. {
  102. Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D)
  103. }
  104. If(LEqual(Arg0,3)) // Write Port 80h, Bits 31:24.
  105. {
  106. Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D)
  107. }
  108. Store(P80D,P80H)
  109. }
  110. // Debug Port 80h Update:
  111. // If Acpidebug is enabled only then call D8XH to update 8 bits of the 32-bit Port 80h.
  112. //
  113. // Arguments:
  114. // Arg0: 0 = Write Port 80h, Bits 7:0 Only.
  115. // 1 = Write Port 80h, Bits 15:8 Only.
  116. // 2 = Write Port 80h, Bits 23:16 Only.
  117. // 3 = Write Port 80h, Bits 31:24 Only.
  118. // Arg1: 8-bit Value to write
  119. //
  120. // Return Value:
  121. // None
  122. Method(P8XH,2,Serialized)
  123. {
  124. // If ACPI debug is enabled, then display post codes on Port 80h
  125. If(CondRefOf(MDBG)) {// Check if ACPI Debug SSDT is loaded
  126. D8XH(Arg0,Arg1)
  127. }
  128. }
  129. Method(ADBG,1,Serialized)
  130. {
  131. Return(0)
  132. }
  133. //
  134. // Define SW SMI port as an ACPI Operating Region to use for generate SW SMI.
  135. //
  136. OperationRegion(SPRT,SystemIO, 0xB2,2)
  137. Field (SPRT, ByteAcc, Lock, Preserve) {
  138. SSMP, 8
  139. }
  140. // The _PIC Control Method is optional for ACPI design. It allows the
  141. // OS to inform the ASL code which interrupt controller is being used,
  142. // the 8259 or APIC. The reference code in this document will address
  143. // PCI IRQ Routing and resource allocation for both cases.
  144. //
  145. // The values passed into _PIC are:
  146. // 0 = 8259
  147. // 1 = IOAPIC
  148. Method(\_PIC,1)
  149. {
  150. Store(Arg0,GPIC)
  151. Store(Arg0,PICM)
  152. }
  153. // Prepare to Sleep. The hook is called when the OS is about to
  154. // enter a sleep state. The argument passed is the numeric value of
  155. // the Sx state.
  156. Method(_PTS,1)
  157. {
  158. Store(0,P80D) // Zero out the entire Port 80h DWord.
  159. D8XH(0,Arg0) // Output Sleep State to Port 80h, Byte 0.
  160. ADBG(Concatenate("_PTS=",ToHexString(Arg0)))
  161. // If code is executed, Wake from RI# via Serial Modem will be
  162. // enabled. If code is not executed, COM Port Debugging throughout
  163. // all Sx states will be enabled.
  164. If(LEqual(Arg0,3))
  165. {
  166. //
  167. // Disable update DTS temperature and threshold value in every SMI
  168. //
  169. If(CondRefOf(\_PR.DTSE)){
  170. If(LAnd(\_PR.DTSE, LGreater(TCNT, 1)))
  171. {
  172. TRAP(TRAP_TYPE_DTS,30)
  173. }
  174. }
  175. }
  176. // Generate a SW SMI trap to save some NVRAM data back to CMOS.
  177. // Don't enable IGD OpRegion support yet.
  178. // TRAP(1, 81)
  179. //
  180. // Call TPM.PTS
  181. //
  182. If(CondRefOf(\_SB.TPM.PTS))
  183. {
  184. //
  185. // Call TPM PTS method
  186. //
  187. \_SB.TPM.PTS (Arg0)
  188. }
  189. }
  190. // Wake. This hook is called when the OS is about to wake from a
  191. // sleep state. The argument passed is the numeric value of the
  192. // sleep state the system is waking from.
  193. Method(_WAK,1,Serialized)
  194. {
  195. D8XH(1,0xAB) // Beginning of _WAK.
  196. ADBG("_WAK")
  197. //
  198. // Only set 8254 CG if Low Power S0 Idle Capability is enabled
  199. //
  200. If (LEqual(S0ID, One)) {
  201. //
  202. // Set ITSSPRC.8254CGE: Offset 3300h ITSSPRC[2]
  203. //
  204. Store(0x01, \_SB.SCGE)
  205. }
  206. If(NEXP)
  207. {
  208. // Reinitialize the Native PCI Express after resume
  209. If(And(OSCC,0x02))
  210. {
  211. \_SB.PCI0.NHPG()
  212. }
  213. If(And(OSCC,0x04)) // PME control granted?
  214. {
  215. \_SB.PCI0.NPME()
  216. }
  217. }
  218. If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume
  219. {
  220. // Check to send Convertible/Dock state changes upon resume from Sx.
  221. If(And(GBSX,0x40))
  222. {
  223. \_SB.PCI0.GFX0.IUEH(6)
  224. //
  225. // Do the same thing for Virtul Button device.
  226. // Toggle Bit3 of PB1E(Slate/Notebook status)
  227. //
  228. Xor(PB1E, 0x08, PB1E)
  229. }
  230. If(And(GBSX,0x80))
  231. {
  232. \_SB.PCI0.GFX0.IUEH(7)
  233. //
  234. // Do the same thing for Virtul Button device.
  235. // Toggle Bit4 of PB1E (Dock/Undock status)
  236. //
  237. Xor(PB1E, 0x10, PB1E)
  238. }
  239. If(CondRefOf(\_PR.DTSE)){
  240. If(LAnd(\_PR.DTSE, LGreater(TCNT, 1)))
  241. {
  242. TRAP(TRAP_TYPE_DTS, 20)
  243. }
  244. }
  245. // For PCI Express Express Cards, it is possible a device was
  246. // either inserted or removed during an Sx State. The problem
  247. // is that no wake event will occur for a given warm insertion
  248. // or removal, so the OS will not become aware of any change.
  249. // To get around this, re-enumerate all Express Card slots.
  250. //
  251. // If the Root Port is enabled, it may be assumed to be hot-pluggable.
  252. If(LNotEqual(\_SB.PCI0.RP01.VDID,0xFFFFFFFF))
  253. {
  254. Notify (\_SB.PCI0.RP01,0)
  255. }
  256. If(LNotEqual(\_SB.PCI0.RP02.VDID,0xFFFFFFFF))
  257. {
  258. Notify (\_SB.PCI0.RP02,0)
  259. }
  260. If(LNotEqual(\_SB.PCI0.RP03.VDID,0xFFFFFFFF))
  261. {
  262. Notify (\_SB.PCI0.RP03,0)
  263. }
  264. If(LNotEqual(\_SB.PCI0.RP04.VDID,0xFFFFFFFF))
  265. {
  266. Notify (\_SB.PCI0.RP04,0)
  267. }
  268. If(LNotEqual(\_SB.PCI0.RP05.VDID,0xFFFFFFFF))
  269. {
  270. Notify (\_SB.PCI0.RP05,0)
  271. }
  272. If(LNotEqual(\_SB.PCI0.RP06.VDID,0xFFFFFFFF))
  273. {
  274. Notify (\_SB.PCI0.RP06,0)
  275. }
  276. If(LNotEqual(\_SB.PCI0.RP07.VDID,0xFFFFFFFF))
  277. {
  278. Notify (\_SB.PCI0.RP07,0)
  279. }
  280. If(LNotEqual(\_SB.PCI0.RP08.VDID,0xFFFFFFFF))
  281. {
  282. Notify (\_SB.PCI0.RP08,0)
  283. }
  284. If(LNotEqual(\_SB.PCI0.RP09.VDID,0xFFFFFFFF))
  285. {
  286. Notify (\_SB.PCI0.RP09,0)
  287. }
  288. If(LNotEqual(\_SB.PCI0.RP10.VDID,0xFFFFFFFF))
  289. {
  290. Notify (\_SB.PCI0.RP10,0)
  291. }
  292. If(LNotEqual(\_SB.PCI0.RP11.VDID,0xFFFFFFFF))
  293. {
  294. Notify (\_SB.PCI0.RP11,0)
  295. }
  296. If(LNotEqual(\_SB.PCI0.RP12.VDID,0xFFFFFFFF))
  297. {
  298. Notify (\_SB.PCI0.RP12,0)
  299. }
  300. If(LNotEqual(\_SB.PCI0.RP13.VDID,0xFFFFFFFF))
  301. {
  302. Notify (\_SB.PCI0.RP13,0)
  303. }
  304. If(LNotEqual(\_SB.PCI0.RP14.VDID,0xFFFFFFFF))
  305. {
  306. Notify (\_SB.PCI0.RP14,0)
  307. }
  308. If(LNotEqual(\_SB.PCI0.RP15.VDID,0xFFFFFFFF))
  309. {
  310. Notify (\_SB.PCI0.RP15,0)
  311. }
  312. If(LNotEqual(\_SB.PCI0.RP16.VDID,0xFFFFFFFF))
  313. {
  314. Notify (\_SB.PCI0.RP16,0)
  315. }
  316. If(LNotEqual(\_SB.PCI0.RP17.VDID,0xFFFFFFFF))
  317. {
  318. Notify (\_SB.PCI0.RP17,0)
  319. }
  320. If(LNotEqual(\_SB.PCI0.RP18.VDID,0xFFFFFFFF))
  321. {
  322. Notify (\_SB.PCI0.RP18,0)
  323. }
  324. If(LNotEqual(\_SB.PCI0.RP19.VDID,0xFFFFFFFF))
  325. {
  326. Notify (\_SB.PCI0.RP19,0)
  327. }
  328. If(LNotEqual(\_SB.PCI0.RP20.VDID,0xFFFFFFFF))
  329. {
  330. Notify (\_SB.PCI0.RP20,0)
  331. }
  332. }
  333. Return(Package(){0,0})
  334. }
  335. // Get Buffer:
  336. // This method will take a buffer passed into the method and
  337. // create then return a smaller buffer based on the pointer
  338. // and size parameters passed in.
  339. //
  340. // Arguments:
  341. // Arg0: Pointer to start of new Buffer in passed in Buffer.
  342. // Arg1: Size of Buffer to create.
  343. // Arg2: Original Buffer
  344. //
  345. // Return Value:
  346. // Newly created buffer.
  347. Method(GETB,3,Serialized)
  348. {
  349. Multiply(Arg0,8,Local0) // Convert Index.
  350. Multiply(Arg1,8,Local1) // Convert Size.
  351. CreateField(Arg2,Local0,Local1,TBF3) // Create Buffer.
  352. Return(TBF3) // Return Buffer.
  353. }
  354. // Power Notification:
  355. // Perform all needed OS notifications during a
  356. // Power Switch.
  357. //
  358. // Arguments:
  359. // None
  360. //
  361. // Return Value:
  362. // None
  363. Method(PNOT,0,Serialized)
  364. {
  365. //
  366. // If MP enabled and driver support is present, notify all
  367. // processors.
  368. //
  369. If(LGreater(TCNT, 1))
  370. {
  371. If(And(\PC00,0x0008)){
  372. Notify(\_PR.PR00,0x80) // Eval PR00 _PPC.
  373. }
  374. If(And(\PC01,0x0008)){
  375. Notify(\_PR.PR01,0x80) // Eval PR01 _PPC.
  376. }
  377. If(And(\PC02,0x0008)){
  378. Notify(\_PR.PR02,0x80) // Eval PR02 _PPC.
  379. }
  380. If(And(\PC03,0x0008)){
  381. Notify(\_PR.PR03,0x80) // Eval PR03 _PPC.
  382. }
  383. If(And(\PC04,0x0008)){
  384. Notify(\_PR.PR04,0x80) // Eval PR04 _PPC.
  385. }
  386. If(And(\PC05,0x0008)){
  387. Notify(\_PR.PR05,0x80) // Eval PR05 _PPC.
  388. }
  389. If(And(\PC06,0x0008)){
  390. Notify(\_PR.PR06,0x80) // Eval PR06 _PPC.
  391. }
  392. If(And(\PC07,0x0008)){
  393. Notify(\_PR.PR07,0x80) // Eval PR07 _PPC.
  394. }
  395. If(And(\PC08,0x0008)){
  396. Notify(\_PR.PR08,0x80) // Eval PR08 _PPC.
  397. }
  398. If(And(\PC09,0x0008)){
  399. Notify(\_PR.PR09,0x80) // Eval PR09 _PPC.
  400. }
  401. If(And(\PC10,0x0008)){
  402. Notify(\_PR.PR10,0x80) // Eval PR10 _PPC.
  403. }
  404. If(And(\PC11,0x0008)){
  405. Notify(\_PR.PR11,0x80) // Eval PR11 _PPC.
  406. }
  407. If(And(\PC12,0x0008)){
  408. Notify(\_PR.PR12,0x80) // Eval PR12 _PPC.
  409. }
  410. If(And(\PC13,0x0008)){
  411. Notify(\_PR.PR13,0x80) // Eval PR13 _PPC.
  412. }
  413. If(And(\PC14,0x0008)){
  414. Notify(\_PR.PR14,0x80) // Eval PR14 _PPC.
  415. }
  416. If(And(\PC15,0x0008)){
  417. Notify(\_PR.PR15,0x80) // Eval PR15 _PPC.
  418. }
  419. }Else{
  420. Notify(\_PR.PR00,0x80) // Eval _PPC.
  421. }
  422. If(LGreater(TCNT, 1)){
  423. If(LAnd(And(\PC00,0x0008),And(\PC00,0x0010))){
  424. Notify(\_PR.PR00,0x81) // Eval PR00 _CST.
  425. }
  426. If(LAnd(And(\PC01,0x0008),And(\PC01,0x0010))){
  427. Notify(\_PR.PR01,0x81) // Eval PR01 _CST.
  428. }
  429. If(LAnd(And(\PC02,0x0008),And(\PC02,0x0010))){
  430. Notify(\_PR.PR02,0x81) // Eval PR02 _CST.
  431. }
  432. If(LAnd(And(\PC03,0x0008),And(\PC03,0x0010))){
  433. Notify(\_PR.PR03,0x81) // Eval PR03 _CST.
  434. }
  435. If(LAnd(And(\PC04,0x0008),And(\PC04,0x0010))){
  436. Notify(\_PR.PR04,0x81) // Eval PR04 _CST.
  437. }
  438. If(LAnd(And(\PC05,0x0008),And(\PC05,0x0010))){
  439. Notify(\_PR.PR05,0x81) // Eval PR05 _CST.
  440. }
  441. If(LAnd(And(\PC06,0x0008),And(\PC06,0x0010))){
  442. Notify(\_PR.PR06,0x81) // Eval PR06 _CST.
  443. }
  444. If(LAnd(And(\PC07,0x0008),And(\PC07,0x0010))){
  445. Notify(\_PR.PR07,0x81) // Eval PR07 _CST.
  446. }
  447. If(LAnd(And(\PC08,0x0008),And(\PC08,0x0010))){
  448. Notify(\_PR.PR08,0x81) // Eval PR08 _CST.
  449. }
  450. If(LAnd(And(\PC09,0x0008),And(\PC09,0x0010))){
  451. Notify(\_PR.PR09,0x81) // Eval PR09 _CST.
  452. }
  453. If(LAnd(And(\PC10,0x0008),And(\PC10,0x0010))){
  454. Notify(\_PR.PR10,0x81) // Eval PR10 _CST.
  455. }
  456. If(LAnd(And(\PC11,0x0008),And(\PC11,0x0010))){
  457. Notify(\_PR.PR11,0x81) // Eval PR11 _CST.
  458. }
  459. If(LAnd(And(\PC12,0x0008),And(\PC12,0x0010))){
  460. Notify(\_PR.PR12,0x81) // Eval PR12 _CST.
  461. }
  462. If(LAnd(And(\PC13,0x0008),And(\PC13,0x0010))){
  463. Notify(\_PR.PR13,0x81) // Eval PR13 _CST.
  464. }
  465. If(LAnd(And(\PC14,0x0008),And(\PC14,0x0010))){
  466. Notify(\_PR.PR14,0x81) // Eval PR14 _CST.
  467. }
  468. If(LAnd(And(\PC15,0x0008),And(\PC15,0x0010))){
  469. Notify(\_PR.PR15,0x81) // Eval PR15 _CST.
  470. }
  471. } Else {
  472. Notify(\_PR.PR00,0x81) // Eval _CST.
  473. }
  474. } // end of Method(PNOT)
  475. //
  476. // Memory window to the CTDP registers starting at MCHBAR+5000h.
  477. //
  478. OperationRegion (MBAR, SystemMemory, Add(\_SB.PCI0.GMHB(),0x5000), 0x1000)
  479. Field (MBAR, ByteAcc, NoLock, Preserve)
  480. {
  481. Offset (0x938), // PACKAGE_POWER_SKU_UNIT (MCHBAR+0x5938)
  482. PWRU, 4, // Power Units [3:0] unit value is calculated by 1 W / Power(2,PWR_UNIT). The default value of 0011b corresponds to 1/8 W.
  483. Offset (0x9A0), // TURBO_POWER_LIMIT1 (MCHBAR+0x59A0)
  484. PPL1, 15, // PKG_PWR_LIM_1 [14:0]
  485. PL1E,1, // PKG_PWR_LIM1_EN [15]
  486. CLP1,1, // Package Clamping Limitation 1
  487. }
  488. Name(CLMP, 0) // save the clamp bit
  489. Name(PLEN,0) // save the power limit enable bit
  490. Name(PLSV,0x8000) // save value of PL1 upon entering CS
  491. Name(CSEM, 0) //semaphore to avoid multiple calls to SPL1. SPL1/RPL1 must always be called in pairs, like push/pop off a stack
  492. //
  493. // SPL1 (Set PL1 to 4.5 watts with clamp bit set)
  494. // Per Legacy Thermal management CS requirements, we would like to set the PL1 limit when entering CS to 4.5W with clamp bit set via MMIO.
  495. // This can be done in the ACPI object which gets called by graphics driver during CS Entry.
  496. // Likewise, during CS exit, the BIOS must reset the PL1 value to the previous value prior to CS entry and reset the clamp bit.
  497. //
  498. // Arguments:
  499. // None
  500. //
  501. // Return Value:
  502. // None
  503. Method(SPL1,0,Serialized)
  504. {
  505. Name(PPUU,0) // units
  506. If (LEqual(CSEM, 1))
  507. {
  508. Return() // we have already been called, must have CS exit before calling again
  509. }
  510. Store(1, CSEM) // record first call
  511. Store (PPL1, PLSV) // save PL1 value upon entering CS
  512. Store (PL1E, PLEN) // save PL1 Enable bit upon entering CS
  513. Store (CLP1, CLMP) // save PL1 Clamp bit upon entering CS
  514. If (LEqual(PWRU,0)) { // use PACKAGE_POWER_SKU_UNIT - Power Units[3:0]
  515. Store(1,PPUU)
  516. } Else {
  517. ShiftLeft(Decrement(PWRU),2,PPUU) // get units
  518. }
  519. Multiply(PLVL,PPUU,Local0) // convert SETUP value to power units in milli-watts
  520. Divide(Local0,1000,,Local1) // convert SETUP value to power units in watts
  521. Store(Local1, PPL1) // copy value to PL1
  522. Store(1, PL1E) // set Enable bit
  523. Store(1, CLP1) // set Clamp bit
  524. }
  525. //
  526. // RPL1 (Restore the PL1 register to the values prior to CS entry)
  527. //
  528. // Arguments:
  529. // None
  530. //
  531. // Return Value:
  532. // None
  533. Method(RPL1,0,Serialized)
  534. {
  535. Store (PLSV, PPL1) // restore value of PL1 upon exiting CS
  536. Store(PLEN, PL1E) // restore the PL1 enable bit
  537. Store(CLMP, CLP1) // restore the PL1 Clamp bit
  538. Store(0, CSEM) // restore semaphore
  539. }
  540. Name(UAMS, 0) // User Absent Mode state, Zero - User Present; non-Zero - User not present
  541. Name(GLCK, 0) // a spin lock to avoid multi execution of GUAM
  542. // GUAM - Global User Absent Mode
  543. // Run when a change to User Absent mode is made, e.g. screen/display on/off events.
  544. // Any device that needs notifications of these events includes its own UAMN Control Method.
  545. //
  546. // Arguments:
  547. // Power State:
  548. // 00h = On
  549. // 01h = Standby
  550. // other value = do nothing & return
  551. //
  552. // Return Value:
  553. // None
  554. //
  555. Method(GUAM,1,Serialized)
  556. {
  557. Switch(ToInteger(Arg0))
  558. {
  559. Case(0) // exit CS
  560. {
  561. If(LEqual(GLCK, 1)){
  562. store(0, GLCK)
  563. P8XH(0, 0xE1)
  564. P8XH(1, 0xAB)
  565. ADBG("Exit Resiliency")
  566. // @Todo: Exit EC Low Power Mode here
  567. If(PSCP){
  568. // if P-state Capping s enabled
  569. If (CondRefOf(\_PR.PR00._PPC))
  570. {
  571. Store(Zero, \_PR.CPPC)
  572. PNOT()
  573. }
  574. }
  575. If(PLCS){
  576. RPL1() // restore PL1 to pre-CS value upon exiting CS
  577. }
  578. } // end GLCK=1
  579. } // end case(0)
  580. Case(1) // enter CS
  581. {
  582. If(LEqual(GLCK, 0)){
  583. store(1, GLCK)
  584. P8XH(0, 0xE0)
  585. P8XH(1, 00)
  586. ADBG("Enter Resiliency")
  587. //@Todo: Enter EC Low Power Mode here
  588. If(PSCP){
  589. // if P-state Capping is enabled
  590. If (LAnd(CondRefOf(\_PR.PR00._PSS), CondRefOf(\_PR.PR00._PPC)))
  591. {
  592. If(And(\PC00,0x0400))
  593. {
  594. Subtract(SizeOf(\_PR.PR00.TPSS), One, \_PR.CPPC)
  595. } Else {
  596. Subtract(SizeOf(\_PR.PR00.LPSS), One, \_PR.CPPC)
  597. }
  598. PNOT()
  599. }
  600. }
  601. If(PLCS){
  602. SPL1() // set PL1 to low value upon CS entry
  603. }
  604. } // end GLCK=0
  605. } // end case(1)
  606. Default{
  607. Return() // do nothing
  608. }
  609. } // end switch(arg0)
  610. Store(LAnd(Arg0, LNot(PWRS)), UAMS) // UAMS: User Absent Mode state, Zero - User Present; non-Zero - User not present
  611. P_CS() // Powergating during CS
  612. } // end method GUAM()
  613. // Power CS Powergated Devices:
  614. // Method to enable/disable power during CS
  615. Method(P_CS,0,Serialized)
  616. {
  617. // NOTE: Do not turn ON Touch devices from here. Touch does not have PUAM
  618. If(CondRefOf(\_SB.PCI0.PAUD.PUAM)){ // Notify Codec(HD-A/ADSP)
  619. \_SB.PCI0.PAUD.PUAM()
  620. }
  621. // Adding back USB powergating (ONLY for Win8) until RTD3 walkup port setup implementation is complete */
  622. If(LEqual(OSYS,2012)){ // ONLY for Win8 OS
  623. If(CondRefOf(\_SB.PCI0.XHC.DUAM)){ // Notify USB port- RVP
  624. \_SB.PCI0.XHC.DUAM()
  625. }
  626. }
  627. // TODO: Add calls to UAMN methods for
  628. // * USB controller(s)
  629. // * Embedded Controller
  630. // * Sensor devices
  631. // * Audio DSP?
  632. // * Any other devices dependent on User Absent mode for power controls
  633. }
  634. // SMI I/O Trap:
  635. // Generate a Mutex protected SMI I/O Trap.
  636. //
  637. // Arguments:
  638. // Arg0: I/O Trap type.
  639. // 2 - For DTS
  640. // 3 - For IGD
  641. // 4 - For BIOS Guard Tools
  642. // Arg1: SMI I/O Trap Function to call.
  643. //
  644. // Return Value:
  645. // SMI I/O Trap Return value.
  646. // 0 = Success. Non-zero = Failure.
  647. Scope(\)
  648. {
  649. //
  650. // The IO address in this ACPI Operating Region will be updated during POST.
  651. // This address range is used as a HotKey I/O Trap SMI so that ASL and SMI can
  652. // communicate when needed.
  653. //
  654. OperationRegion(IO_H,SystemIO,0x1000,0x4)
  655. Field(IO_H,ByteAcc,NoLock,Preserve) {
  656. TRPH, 8
  657. }
  658. }
  659. Method(TRAP,2,Serialized)
  660. {
  661. Store(Arg1,SMIF) // Store SMI Function.
  662. If(LEqual(Arg0,TRAP_TYPE_DTS)) // Is DTS IO Trap?
  663. {
  664. Store(Arg1,\_PR.DTSF) // Store the function number global NVS
  665. Store(0,\_PR.TRPD) // Generate IO Trap.
  666. Return(\_PR.DTSF) // Return status from SMI handler
  667. }
  668. If(LEqual(Arg0,TRAP_TYPE_IGD)) // Is IGD IO Trap?
  669. {
  670. Store(0,TRPH) // Generate IO Trap.
  671. }
  672. If(LEqual(Arg0,TRAP_TYPE_BGD)) // Is BIOS Guard TOOLS IO Trap?
  673. {
  674. Store(0,\_PR.TRPF) // Generate IO Trap
  675. }
  676. Return(SMIF) // Return SMIF. 0 = Success.
  677. }
  678. // Note: Only add the indicator device needed by the platform.
  679. //
  680. // System Bus
  681. //
  682. Scope(\_SB.PCI0)
  683. {
  684. Method(_INI,0, Serialized)
  685. {
  686. // Determine the OS and store the value, where:
  687. //
  688. // OSYS = 1000 = Linux.
  689. // OSYS = 2000 = WIN2000.
  690. // OSYS = 2001 = WINXP, RTM or SP1.
  691. // OSYS = 2002 = WINXP SP2.
  692. // OSYS = 2006 = Vista.
  693. // OSYS = 2009 = Windows 7 and Windows Server 2008 R2.
  694. // OSYS = 2012 = Windows 8 and Windows Server 2012.
  695. // OSYS = 2013 = Windows Blue.
  696. //
  697. // Assume Windows 2000 at a minimum.
  698. Store(2000,OSYS)
  699. // Check for a specific OS which supports _OSI.
  700. If(CondRefOf(\_OSI))
  701. {
  702. If(\_OSI("Linux"))
  703. {
  704. Store(1000,OSYS)
  705. }
  706. If(\_OSI("Windows 2001")) // Windows XP
  707. {
  708. Store(2001,OSYS)
  709. }
  710. If(\_OSI("Windows 2001 SP1")) //Windows XP SP1
  711. {
  712. Store(2001,OSYS)
  713. }
  714. If(\_OSI("Windows 2001 SP2")) //Windows XP SP2
  715. {
  716. Store(2002,OSYS)
  717. }
  718. If (\_OSI( "Windows 2001.1")) //Windows Server 2003
  719. {
  720. Store(2003,OSYS)
  721. }
  722. If(\_OSI("Windows 2006")) //Windows Vista
  723. {
  724. Store(2006,OSYS)
  725. }
  726. If(\_OSI("Windows 2009")) //Windows 7 and Windows Server 2008 R2
  727. {
  728. Store(2009,OSYS)
  729. }
  730. If(\_OSI("Windows 2012")) //Windows 8 and Windows Server 2012
  731. {
  732. Store(2012,OSYS)
  733. }
  734. If(\_OSI("Windows 2013")) //Windows 8.1 and Windows Server 2012 R2
  735. {
  736. Store(2013,OSYS)
  737. }
  738. If(\_OSI("Windows 2015")) //Windows 10
  739. {
  740. Store(2015,OSYS)
  741. }
  742. }
  743. //
  744. // Set DTS NVS data means in OS ACPI mode enabled insteads of GlobalNvs OperatingSystem (OSYS)
  745. //
  746. If(CondRefOf(\_PR.DTSE)){
  747. If(LGreaterEqual(\_PR.DTSE, 0x01)){
  748. Store(0x01, \_PR.DSAE)
  749. }
  750. }
  751. }
  752. Method(NHPG,0,Serialized)
  753. {
  754. Store(0,^RP01.HPEX) // clear the hot plug SCI enable bit
  755. Store(0,^RP02.HPEX) // clear the hot plug SCI enable bit
  756. Store(0,^RP03.HPEX) // clear the hot plug SCI enable bit
  757. Store(0,^RP04.HPEX) // clear the hot plug SCI enable bit
  758. Store(0,^RP05.HPEX) // clear the hot plug SCI enable bit
  759. Store(0,^RP06.HPEX) // clear the hot plug SCI enable bit
  760. Store(0,^RP07.HPEX) // clear the hot plug SCI enable bit
  761. Store(0,^RP08.HPEX) // clear the hot plug SCI enable bit
  762. Store(0,^RP09.HPEX) // clear the hot plug SCI enable bit
  763. Store(0,^RP10.HPEX) // clear the hot plug SCI enable bit
  764. Store(0,^RP11.HPEX) // clear the hot plug SCI enable bit
  765. Store(0,^RP12.HPEX) // clear the hot plug SCI enable bit
  766. Store(0,^RP13.HPEX) // clear the hot plug SCI enable bit
  767. Store(0,^RP14.HPEX) // clear the hot plug SCI enable bit
  768. Store(0,^RP15.HPEX) // clear the hot plug SCI enable bit
  769. Store(0,^RP16.HPEX) // clear the hot plug SCI enable bit
  770. Store(0,^RP17.HPEX) // clear the hot plug SCI enable bit
  771. Store(0,^RP18.HPEX) // clear the hot plug SCI enable bit
  772. Store(0,^RP19.HPEX) // clear the hot plug SCI enable bit
  773. Store(0,^RP20.HPEX) // clear the hot plug SCI enable bit
  774. Store(1,^RP01.HPSX) // clear the hot plug SCI status bit
  775. Store(1,^RP02.HPSX) // clear the hot plug SCI status bit
  776. Store(1,^RP03.HPSX) // clear the hot plug SCI status bit
  777. Store(1,^RP04.HPSX) // clear the hot plug SCI status bit
  778. Store(1,^RP05.HPSX) // clear the hot plug SCI status bit
  779. Store(1,^RP06.HPSX) // clear the hot plug SCI status bit
  780. Store(1,^RP07.HPSX) // clear the hot plug SCI status bit
  781. Store(1,^RP08.HPSX) // clear the hot plug SCI status bit
  782. Store(1,^RP09.HPSX) // clear the hot plug SCI status bit
  783. Store(1,^RP10.HPSX) // clear the hot plug SCI status bit
  784. Store(1,^RP11.HPSX) // clear the hot plug SCI status bit
  785. Store(1,^RP12.HPSX) // clear the hot plug SCI status bit
  786. Store(1,^RP13.HPSX) // clear the hot plug SCI status bit
  787. Store(1,^RP14.HPSX) // clear the hot plug SCI status bit
  788. Store(1,^RP15.HPSX) // clear the hot plug SCI status bit
  789. Store(1,^RP16.HPSX) // clear the hot plug SCI status bit
  790. Store(1,^RP17.HPSX) // clear the hot plug SCI status bit
  791. Store(1,^RP18.HPSX) // clear the hot plug SCI status bit
  792. Store(1,^RP19.HPSX) // clear the hot plug SCI status bit
  793. Store(1,^RP20.HPSX) // clear the hot plug SCI status bit
  794. }
  795. Method(NPME,0,Serialized)
  796. {
  797. Store(0,^RP01.PMEX) // clear the PME SCI enable bit
  798. Store(0,^RP02.PMEX) // clear the PME SCI enable bit
  799. Store(0,^RP03.PMEX) // clear the PME SCI enable bit
  800. Store(0,^RP04.PMEX) // clear the PME SCI enable bit
  801. Store(0,^RP05.PMEX) // clear the PME SCI enable bit
  802. Store(0,^RP06.PMEX) // clear the PME SCI enable bit
  803. Store(0,^RP07.PMEX) // clear the PME SCI enable bit
  804. Store(0,^RP08.PMEX) // clear the PME SCI enable bit
  805. Store(0,^RP09.PMEX) // clear the PME SCI enable bit
  806. Store(0,^RP10.PMEX) // clear the PME SCI enable bit
  807. Store(0,^RP11.PMEX) // clear the PME SCI enable bit
  808. Store(0,^RP12.PMEX) // clear the PME SCI enable bit
  809. Store(0,^RP13.PMEX) // clear the PME SCI enable bit
  810. Store(0,^RP14.PMEX) // clear the PME SCI enable bit
  811. Store(0,^RP15.PMEX) // clear the PME SCI enable bit
  812. Store(0,^RP16.PMEX) // clear the PME SCI enable bit
  813. Store(0,^RP17.PMEX) // clear the PME SCI enable bit
  814. Store(0,^RP18.PMEX) // clear the PME SCI enable bit
  815. Store(0,^RP19.PMEX) // clear the PME SCI enable bit
  816. Store(0,^RP20.PMEX) // clear the PME SCI enable bit
  817. Store(1,^RP01.PMSX) // clear the PME SCI status bit
  818. Store(1,^RP02.PMSX) // clear the PME SCI status bit
  819. Store(1,^RP03.PMSX) // clear the PME SCI status bit
  820. Store(1,^RP04.PMSX) // clear the PME SCI status bit
  821. Store(1,^RP05.PMSX) // clear the PME SCI status bit
  822. Store(1,^RP06.PMSX) // clear the PME SCI enable bit
  823. Store(1,^RP07.PMSX) // clear the PME SCI status bit
  824. Store(1,^RP08.PMSX) // clear the PME SCI status bit
  825. Store(1,^RP09.PMSX) // clear the PME SCI status bit
  826. Store(1,^RP10.PMSX) // clear the PME SCI status bit
  827. Store(1,^RP11.PMSX) // clear the PME SCI status bit
  828. Store(1,^RP12.PMSX) // clear the PME SCI status bit
  829. Store(1,^RP13.PMSX) // clear the PME SCI status bit
  830. Store(1,^RP14.PMSX) // clear the PME SCI status bit
  831. Store(1,^RP15.PMSX) // clear the PME SCI status bit
  832. Store(1,^RP16.PMSX) // clear the PME SCI status bit
  833. Store(1,^RP17.PMSX) // clear the PME SCI status bit
  834. Store(1,^RP18.PMSX) // clear the PME SCI status bit
  835. Store(1,^RP19.PMSX) // clear the PME SCI status bit
  836. Store(1,^RP20.PMSX) // clear the PME SCI status bit
  837. }
  838. }
  839. Scope (\)
  840. {
  841. //
  842. // Global Name, returns current Interrupt controller mode;
  843. // updated from _PIC control method
  844. //
  845. Name(PICM, 0)
  846. //
  847. // Procedure: GPRW
  848. //
  849. // Description: Generic Wake up Control Method ("Big brother")
  850. // to detect the Max Sleep State available in ASL Name scope
  851. // and Return the Package compatible with _PRW format.
  852. // Input: Arg0 = bit offset within GPE register space device event will be triggered to.
  853. // Arg1 = Max Sleep state, device can resume the System from.
  854. // If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the System.
  855. // Output: _PRW package
  856. //
  857. Name(PRWP, Package(){Zero, Zero}) // _PRW Package
  858. Method(GPRW, 2)
  859. {
  860. Store(Arg0, Index(PRWP, 0)) // copy GPE#
  861. //
  862. // SS1-SS4 - enabled in BIOS Setup Sleep states
  863. //
  864. Store(ShiftLeft(SS1,1),Local0) // S1 ?
  865. Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ?
  866. Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ?
  867. Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ?
  868. //
  869. // Local0 has a bit mask of enabled Sx(1 based)
  870. // bit mask of enabled in BIOS Setup Sleep states(1 based)
  871. //
  872. If(And(ShiftLeft(1, Arg1), Local0))
  873. {
  874. //
  875. // Requested wake up value (Arg1) is present in Sx list of available Sleep states
  876. //
  877. Store(Arg1, Index(PRWP, 1)) // copy Sx#
  878. }
  879. Else
  880. {
  881. //
  882. // Not available -> match Wake up value to the higher Sx state
  883. //
  884. ShiftRight(Local0, 1, Local0)
  885. // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x
  886. // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Max Sx
  887. // } Else { // ??? Win2k / XP
  888. FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Min Sx
  889. // }
  890. }
  891. Return(PRWP)
  892. }
  893. }
  894. Scope (\_SB)
  895. {
  896. Name(OSCI, 0) // \_SB._OSC DWORD2 input
  897. Name(OSCO, 0) // \_SB._OSC DWORD2 output
  898. Name(OSCP, 0) // \_SB._OSC CAPABILITIES
  899. // _OSC (Operating System Capabilities)
  900. // _OSC under \_SB scope is used to convey platform wide OSPM capabilities.
  901. // For a complete description of _OSC ACPI Control Method, refer to ACPI 5.0
  902. // specification, section 6.2.10.
  903. // Arguments: (4)
  904. // Arg0 - A Buffer containing the UUID "0811B06E-4A27-44F9-8D60-3CBBC22E7B48"
  905. // Arg1 - An Integer containing the Revision ID of the buffer format
  906. // Arg2 - An Integer containing a count of entries in Arg3
  907. // Arg3 - A Buffer containing a list of DWORD capabilities
  908. // Return Value:
  909. // A Buffer containing the list of capabilities
  910. //
  911. Method(_OSC,4,Serialized)
  912. {
  913. //
  914. // Point to Status DWORD in the Arg3 buffer (STATUS)
  915. //
  916. CreateDWordField(Arg3, 0, STS0)
  917. //
  918. // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES)
  919. //
  920. CreateDwordField(Arg3, 4, CAP0)
  921. //
  922. // Only set 8254 CG if Low Power S0 Idle Capability is enabled
  923. //
  924. If (LEqual(S0ID, One)) {
  925. //
  926. // Set ITSSPRC.8254CGE: Offset 3300h ITSSPRC[2]
  927. //
  928. Store(0x01, \_SB.SCGE)
  929. }
  930. //
  931. // Check UUID
  932. //
  933. If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
  934. {
  935. //
  936. // Check Revision
  937. //
  938. If(LEqual(Arg1,One))
  939. {
  940. Store(CAP0, OSCP)
  941. If(And(CAP0,0x04)) // Check _PR3 Support(BIT2)
  942. {
  943. Store(0x04, OSCO)
  944. If(LNotEqual(And(SGMD,0x0F),2)) // Check Switchable/Hybrid graphics is not enabled in bios setup [SgModeMuxless]?
  945. {
  946. If(LEqual(RTD3,0)) // Is RTD3 support disabled in Bios Setup?
  947. {
  948. // RTD3 is disabled via BIOS Setup.
  949. And(CAP0, 0x3B, CAP0) // Clear _PR3 capability
  950. Or(STS0, 0x10, STS0) // Indicate capability bit is cleared
  951. }
  952. }
  953. }
  954. } Else{
  955. And(STS0,0xFFFFFF00,STS0)
  956. Or(STS0,0xA, STS0) // Unrecognised Revision and report OSC failure
  957. }
  958. } Else {
  959. And(STS0,0xFFFFFF00,STS0)
  960. Or (STS0,0x6, STS0) // Unrecognised UUID and report OSC failure
  961. }
  962. Return(Arg3)
  963. } // End _OSC
  964. } // End of Scope(\_SB)
  965. //
  966. // CS Wake up event support
  967. //
  968. Scope (\_SB)
  969. {
  970. // Define Sleep button to put the system in sleep
  971. Device (SLPB)
  972. {
  973. Name (_HID, EISAID ("PNP0C0E"))
  974. Name (_STA, 0x0B)
  975. // Bit0 - the device is present: Yes.
  976. // Bit1 - the device is enabled and decoding its resources: Yes.
  977. // Bit2 - the device should be shown in the UI: No.
  978. // Bit3 - the device is functioning properly: Yes.
  979. // Bit4 - the battery is present: N/A
  980. }
  981. } // End of Scope(\_SB)