PciTree.asl 11 KB

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  1. /** @file
  2. ACPI DSDT table
  3. Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. Scope(\_SB) {
  7. Name(PR00, Package(){
  8. // PCI Bridge
  9. // D31: cAVS, SMBus, GbE, Nothpeak
  10. Package(){0x001FFFFF, 0, LNKA, 0 },
  11. Package(){0x001FFFFF, 1, LNKB, 0 },
  12. Package(){0x001FFFFF, 2, LNKC, 0 },
  13. Package(){0x001FFFFF, 3, LNKD, 0 },
  14. // D30: SerialIo and SCS - can't use PIC
  15. // D29: PCI Express Port 9-16
  16. Package(){0x001DFFFF, 0, LNKA, 0 },
  17. Package(){0x001DFFFF, 1, LNKB, 0 },
  18. Package(){0x001DFFFF, 2, LNKC, 0 },
  19. Package(){0x001DFFFF, 3, LNKD, 0 },
  20. // D28: PCI Express Port 1-8
  21. Package(){0x001CFFFF, 0, LNKA, 0 },
  22. Package(){0x001CFFFF, 1, LNKB, 0 },
  23. Package(){0x001CFFFF, 2, LNKC, 0 },
  24. Package(){0x001CFFFF, 3, LNKD, 0 },
  25. // D27: PCI Express Port 17-20
  26. Package(){0x001BFFFF, 0, LNKA, 0 },
  27. Package(){0x001BFFFF, 1, LNKB, 0 },
  28. Package(){0x001BFFFF, 2, LNKC, 0 },
  29. Package(){0x001BFFFF, 3, LNKD, 0 },
  30. // D25: SerialIo - can't use PIC
  31. // D23: SATA controller
  32. Package(){0x0017FFFF, 0, LNKA, 0 },
  33. // D22: CSME (HECI, IDE-R, Keyboard and Text redirection
  34. Package(){0x0016FFFF, 0, LNKA, 0 },
  35. Package(){0x0016FFFF, 1, LNKB, 0 },
  36. Package(){0x0016FFFF, 2, LNKC, 0 },
  37. Package(){0x0016FFFF, 3, LNKD, 0 },
  38. // D21: SerialIo - can't use PIC
  39. // D20: xHCI, Thermal Subsystem, Camera IO Host Controller
  40. Package(){0x0014FFFF, 0, LNKA, 0 },
  41. Package(){0x0014FFFF, 1, LNKB, 0 },
  42. Package(){0x0014FFFF, 2, LNKC, 0 },
  43. Package(){0x0014FFFF, 3, LNKD, 0 },
  44. // D19: Integrated Sensor Hub - can't use PIC
  45. // Host Bridge
  46. // P.E.G. Root Port D1F0
  47. Package(){0x0001FFFF, 0, LNKA, 0 },
  48. Package(){0x0001FFFF, 1, LNKB, 0 },
  49. Package(){0x0001FFFF, 2, LNKC, 0 },
  50. Package(){0x0001FFFF, 3, LNKD, 0 },
  51. // P.E.G. Root Port D1F1
  52. // P.E.G. Root Port D1F2
  53. // SA IGFX Device
  54. Package(){0x0002FFFF, 0, LNKA, 0 },
  55. // SA Thermal Device
  56. Package(){0x0004FFFF, 0, LNKA, 0 },
  57. // SA SkyCam Device
  58. Package(){0x0005FFFF, 0, LNKA, 0 },
  59. // SA GMM Device
  60. Package(){0x0008FFFF, 0, LNKA, 0 },
  61. })
  62. Name(AR00, Package(){
  63. // PCI Bridge
  64. // D31: cAVS, SMBus, GbE, Nothpeak
  65. Package(){0x001FFFFF, 0, 0, 16 },
  66. Package(){0x001FFFFF, 1, 0, 17 },
  67. Package(){0x001FFFFF, 2, 0, 18 },
  68. Package(){0x001FFFFF, 3, 0, 19 },
  69. // D30: SerialIo and SCS
  70. Package(){0x001EFFFF, 0, 0, 20 },
  71. Package(){0x001EFFFF, 1, 0, 21 },
  72. Package(){0x001EFFFF, 2, 0, 22 },
  73. Package(){0x001EFFFF, 3, 0, 23 },
  74. // D29: PCI Express Port 9-16
  75. Package(){0x001DFFFF, 0, 0, 16 },
  76. Package(){0x001DFFFF, 1, 0, 17 },
  77. Package(){0x001DFFFF, 2, 0, 18 },
  78. Package(){0x001DFFFF, 3, 0, 19 },
  79. // D28: PCI Express Port 1-8
  80. Package(){0x001CFFFF, 0, 0, 16 },
  81. Package(){0x001CFFFF, 1, 0, 17 },
  82. Package(){0x001CFFFF, 2, 0, 18 },
  83. Package(){0x001CFFFF, 3, 0, 19 },
  84. // D27: PCI Express Port 17-20
  85. Package(){0x001BFFFF, 0, 0, 16 },
  86. Package(){0x001BFFFF, 1, 0, 17 },
  87. Package(){0x001BFFFF, 2, 0, 18 },
  88. Package(){0x001BFFFF, 3, 0, 19 },
  89. // D25: SerialIo
  90. Package(){0x0019FFFF, 0, 0, 32 },
  91. Package(){0x0019FFFF, 1, 0, 33 },
  92. Package(){0x0019FFFF, 2, 0, 34 },
  93. // D23: SATA controller
  94. Package(){0x0017FFFF, 0, 0, 16 },
  95. // D22: CSME (HECI, IDE-R, Keyboard and Text redirection
  96. Package(){0x0016FFFF, 0, 0, 16 },
  97. Package(){0x0016FFFF, 1, 0, 17 },
  98. Package(){0x0016FFFF, 2, 0, 18 },
  99. Package(){0x0016FFFF, 3, 0, 19 },
  100. // D21: SerialIo
  101. Package(){0x0015FFFF, 0, 0, 16 },
  102. Package(){0x0015FFFF, 1, 0, 17 },
  103. Package(){0x0015FFFF, 2, 0, 18 },
  104. Package(){0x0015FFFF, 3, 0, 19 },
  105. // D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller
  106. Package(){0x0014FFFF, 0, 0, 16 },
  107. Package(){0x0014FFFF, 1, 0, 17 },
  108. Package(){0x0014FFFF, 2, 0, 18 },
  109. Package(){0x0014FFFF, 3, 0, 19 },
  110. // D19: Integrated Sensor Hub
  111. Package(){0x0013FFFF, 0, 0, 20 },
  112. // Host Bridge
  113. // P.E.G. Root Port D1F0
  114. Package(){0x0001FFFF, 0, 0, 16 },
  115. Package(){0x0001FFFF, 1, 0, 17 },
  116. Package(){0x0001FFFF, 2, 0, 18 },
  117. Package(){0x0001FFFF, 3, 0, 19 },
  118. // P.E.G. Root Port D1F1
  119. // P.E.G. Root Port D1F2
  120. // SA IGFX Device
  121. Package(){0x0002FFFF, 0, 0, 16 },
  122. // SA Thermal Device
  123. Package(){0x0004FFFF, 0, 0, 16 },
  124. // SA SkyCam Device
  125. Package(){0x0005FFFF, 0, 0, 16 },
  126. // SA GMM Device
  127. Package(){0x0008FFFF, 0, 0, 16 },
  128. })
  129. Name(PR04, Package(){
  130. Package(){0x0000FFFF, 0, LNKA, 0 },
  131. Package(){0x0000FFFF, 1, LNKB, 0 },
  132. Package(){0x0000FFFF, 2, LNKC, 0 },
  133. Package(){0x0000FFFF, 3, LNKD, 0 },
  134. })
  135. Name(AR04, Package(){
  136. Package(){0x0000FFFF, 0, 0, 16 },
  137. Package(){0x0000FFFF, 1, 0, 17 },
  138. Package(){0x0000FFFF, 2, 0, 18 },
  139. Package(){0x0000FFFF, 3, 0, 19 },
  140. })
  141. Name(PR05, Package(){
  142. Package(){0x0000FFFF, 0, LNKB, 0 },
  143. Package(){0x0000FFFF, 1, LNKC, 0 },
  144. Package(){0x0000FFFF, 2, LNKD, 0 },
  145. Package(){0x0000FFFF, 3, LNKA, 0 },
  146. })
  147. Name(AR05, Package(){
  148. Package(){0x0000FFFF, 0, 0, 17 },
  149. Package(){0x0000FFFF, 1, 0, 18 },
  150. Package(){0x0000FFFF, 2, 0, 19 },
  151. Package(){0x0000FFFF, 3, 0, 16 },
  152. })
  153. Name(PR06, Package(){
  154. Package(){0x0000FFFF, 0, LNKC, 0 },
  155. Package(){0x0000FFFF, 1, LNKD, 0 },
  156. Package(){0x0000FFFF, 2, LNKA, 0 },
  157. Package(){0x0000FFFF, 3, LNKB, 0 },
  158. })
  159. Name(AR06, Package(){
  160. Package(){0x0000FFFF, 0, 0, 18 },
  161. Package(){0x0000FFFF, 1, 0, 19 },
  162. Package(){0x0000FFFF, 2, 0, 16 },
  163. Package(){0x0000FFFF, 3, 0, 17 },
  164. })
  165. Name(PR07, Package(){
  166. Package(){0x0000FFFF, 0, LNKD, 0 },
  167. Package(){0x0000FFFF, 1, LNKA, 0 },
  168. Package(){0x0000FFFF, 2, LNKB, 0 },
  169. Package(){0x0000FFFF, 3, LNKC, 0 },
  170. })
  171. Name(AR07, Package(){
  172. Package(){0x0000FFFF, 0, 0, 19 },
  173. Package(){0x0000FFFF, 1, 0, 16 },
  174. Package(){0x0000FFFF, 2, 0, 17 },
  175. Package(){0x0000FFFF, 3, 0, 18 },
  176. })
  177. Name(PR08, Package(){
  178. Package(){0x0000FFFF, 0, LNKA, 0 },
  179. Package(){0x0000FFFF, 1, LNKB, 0 },
  180. Package(){0x0000FFFF, 2, LNKC, 0 },
  181. Package(){0x0000FFFF, 3, LNKD, 0 },
  182. })
  183. Name(AR08, Package(){
  184. Package(){0x0000FFFF, 0, 0, 16 },
  185. Package(){0x0000FFFF, 1, 0, 17 },
  186. Package(){0x0000FFFF, 2, 0, 18 },
  187. Package(){0x0000FFFF, 3, 0, 19 },
  188. })
  189. Name(PR09, Package(){
  190. Package(){0x0000FFFF, 0, LNKB, 0 },
  191. Package(){0x0000FFFF, 1, LNKC, 0 },
  192. Package(){0x0000FFFF, 2, LNKD, 0 },
  193. Package(){0x0000FFFF, 3, LNKA, 0 },
  194. })
  195. Name(AR09, Package(){
  196. Package(){0x0000FFFF, 0, 0, 17 },
  197. Package(){0x0000FFFF, 1, 0, 18 },
  198. Package(){0x0000FFFF, 2, 0, 19 },
  199. Package(){0x0000FFFF, 3, 0, 16 },
  200. })
  201. Name(PR0E, Package(){
  202. Package(){0x0000FFFF, 0, LNKC, 0 },
  203. Package(){0x0000FFFF, 1, LNKD, 0 },
  204. Package(){0x0000FFFF, 2, LNKA, 0 },
  205. Package(){0x0000FFFF, 3, LNKB, 0 },
  206. })
  207. Name(AR0E, Package(){
  208. Package(){0x0000FFFF, 0, 0, 18 },
  209. Package(){0x0000FFFF, 1, 0, 19 },
  210. Package(){0x0000FFFF, 2, 0, 16 },
  211. Package(){0x0000FFFF, 3, 0, 17 },
  212. })
  213. Name(PR0F, Package(){
  214. Package(){0x0000FFFF, 0, LNKD, 0 },
  215. Package(){0x0000FFFF, 1, LNKA, 0 },
  216. Package(){0x0000FFFF, 2, LNKB, 0 },
  217. Package(){0x0000FFFF, 3, LNKC, 0 },
  218. })
  219. Name(AR0F, Package(){
  220. Package(){0x0000FFFF, 0, 0, 19 },
  221. Package(){0x0000FFFF, 1, 0, 16 },
  222. Package(){0x0000FFFF, 2, 0, 17 },
  223. Package(){0x0000FFFF, 3, 0, 18 },
  224. })
  225. Name(PR02, Package(){
  226. Package(){0x0000FFFF, 0, LNKA, 0 },
  227. Package(){0x0000FFFF, 1, LNKB, 0 },
  228. Package(){0x0000FFFF, 2, LNKC, 0 },
  229. Package(){0x0000FFFF, 3, LNKD, 0 },
  230. })
  231. Name(AR02, Package(){
  232. // P.E.G. Port Slot x16
  233. Package(){0x0000FFFF, 0, 0, 16 },
  234. Package(){0x0000FFFF, 1, 0, 17 },
  235. Package(){0x0000FFFF, 2, 0, 18 },
  236. Package(){0x0000FFFF, 3, 0, 19 },
  237. })
  238. Name(PR0A, Package(){
  239. // P.E.G. Port Slot x8
  240. Package(){0x0000FFFF, 0, LNKB, 0 },
  241. Package(){0x0000FFFF, 1, LNKC, 0 },
  242. Package(){0x0000FFFF, 2, LNKD, 0 },
  243. Package(){0x0000FFFF, 3, LNKA, 0 },
  244. })
  245. Name(AR0A, Package(){
  246. // P.E.G. Port Slot x8
  247. Package(){0x0000FFFF, 0, 0, 17 },
  248. Package(){0x0000FFFF, 1, 0, 18 },
  249. Package(){0x0000FFFF, 2, 0, 19 },
  250. Package(){0x0000FFFF, 3, 0, 16 },
  251. })
  252. Name(PR0B, Package(){
  253. // P.E.G. Port Slot x4
  254. Package(){0x0000FFFF, 0, LNKC, 0 },
  255. Package(){0x0000FFFF, 1, LNKD, 0 },
  256. Package(){0x0000FFFF, 2, LNKA, 0 },
  257. Package(){0x0000FFFF, 3, LNKB, 0 },
  258. })
  259. Name(AR0B, Package(){
  260. // P.E.G. Port Slot x4
  261. Package(){0x0000FFFF, 0, 0, 18 },
  262. Package(){0x0000FFFF, 1, 0, 19 },
  263. Package(){0x0000FFFF, 2, 0, 16 },
  264. Package(){0x0000FFFF, 3, 0, 17 },
  265. })
  266. //---------------------------------------------------------------------------
  267. // List of IRQ resource buffers compatible with _PRS return format.
  268. //---------------------------------------------------------------------------
  269. // Naming legend:
  270. // RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.
  271. // Note. PRSy name is generated if IRQ Link name starts from "LNK".
  272. // HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.
  273. //---------------------------------------------------------------------------
  274. Name(PRSA, ResourceTemplate(){ // Link name: LNKA
  275. IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}
  276. })
  277. Alias(PRSA,PRSB) // Link name: LNKB
  278. Alias(PRSA,PRSC) // Link name: LNKC
  279. Alias(PRSA,PRSD) // Link name: LNKD
  280. Alias(PRSA,PRSE) // Link name: LNKE
  281. Alias(PRSA,PRSF) // Link name: LNKF
  282. Alias(PRSA,PRSG) // Link name: LNKG
  283. Alias(PRSA,PRSH) // Link name: LNKH
  284. //---------------------------------------------------------------------------
  285. // Begin PCI tree object scope
  286. //---------------------------------------------------------------------------
  287. Device(PCI0) { // PCI Bridge "Host Bridge"
  288. Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
  289. Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID
  290. Name(_ADR, 0x00000000)
  291. Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
  292. Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root PCI Bus
  293. Name(_UID, 0x0000) // Unique Bus ID, optional
  294. Method(_PRT,0) {
  295. If(PICM) {Return(AR00)} // APIC mode
  296. Return (PR00) // PIC Mode
  297. } // end _PRT
  298. Include("HostBus.asl")
  299. } // end PCI0 Bridge "Host Bridge"
  300. } // end _SB scope