PCI_DRC.ASL 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116
  1. /** @file
  2. ACPI DSDT table
  3. Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. Scope (\_SB.PCI0){
  7. Device(PDRC)
  8. {
  9. //
  10. // PCI Device Resource Consumption
  11. //
  12. Name(_HID,EISAID("PNP0C02"))
  13. Name(_UID,1)
  14. Name(BUF0,ResourceTemplate()
  15. {
  16. //
  17. // MCH BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.48h
  18. //
  19. Memory32Fixed(ReadWrite,0,0x08000,MCHB)
  20. //
  21. // DMI BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.68h
  22. //
  23. Memory32Fixed(ReadWrite,0,0x01000,DMIB)
  24. //
  25. // EP BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.40h
  26. //
  27. Memory32Fixed(ReadWrite,0,0x01000,EGPB)
  28. //
  29. // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h
  30. //
  31. Memory32Fixed(ReadWrite,0,0,PCIX)
  32. //
  33. // MISC ICH TTT base address reserved for the TxT module use. Check if the hard code meets the real configuration.
  34. // If not, dynamically update it like the _CRS method below.
  35. //
  36. Memory32Fixed(ReadWrite,0xFED20000,0x20000)
  37. //
  38. // VTD engine memory range. Check if the hard code meets the real configuration.
  39. // If not, dynamically update it like the _CRS method below.
  40. //
  41. Memory32Fixed(ReadOnly, 0xFED90000, 0x00004000)
  42. //
  43. // MISC ICH. Check if the hard code meets the real configuration.
  44. // If not, dynamically update it like the _CRS method below.
  45. //
  46. Memory32Fixed(ReadWrite,0xFED45000,0x4B000,TPMM)
  47. //
  48. // FLASH range
  49. //
  50. Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) //16MB as per IOH spec
  51. //
  52. // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
  53. //
  54. Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
  55. //
  56. // Sx handler reserved MMIO
  57. //
  58. Memory32Fixed (ReadWrite, 0, 0, SXRE)
  59. //
  60. // Reserve HPET address decode range
  61. //
  62. Memory32Fixed (ReadWrite, 0, 0, HPET)
  63. })
  64. Method(_CRS,0,Serialized)
  65. {
  66. CreateDwordField(BUF0,^MCHB._BAS,MBR0)
  67. Store(\_SB.PCI0.GMHB(), MBR0)
  68. CreateDwordField(BUF0,^DMIB._BAS,DBR0)
  69. Store(\_SB.PCI0.GDMB(), DBR0)
  70. CreateDwordField(BUF0,^EGPB._BAS,EBR0)
  71. Store(\_SB.PCI0.GEPB(), EBR0)
  72. CreateDwordField(BUF0,^PCIX._BAS,XBR0)
  73. Store(\_SB.PCI0.GPCB(), XBR0)
  74. CreateDwordField(BUF0,^PCIX._LEN,XSZ0)
  75. Store(\_SB.PCI0.GPCL(), XSZ0)
  76. CreateDwordField(BUF0,^SXRE._BAS,SXRA)
  77. Store(SXRB, SXRA)
  78. CreateDwordField(BUF0,^SXRE._LEN,SXRL)
  79. Store(SXRS, SXRL)
  80. // HPET device claims the resource in LPC_DEV.ASL.
  81. If(LNOT(HPTE)){
  82. CreateDwordField(BUF0,^HPET._BAS,HBAS)
  83. CreateDwordField(BUF0,^HPET._LEN,HLEN)
  84. Store(HPTB, HBAS)
  85. Store(0x400, HLEN)
  86. }
  87. Return(BUF0)
  88. }
  89. } //end of PDRC
  90. } // end of SB