Cn9131DbA.dsc.inc 3.2 KB

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  1. ## @file
  2. # Component description file for the CN9131 Development Board (variant A)
  3. #
  4. # Copyright (c) 2019 Marvell International Ltd.<BR>
  5. #
  6. # SPDX-License-Identifier: BSD-2-Clause-Patent
  7. #
  8. ##
  9. ################################################################################
  10. #
  11. # Pcd Section - list of all EDK II PCD Entries defined by this Platform
  12. #
  13. ################################################################################
  14. [PcdsFixedAtBuild.common]
  15. # CP115 count
  16. gMarvellTokenSpaceGuid.PcdMaxCpCount|2
  17. # MPP
  18. gMarvellTokenSpaceGuid.PcdMppChipCount|3
  19. # CP115 #1 MPP
  20. gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
  21. gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
  22. gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
  23. gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
  24. gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
  25. gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x0 }
  26. gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x7, 0x2, 0x2, 0x0 }
  27. gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
  28. gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
  29. gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
  30. # ComPhy
  31. gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
  32. # ComPhy1
  33. # 0: PCIE0 5 Gbps
  34. # 1: PCIE0 5 Gbps
  35. # 2: UNCONNECTED
  36. # 3: USB3_HOST1 5 Gbps
  37. # 4: SFI 10.31 Gbps
  38. # 5: SATA1 5 Gbps
  39. gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)}
  40. gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_DEFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
  41. # UtmiPhy
  42. gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 }
  43. gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
  44. # MDIO
  45. gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
  46. # PHY
  47. gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
  48. gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
  49. gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
  50. gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
  51. # NET
  52. gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }
  53. gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
  54. gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) }
  55. gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI) }
  56. gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF }
  57. gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }
  58. gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }
  59. gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
  60. # NonDiscoverableDevices
  61. gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }
  62. gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
  63. gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }