BeagleBoard.h 6.6 KB

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  1. /** @file
  2. * Header defining the BeagleBoard constants (Base addresses, sizes, flags)
  3. *
  4. * Copyright (c) 2011, ARM Limited. All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-2-Clause-Patent
  7. *
  8. **/
  9. #ifndef __BEAGLEBOARD_PLATFORM_H__
  10. #define __BEAGLEBOARD_PLATFORM_H__
  11. // DDR attributes
  12. #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
  13. #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
  14. // SoC registers. L3 interconnects
  15. #define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000
  16. #define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000
  17. #define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
  18. // SoC registers. L4 interconnects
  19. #define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000
  20. #define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000
  21. #define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
  22. #if 0
  23. /*******************************************
  24. // Platform Memory Map
  25. *******************************************/
  26. // Can be NOR, DOC, DRAM, SRAM
  27. #define ARM_EB_REMAP_BASE 0x00000000
  28. #define ARM_EB_REMAP_SZ 0x04000000
  29. // Motherboard Peripheral and On-chip peripheral
  30. #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000
  31. #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000
  32. #define ARM_EB_BOARD_PERIPH_BASE 0x10000000
  33. //#define ARM_EB_CHIP_PERIPH_BASE 0x10020000
  34. // SMC
  35. #define ARM_EB_SMC_BASE 0x40000000
  36. #define ARM_EB_SMC_SZ 0x20000000
  37. // NOR Flash 1
  38. #define ARM_EB_SMB_NOR_BASE 0x40000000
  39. #define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */
  40. // DOC Flash
  41. #define ARM_EB_SMB_DOC_BASE 0x44000000
  42. #define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */
  43. // SRAM
  44. #define ARM_EB_SMB_SRAM_BASE 0x48000000
  45. #define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */
  46. // USB, Ethernet, VRAM
  47. #define ARM_EB_SMB_PERIPH_BASE 0x4E000000
  48. //#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000
  49. #define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */
  50. // DRAM
  51. #define ARM_EB_DRAM_BASE 0x70000000
  52. #define ARM_EB_DRAM_SZ 0x10000000
  53. // Logic Tile
  54. #define ARM_EB_LOGIC_TILE_BASE 0xC0000000
  55. #define ARM_EB_LOGIC_TILE_SZ 0x40000000
  56. /*******************************************
  57. // Motherboard peripherals
  58. *******************************************/
  59. // Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)
  60. #define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
  61. #define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
  62. #define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)
  63. #define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
  64. #define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
  65. #define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)
  66. #define ARM_EB_SYS_CLCD (ARM_EB_BOARD_PERIPH_BASE + 0x00050)
  67. #define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)
  68. #define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)
  69. #define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)
  70. #define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)
  71. #define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)
  72. // SP810 Controller
  73. #define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)
  74. // SYSTRCL Register
  75. #define ARM_EB_SYSCTRL 0x10001000
  76. // Uart0
  77. #define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)
  78. #define PL011_CONSOLE_UART_SPEED 115200
  79. // SP804 Timer Bases
  80. #define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)
  81. #define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)
  82. #define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)
  83. #define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)
  84. // PL301 RTC
  85. #define PL031_RTC_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x17000)
  86. // Dynamic Memory Controller Base
  87. #define ARM_EB_DMC_BASE 0x10018000
  88. // Static Memory Controller Base
  89. #define ARM_EB_SMC_CTRL_BASE 0x10080000
  90. #define PL111_CLCD_BASE 0x10020000
  91. //TODO: FIXME ... Reserved the memory in UEFI !!! Otherwise risk of corruption
  92. #define PL111_CLCD_VRAM_BASE 0x78000000
  93. #define ARM_EB_SYS_OSCCLK4 0x1000001C
  94. /*// System Configuration Controller register Base addresses
  95. //#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000
  96. #define ARM_EB_SYS_CFGRW0_REG 0x100E2000
  97. #define ARM_EB_SYS_CFGRW1_REG 0x100E2004
  98. #define ARM_EB_SYS_CFGRW2_REG 0x100E2008
  99. #define ARM_EB_CFGRW1_REMAP_NOR0 0
  100. #define ARM_EB_CFGRW1_REMAP_NOR1 (1 << 28)
  101. #define ARM_EB_CFGRW1_REMAP_EXT_AXI (1 << 29)
  102. #define ARM_EB_CFGRW1_REMAP_DRAM (1 << 30)
  103. // PL301 Fast AXI Base Address
  104. #define ARM_EB_FAXI_BASE 0x100E9000
  105. // L2x0 Cache Controller Base Address
  106. //#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/
  107. // PL031 RTC - Other settings
  108. #define PL031_PPM_ACCURACY 300000000
  109. /*******************************************
  110. // Interrupt Map
  111. *******************************************/
  112. // Timer Interrupts
  113. #define TIMER01_INTERRUPT_NUM 34
  114. #define TIMER23_INTERRUPT_NUM 35
  115. /*******************************************
  116. // EFI Memory Map in Permanent Memory (DRAM)
  117. *******************************************/
  118. // This region is allocated at the bottom of the DRAM. It will be used
  119. // for fixed address allocations such as Vector Table
  120. #define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB
  121. // This region is the memory declared to PEI as permanent memory for PEI
  122. // and DXE. EFI stacks and heaps will be declared in this region.
  123. #define ARM_EB_EFI_MEMORY_REGION_SZ 0x1000000
  124. #endif
  125. typedef enum {
  126. REVISION_XM,
  127. REVISION_UNKNOWN0,
  128. REVISION_UNKNOWN1,
  129. REVISION_UNKNOWN2,
  130. REVISION_UNKNOWN3,
  131. REVISION_C4,
  132. REVISION_C123,
  133. REVISION_AB,
  134. } BEAGLEBOARD_REVISION;
  135. #endif