ArmPlatform.h 7.4 KB

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  1. /** @file
  2. *
  3. * Copyright (c) 2013-2017, ARM Limited. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-2-Clause-Patent
  6. *
  7. **/
  8. #ifndef __ARM_JUNO_H__
  9. #define __ARM_JUNO_H__
  10. //#include <VExpressMotherBoard.h>
  11. /***********************************************************************************
  12. // Platform Memory Map
  13. ************************************************************************************/
  14. // Motherboard Peripheral and On-chip peripheral
  15. #define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
  16. #define ARM_VE_BOARD_SYS_ID 0x0000
  17. #define ARM_VE_BOARD_SYS_PCIE_GBE_L 0x0074
  18. #define ARM_VE_BOARD_SYS_PCIE_GBE_H 0x0078
  19. #define ARM_VE_BOARD_SYS_ID_REV(word) ((word >> 28) & 0xff)
  20. // NOR Flash 0
  21. #define ARM_VE_SMB_NOR0_BASE 0x08000000
  22. #define ARM_VE_SMB_NOR0_SZ SIZE_64MB
  23. // Off-Chip peripherals (USB, Ethernet, VRAM)
  24. #define ARM_VE_SMB_PERIPH_BASE 0x18000000
  25. #define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_2MB)
  26. // On-Chip non-secure ROM
  27. #define ARM_JUNO_NON_SECURE_ROM_BASE 0x1F000000
  28. #define ARM_JUNO_NON_SECURE_ROM_SZ SIZE_16MB
  29. // On-Chip Peripherals
  30. #define ARM_JUNO_PERIPHERALS_BASE 0x20000000
  31. #define ARM_JUNO_PERIPHERALS_SZ 0x0E000000
  32. // PCIe MSI address window
  33. #define ARM_JUNO_GIV2M_MSI_BASE 0x2c1c0000
  34. #define ARM_JUNO_GIV2M_MSI_SZ SIZE_256KB
  35. // PCIe MSI to SPI mapping range
  36. #define ARM_JUNO_GIV2M_MSI_SPI_BASE 224
  37. #define ARM_JUNO_GIV2M_MSI_SPI_COUNT 127 //TRM says last SPI is 351, 351-224=127
  38. // On-Chip non-secure SRAM
  39. #define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E000000
  40. #define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB
  41. // SOC peripherals (HDLCD, UART, I2C, I2S, USB, SMC-PL354, etc)
  42. #define ARM_JUNO_SOC_PERIPHERALS_BASE 0x7FF50000
  43. #define ARM_JUNO_SOC_PERIPHERALS_SZ (SIZE_64KB * 9)
  44. // 6GB of DRAM from the 64bit address space
  45. #define ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE 0x0880000000
  46. #define ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ (SIZE_2GB + SIZE_4GB)
  47. //
  48. // ACPI table information used to initialize tables.
  49. //
  50. #define EFI_ACPI_ARM_OEM_ID 'A','R','M','L','T','D' // OEMID 6 bytes long
  51. #define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('A','R','M','-','J','U','N','O') // OEM table id 8 bytes long
  52. #define EFI_ACPI_ARM_OEM_REVISION 0x20140727
  53. #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
  54. #define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
  55. // A macro to initialise the common header part of EFI ACPI tables as defined by
  56. // EFI_ACPI_DESCRIPTION_HEADER structure.
  57. #define ARM_ACPI_HEADER(Signature, Type, Revision) { \
  58. Signature, /* UINT32 Signature */ \
  59. sizeof (Type), /* UINT32 Length */ \
  60. Revision, /* UINT8 Revision */ \
  61. 0, /* UINT8 Checksum */ \
  62. { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
  63. EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
  64. EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
  65. EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
  66. EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
  67. }
  68. //
  69. // Hardware platform identifiers
  70. //
  71. #define JUNO_REVISION_PROTOTYPE 0
  72. #define JUNO_REVISION_R0 1
  73. #define JUNO_REVISION_R1 2
  74. #define JUNO_REVISION_R2 3
  75. #define JUNO_REVISION_UKNOWN 0xFF
  76. //
  77. // We detect whether we are running on a Juno r0, r1 or r2
  78. // board at runtime by checking the value of board SYS_ID
  79. //
  80. #define GetJunoRevision(JunoRevision) \
  81. { \
  82. UINT32 SysId; \
  83. SysId = MmioRead32 (ARM_VE_BOARD_PERIPH_BASE+ARM_VE_BOARD_SYS_ID); \
  84. JunoRevision = ARM_VE_BOARD_SYS_ID_REV( SysId ); \
  85. }
  86. // Define if the exported ACPI Tables are based on ACPI 5.0 spec or latest
  87. //#define ARM_JUNO_ACPI_5_0
  88. //
  89. // Address of the system registers that contain the MAC address
  90. // assigned to the PCI Gigabyte Ethernet device.
  91. //
  92. #define ARM_JUNO_SYS_PCIGBE_L (ARM_VE_BOARD_PERIPH_BASE + ARM_VE_BOARD_SYS_PCIE_GBE_L)
  93. #define ARM_JUNO_SYS_PCIGBE_H (ARM_VE_BOARD_PERIPH_BASE + ARM_VE_BOARD_SYS_PCIE_GBE_H)
  94. /***********************************************************************************
  95. // Motherboard memory-mapped peripherals
  96. ************************************************************************************/
  97. // Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
  98. #define ARM_VE_SYS_ID_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00000)
  99. #define ARM_VE_SYS_SW_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00004)
  100. #define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)
  101. #define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
  102. #define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
  103. #define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)
  104. #define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
  105. #define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
  106. #define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)
  107. #define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)
  108. #define ARM_VE_SYS_CFGSWR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00058)
  109. #define ARM_VE_SYS_MISC (ARM_VE_BOARD_PERIPH_BASE + 0x00060)
  110. #define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)
  111. #define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)
  112. #define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)
  113. #define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)
  114. #define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)
  115. //
  116. // Sites where the peripheral is fitted
  117. //
  118. #define ARM_VE_UNSUPPORTED ~0
  119. #define ARM_VE_MOTHERBOARD_SITE 0
  120. #define ARM_VE_DAUGHTERBOARD_1_SITE 1
  121. #define ARM_VE_DAUGHTERBOARD_2_SITE 2
  122. #define VIRTUAL_SYS_CFG(site,func) (((site) << 24) | (func))
  123. //
  124. // System Configuration Control Functions
  125. //
  126. #define SYS_CFG_OSC 1
  127. #define SYS_CFG_VOLT 2
  128. #define SYS_CFG_AMP 3
  129. #define SYS_CFG_TEMP 4
  130. #define SYS_CFG_RESET 5
  131. #define SYS_CFG_SCC 6
  132. #define SYS_CFG_MUXFPGA 7
  133. #define SYS_CFG_SHUTDOWN 8
  134. #define SYS_CFG_REBOOT 9
  135. #define SYS_CFG_DVIMODE 11
  136. #define SYS_CFG_POWER 12
  137. // Oscillator for Site 1
  138. #define SYS_CFG_OSC_SITE1 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_1_SITE, \
  139. SYS_CFG_OSC)
  140. // Oscillator for Site 2
  141. #define SYS_CFG_OSC_SITE2 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_2_SITE, \
  142. SYS_CFG_OSC)
  143. // Can not access the battery backed-up hardware clock on the
  144. // Versatile Express motherboard
  145. #define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)
  146. #endif