OverdriveBoard.dts 12 KB

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  1. /*
  2. * DTS file for AMD Seattle (Rev.B) Overdrive Development Board
  3. *
  4. * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-2-Clause-Patent
  7. *
  8. */
  9. /dts-v1/;
  10. / {
  11. model = "AMD Seattle (Rev.B) Development Board (Overdrive)";
  12. compatible = "amd,seattle-overdrive", "amd,seattle";
  13. interrupt-parent = <&gic>;
  14. #address-cells = <0x2>;
  15. #size-cells = <0x2>;
  16. gic: interrupt-controller@e1101000 {
  17. compatible = "arm,gic-400", "arm,cortex-a15-gic";
  18. interrupt-controller;
  19. #interrupt-cells = <0x3>;
  20. #address-cells = <0x2>;
  21. #size-cells = <0x2>;
  22. reg = <0x0 0xe1110000 0x0 0x1000>,
  23. <0x0 0xe112f000 0x0 0x2000>,
  24. <0x0 0xe1140000 0x0 0x2000>,
  25. <0x0 0xe1160000 0x0 0x2000>;
  26. interrupts = <0x1 0x9 0xf04>;
  27. ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>;
  28. msi: v2m@e0080000 {
  29. compatible = "arm,gic-v2m-frame";
  30. msi-controller;
  31. reg = <0x0 0x80000 0x0 0x1000>;
  32. };
  33. };
  34. timer {
  35. compatible = "arm,armv8-timer";
  36. interrupts = <0x1 0xd 0xff04>,
  37. <0x1 0xe 0xff04>,
  38. <0x1 0xb 0xff04>,
  39. <0x1 0xa 0xff04>;
  40. };
  41. smb {
  42. compatible = "simple-bus";
  43. #address-cells = <0x2>;
  44. #size-cells = <0x2>;
  45. ranges;
  46. /*
  47. * dma-ranges is 40-bit address space containing:
  48. * - GICv2m MSI register is at 0xe0080000
  49. * - DRAM range [0x8000000000 to 0xffffffffff]
  50. */
  51. dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
  52. sata_clk: clk333mhz {
  53. compatible = "fixed-clock";
  54. #clock-cells = <0x0>;
  55. clock-frequency = <333000000>;
  56. clock-output-names = "sataclk_333mhz";
  57. };
  58. i2c_clk: clk250mhz_4 {
  59. compatible = "fixed-clock";
  60. #clock-cells = <0x0>;
  61. clock-frequency = <250000000>;
  62. clock-output-names = "miscclk_250mhz";
  63. };
  64. apb_clk: clk100mhz_1 {
  65. compatible = "fixed-clock";
  66. #clock-cells = <0x0>;
  67. clock-frequency = <100000000>;
  68. clock-output-names = "uartspiclk_100mhz";
  69. };
  70. sata0_smmu: smmu@e0200000 {
  71. compatible = "arm,mmu-401";
  72. reg = <0 0xe0200000 0 0x10000>;
  73. #global-interrupts = <1>;
  74. interrupts = /* Uses combined intr for both
  75. * global and context
  76. */
  77. <0 332 4>,
  78. <0 332 4>;
  79. #iommu-cells = <2>;
  80. dma-coherent;
  81. };
  82. sata1_smmu: smmu@e0c00000 {
  83. compatible = "arm,mmu-401";
  84. reg = <0 0xe0c00000 0 0x10000>;
  85. #global-interrupts = <1>;
  86. interrupts = /* Uses combined intr for both
  87. * global and context
  88. */
  89. <0 331 4>,
  90. <0 331 4>;
  91. #iommu-cells = <1>;
  92. dma-coherent;
  93. };
  94. sata@e0300000 {
  95. compatible = "snps,dwc-ahci";
  96. reg = <0x0 0xe0300000 0x0 0xf0000>;
  97. interrupts = <0x0 0x163 0x4>;
  98. clocks = <&sata_clk>;
  99. dma-coherent;
  100. iommus = <&sata0_smmu 0x0 0x1f>;
  101. };
  102. sata@e0d00000 {
  103. status = "disabled";
  104. compatible = "snps,dwc-ahci";
  105. reg = <0x0 0xe0d00000 0x0 0xf0000>;
  106. interrupts = <0x0 0x162 0x4>;
  107. clocks = <&sata_clk>;
  108. dma-coherent;
  109. iommus = <&sata1_smmu 0x0e>,
  110. <&sata1_smmu 0x0f>,
  111. <&sata1_smmu 0x1e>;
  112. };
  113. i2c@e1000000 {
  114. compatible = "snps,designware-i2c";
  115. reg = <0x0 0xe1000000 0x0 0x1000>;
  116. interrupts = <0x0 0x165 0x4>;
  117. clocks = <&i2c_clk>;
  118. };
  119. i2c@e0050000 {
  120. compatible = "snps,designware-i2c";
  121. reg = <0x0 0xe0050000 0x0 0x1000>;
  122. interrupts = <0x0 0x154 0x4>;
  123. clocks = <&i2c_clk>;
  124. };
  125. serial@e1010000 {
  126. compatible = "arm,pl011", "arm,primecell";
  127. reg = <0x0 0xe1010000 0x0 0x1000>;
  128. interrupts = <0x0 0x148 0x4>;
  129. clocks = <&apb_clk &apb_clk>;
  130. clock-names = "uartclk", "apb_pclk";
  131. };
  132. ssp@e1020000 {
  133. compatible = "arm,pl022", "arm,primecell";
  134. reg = <0x0 0xe1020000 0x0 0x1000>;
  135. spi-controller;
  136. interrupts = <0x0 0x14a 0x4>;
  137. clocks = <&apb_clk>;
  138. clock-names = "apb_pclk";
  139. };
  140. ssp@e1030000 {
  141. compatible = "arm,pl022", "arm,primecell";
  142. reg = <0x0 0xe1030000 0x0 0x1000>;
  143. spi-controller;
  144. interrupts = <0x0 0x149 0x4>;
  145. clocks = <&apb_clk>;
  146. clock-names = "apb_pclk";
  147. num-cs = <0x1>;
  148. #address-cells = <0x1>;
  149. #size-cells = <0x0>;
  150. sdcard@0 {
  151. compatible = "mmc-spi-slot";
  152. reg = <0x0>;
  153. spi-max-frequency = <20000000>;
  154. voltage-ranges = <3200 3400>;
  155. pl022,hierarchy = <0x0>;
  156. pl022,interface = <0x0>;
  157. pl022,com-mode = <0x0>;
  158. pl022,rx-level-trig = <0x0>;
  159. pl022,tx-level-trig = <0x0>;
  160. };
  161. };
  162. gpio@e1050000 { /* [0 : 7] */
  163. compatible = "arm,pl061", "arm,primecell";
  164. #gpio-cells = <0x2>;
  165. reg = <0x0 0xe1050000 0x0 0x1000>;
  166. gpio-controller;
  167. interrupt-controller;
  168. #interrupt-cells = <0x2>;
  169. interrupts = <0x0 0x166 0x4>;
  170. clocks = <&apb_clk>;
  171. clock-names = "apb_pclk";
  172. };
  173. gpio@e0020000 { /* [8 : 15] */
  174. status = "disabled";
  175. compatible = "arm,pl061", "arm,primecell";
  176. #gpio-cells = <0x2>;
  177. reg = <0x0 0xe0020000 0x0 0x1000>;
  178. gpio-controller;
  179. interrupt-controller;
  180. #interrupt-cells = <0x2>;
  181. interrupts = <0x0 0x16e 0x4>;
  182. clocks = <&apb_clk>;
  183. clock-names = "apb_pclk";
  184. };
  185. gpio@e0030000 { /* [16 : 23] */
  186. status = "disabled";
  187. compatible = "arm,pl061", "arm,primecell";
  188. #gpio-cells = <0x2>;
  189. reg = <0x0 0xe0030000 0x0 0x1000>;
  190. gpio-controller;
  191. interrupt-controller;
  192. #interrupt-cells = <0x2>;
  193. interrupts = <0x0 0x16d 0x4>;
  194. clocks = <&apb_clk>;
  195. clock-names = "apb_pclk";
  196. };
  197. gpio@e0080000 { /* [24] */
  198. compatible = "arm,pl061", "arm,primecell";
  199. #gpio-cells = <0x2>;
  200. reg = <0x0 0xe0080000 0x0 0x1000>;
  201. gpio-controller;
  202. interrupt-controller;
  203. #interrupt-cells = <0x2>;
  204. interrupts = <0x0 0x169 0x4>;
  205. clocks = <&apb_clk>;
  206. clock-names = "apb_pclk";
  207. };
  208. ccp: ccp@e0100000 {
  209. compatible = "amd,ccp-seattle-v1a";
  210. reg = <0x0 0xe0100000 0x0 0x10000>;
  211. interrupts = <0x0 0x3 0x4>;
  212. dma-coherent;
  213. amd,zlib-support = <0x1>;
  214. iommus = <&sata1_smmu 0x00>,
  215. <&sata1_smmu 0x02>,
  216. <&sata1_smmu 0x40>,
  217. <&sata1_smmu 0x42>;
  218. };
  219. pcie: pcie@f0000000 {
  220. compatible = "pci-host-ecam-generic";
  221. #address-cells = <0x3>;
  222. #size-cells = <0x2>;
  223. #interrupt-cells = <0x1>;
  224. iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
  225. device_type = "pci";
  226. bus-range = <0x0 0x7f>;
  227. msi-parent = <&msi>;
  228. reg = <0x0 0xf0000000 0x0 0x10000000>;
  229. interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
  230. interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x120 0x1>,
  231. <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x121 0x1>,
  232. <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x122 0x1>,
  233. <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x123 0x1>,
  234. <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x124 0x1>,
  235. <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x125 0x1>,
  236. <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x126 0x1>,
  237. <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x127 0x1>,
  238. <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x128 0x1>,
  239. <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x129 0x1>,
  240. <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12a 0x1>,
  241. <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x12b 0x1>;
  242. dma-coherent;
  243. dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
  244. ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */
  245. <0x2000000 0x0 0x40000000 0x0 0x40000000 0x00 0x80000000>, /* 32-bit MMIO (size=2G) */
  246. <0x3000000 0x1 0x00000000 0x1 0x00000000 0x7f 0x00000000>; /* 64-bit MMIO (size= 124G) */
  247. };
  248. pcie_smmu: smmu@e0a00000 {
  249. compatible = "arm,mmu-401";
  250. reg = <0 0xe0a00000 0 0x10000>;
  251. #global-interrupts = <1>;
  252. interrupts = /* Uses combined intr for both
  253. * global and context
  254. */
  255. <0 333 4>,
  256. <0 333 4>;
  257. #iommu-cells = <1>;
  258. dma-coherent;
  259. };
  260. ccn@e8000000 {
  261. compatible = "arm,ccn-504";
  262. reg = <0x0 0xe8000000 0x0 0x1000000>;
  263. interrupts = <0x0 0x17c 0x4>;
  264. };
  265. gwdt@e0bb0000 {
  266. status = "disabled";
  267. compatible = "arm,sbsa-gwdt";
  268. reg = <0x0 0xe0bb0000 0x0 0x10000
  269. 0x0 0xe0bc0000 0x0 0x10000>;
  270. reg-names = "refresh", "control";
  271. interrupts = <0x0 0x151 0x4>;
  272. interrupt-names = "ws0";
  273. };
  274. kcs@e0010000 {
  275. status = "disabled";
  276. compatible = "ipmi-kcs";
  277. device_type = "ipmi";
  278. reg = <0x0 0xe0010000 0 0x8>;
  279. interrupts = <0 389 4>;
  280. interrupt-names = "ipmi_kcs";
  281. reg-size = <1>;
  282. reg-spacing = <4>;
  283. };
  284. xgmacclk0_dma: clk250mhz_0 {
  285. compatible = "fixed-clock";
  286. #clock-cells = <0x0>;
  287. clock-frequency = <250000000>;
  288. clock-output-names = "xgmacclk0_dma_250mhz";
  289. };
  290. xgmacclk0_ptp: clk250mhz_1 {
  291. compatible = "fixed-clock";
  292. #clock-cells = <0x0>;
  293. clock-frequency = <250000000>;
  294. clock-output-names = "xgmacclk0_ptp_250mhz";
  295. };
  296. xgmacclk1_dma: clk250mhz_2 {
  297. compatible = "fixed-clock";
  298. #clock-cells = <0x0>;
  299. clock-frequency = <250000000>;
  300. clock-output-names = "xgmacclk1_dma_250mhz";
  301. };
  302. xgmacclk1_ptp: clk250mhz_3 {
  303. compatible = "fixed-clock";
  304. #clock-cells = <0x0>;
  305. clock-frequency = <250000000>;
  306. clock-output-names = "xgmacclk1_ptp_250mhz";
  307. };
  308. xgmac0_phy: phy@e1240800 {
  309. status = "disabled";
  310. compatible = "amd,xgbe-phy-seattle-v1a";
  311. reg = <0x0 0xe1240800 0x0 0x0400>, /* SERDES RX/TX0 */
  312. <0x0 0xe1250000 0x0 0x0060>, /* SERDES IR 1/2 */
  313. <0x0 0xe12500f8 0x0 0x0004>; /* SERDES IR 2/2 */
  314. interrupts = <0x0 0x143 0x4>;
  315. amd,speed-set = <0x0>;
  316. amd,serdes-blwc = <0x1 0x1 0x0>;
  317. amd,serdes-cdr-rate = <0x2 0x2 0x7>;
  318. amd,serdes-pq-skew = <0xa 0xa 0x12>;
  319. amd,serdes-tx-amp = <0xf 0xf 0xa>;
  320. amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
  321. amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
  322. };
  323. xgmac1_phy: phy@e1240c00 {
  324. status = "disabled";
  325. compatible = "amd,xgbe-phy-seattle-v1a";
  326. reg = <0x0 0xe1240c00 0x0 0x0400>, /* SERDES RX/TX0 */
  327. <0x0 0xe1250080 0x0 0x0060>, /* SERDES IR 1/2 */
  328. <0x0 0xe12500fc 0x0 0x0004>; /* SERDES IR 2/2 */
  329. interrupts = <0x0 0x142 0x4>;
  330. amd,speed-set = <0x0>;
  331. amd,serdes-blwc = <0x1 0x1 0x0>;
  332. amd,serdes-cdr-rate = <0x2 0x2 0x7>;
  333. amd,serdes-pq-skew = <0xa 0xa 0x12>;
  334. amd,serdes-tx-amp = <0xf 0xf 0xa>;
  335. amd,serdes-dfe-tap-config = <0x3 0x3 0x1>;
  336. amd,serdes-dfe-tap-enable = <0x0 0x0 0x7f>;
  337. };
  338. xgmac0_smmu: smmu@e0600000 {
  339. compatible = "arm,mmu-401";
  340. reg = <0 0xe0600000 0 0x10000>;
  341. #global-interrupts = <1>;
  342. interrupts = /* Uses combined intr for both
  343. * global and context
  344. */
  345. <0 336 4>,
  346. <0 336 4>;
  347. #iommu-cells = <2>;
  348. dma-coherent;
  349. };
  350. xgmac1_smmu: smmu@e0800000 {
  351. compatible = "arm,mmu-401";
  352. reg = <0 0xe0800000 0 0x10000>;
  353. #global-interrupts = <1>;
  354. interrupts = /* Uses combined intr for both
  355. * global and context
  356. */
  357. <0 335 4>,
  358. <0 335 4>;
  359. #iommu-cells = <2>;
  360. dma-coherent;
  361. };
  362. xgmac@e0700000 {
  363. status = "disabled";
  364. compatible = "amd,xgbe-seattle-v1a";
  365. reg = <0x0 0xe0700000 0x0 0x80000 0x0 0xe0780000 0x0 0x80000>;
  366. interrupts = <0x0 0x145 0x4>,
  367. <0x0 0x15a 0x1>,
  368. <0x0 0x15b 0x1>,
  369. <0x0 0x15c 0x1>,
  370. <0x0 0x15d 0x1>;
  371. amd,per-channel-interrupt;
  372. mac-address = [02 a1 a2 a3 a4 a5];
  373. clocks = <&xgmacclk0_dma &xgmacclk0_ptp>;
  374. clock-names = "dma_clk", "ptp_clk";
  375. phy-handle = <&xgmac0_phy>;
  376. phy-mode = "xgmii";
  377. dma-coherent;
  378. iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */
  379. };
  380. xgmac@e0900000 {
  381. status = "disabled";
  382. compatible = "amd,xgbe-seattle-v1a";
  383. reg = <0x0 0xe0900000 0x0 0x80000 0x0 0xe0980000 0x0 0x80000>;
  384. interrupts = <0x0 0x144 0x4>,
  385. <0x0 0x155 0x1>,
  386. <0x0 0x156 0x1>,
  387. <0x0 0x157 0x1>,
  388. <0x0 0x158 0x1>;
  389. amd,per-channel-interrupt;
  390. mac-address = [02 b1 b2 b3 b4 b5];
  391. clocks = <&xgmacclk1_dma &xgmacclk1_ptp>;
  392. clock-names = "dma_clk", "ptp_clk";
  393. phy-handle = <&xgmac1_phy>;
  394. phy-mode = "xgmii";
  395. dma-coherent;
  396. iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */
  397. };
  398. };
  399. chosen {
  400. stdout-path = "/smb/serial@e1010000";
  401. };
  402. psci {
  403. compatible = "arm,psci-0.2", "arm,psci";
  404. method = "smc";
  405. };
  406. };