PlatformPkg.fdf 40 KB

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  1. ## @file
  2. # FDF file of platform with 64-bit DXE
  3. # This package provides platform specific modules and flash layout information.
  4. #
  5. # @copyright
  6. # Copyright 2006 - 2021 Intel Corporation. <BR>
  7. #
  8. # SPDX-License-Identifier: BSD-2-Clause-Patent
  9. ##
  10. [Defines]
  11. DEFINE PLATFORM_PKG = MinPlatformPkg
  12. # 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
  13. DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060
  14. SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x90 # FV Header plus FFS header
  15. DEFINE VPD_HEADER_SIZE = 0x00000090
  16. !if $(FSP_MODE) == 0
  17. DEFINE FSP_BIN_DIR = Api
  18. !else
  19. DEFINE FSP_BIN_DIR = Dispatch
  20. !endif
  21. #
  22. # Note: FlashNv PCD naming conventions are as follows:
  23. # Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for
  24. # Others should be examined with an effort to work toward this guideline.
  25. # PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
  26. # PcdFlash*Size is a hex count of the length of the FD or FV
  27. # All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
  28. #
  29. # Also all values will have a PCD assigned so that they can be used in the system, and
  30. # the FlashMap edit tool can be used to change the values here, without effecting the code.
  31. # This requires all code to only use the PCD tokens to recover the values.
  32. #
  33. # 16MiB Total FLASH Image (visible in memory mapped IO)
  34. #
  35. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF000000
  36. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
  37. ################################################################################
  38. #
  39. # FD SECPEI
  40. #
  41. # Contains all the SEC and PEI modules
  42. #
  43. # Layout: (Low address to high address)
  44. #
  45. # FvBsp for board specific components
  46. # FvPostMemory for compressed post memory MinPlatform spec required components
  47. # FvFspS for compressed post memory silicon initialization components
  48. # FvPostMemorySilicon for silicon components
  49. # FvFspM for pre memory silicon initialization components
  50. # FvPreMemorySilicon for silicon components
  51. # FvFspT for temp RAM silicon initilization components
  52. # FvBspPreMemory for board specific components required to intialize memory
  53. # FvAdvancedPreMemory FV for advanced features components
  54. # FvPreMemory for components required by MinPlatform spec and to initialize memory
  55. # FvPreMemorySecurity FV for stage 6 required components
  56. # Contains reset vector
  57. #
  58. ################################################################################
  59. [FD.SecPei]
  60. BaseAddress = 0xFFCA0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase #The base address of the FLASH Device
  61. Size = 0x00360000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize #The size in bytes of the FLASH Device
  62. ErasePolarity = 1
  63. BlockSize = 0x1000
  64. NumBlocks = 0x360
  65. #
  66. # These must add up to the FD Size.
  67. # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
  68. # At this time, the FSP FV must be aligned at the same address they were built to, 0xFFD00000
  69. # This will be corrected in the future.
  70. #
  71. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
  72. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
  73. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00040000 # Size must match WhitleyFspPkg.fdf content
  74. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x00221000 # Size must match WhitleyFspPkg.fdf content
  75. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00006000 # Size must match WhitleyFspPkg.fdf content
  76. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize = 0x00010000
  77. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
  78. #
  79. # Calculate Offsets Once (Do not modify)
  80. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  81. # Each offset is the prior region's offset plus the prior region's size.
  82. #
  83. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset = 0x00000000
  84. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
  85. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  86. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  87. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  88. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  89. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
  90. #
  91. # FV Layout (Do not modify)
  92. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  93. #
  94. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
  95. FV = FvBsp
  96. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  97. FV = FvPostMemory
  98. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  99. FILE = $(FSP_BIN_PKG)/Fsp_Rebased_S.fd
  100. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  101. FILE = $(FSP_BIN_PKG)/Fsp_Rebased_M.fd
  102. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  103. FILE = $(FSP_BIN_PKG)/Fsp_Rebased_T.fd
  104. #
  105. # Shared FV layout
  106. #
  107. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
  108. FV = FvBspPreMemory
  109. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  110. FV = FvPreMemory
  111. #
  112. # Calculate base addresses (Do not modify)
  113. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  114. # Each base is the prior region's base plus the prior region's size.
  115. #
  116. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset
  117. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
  118. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  119. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  120. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  121. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  122. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
  123. #
  124. # Set duplicate PCD
  125. # These should not need to be changed
  126. #
  127. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
  128. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  129. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
  130. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  131. #
  132. # For API mode, wrappers have some duplicate PCD as well
  133. #
  134. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
  135. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
  136. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
  137. ################################################################################
  138. #
  139. # FD Main
  140. #
  141. # All DXE modules and other regions
  142. #
  143. # Layout: (Low address to high address)
  144. #
  145. # FvAdvanced for advanced feature components
  146. # Assorted advanced feature FV
  147. # FvSecurity for MinPlatform spec required components needed to boot securely
  148. # FvOsBoot for MinPlatform spec required components needed to boot OS
  149. # FvLateSilicon for silicon specific components
  150. # FvUefiBoot for MinPlatform spec required components needed to boot to UEFI shell
  151. #
  152. ################################################################################
  153. [FD.Main]
  154. BaseAddress = 0xFF2E0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase # The base address of the FLASH Device
  155. Size = 0x009C0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize # The size in bytes of the FLASH Device
  156. ErasePolarity = 1
  157. BlockSize = 0x1000
  158. NumBlocks = 0x9C0
  159. #
  160. # These must add up to the FD Size.
  161. # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
  162. # These are out of flash layout order because FvAdvanced gets any remaining space
  163. #
  164. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00010000
  165. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00230000
  166. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x0004C000
  167. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  168. #
  169. # Calculate Offsets Once (Do not modify)
  170. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  171. # Each offset is the prior region's offset plus the prior region's size.
  172. #
  173. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00000000
  174. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  175. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  176. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  177. #
  178. # FV Layout (Do not modify)
  179. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  180. #
  181. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  182. FV = FvAdvanced
  183. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  184. FV = FvSecurity
  185. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  186. FV = FvOsBoot
  187. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  188. FV = FvUefiBoot
  189. #
  190. # Calculate base addresses (Do not modify)
  191. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  192. # Each base is the prior region's base plus the prior region's size.
  193. #
  194. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset
  195. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  196. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  197. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  198. ################################################################################
  199. #
  200. # FD BINARY
  201. #
  202. # Contains the OPROM and other binary modules
  203. #
  204. # Layout: (Low address to high address)
  205. #
  206. # FvOpRom containing pre-built components
  207. # FvAcmRegion containing ACM related content
  208. # FV Header + Blank Space (1K)
  209. # Policy block (3K)
  210. # Blank space to align ACM on 64K boundary (60K)
  211. # ACM binary
  212. # FvMicrocode containing microcode update patches
  213. # Unformatted region for PCI Gen 3 Data
  214. # FvVpd containing PCD VPD data
  215. # FvWhea for WHEA data recording
  216. # FvNvStorageVariable for UEFI Variable storage
  217. # FvNvStorageEventLog for NV Store management
  218. # FvNvStorageFtwWorking for Fault Tolerant Write solution
  219. # FvNvStorageFtwSpare for Fault Tolerant Write solution
  220. #
  221. ################################################################################
  222. [FD.Binary]
  223. BaseAddress = 0xFF000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase
  224. Size = 0x002E0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize
  225. ErasePolarity = 1
  226. BlockSize = 0x1000
  227. NumBlocks = 0x2E0
  228. #
  229. # These must add up to the FD Size.
  230. # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
  231. #
  232. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize = 0x00100000
  233. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize = 0x00050000
  234. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = 0x000D0000
  235. SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize = 0x00010000
  236. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize = 0x00030000
  237. #
  238. # These four items are tightly coupled.
  239. # The spare area size must be >= the first three areas.
  240. #
  241. # There isn't really a benefit to a larger spare area unless the FLASH device
  242. # block size is larger than the size specified.
  243. #
  244. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0003C000
  245. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize = 0x00002000
  246. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000
  247. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  248. #
  249. # Calculate Offsets Once (You should not need to modify this section)
  250. # Each offset is the prior region's offset plus the prior region's size.
  251. #
  252. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset = 0x00000000
  253. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
  254. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
  255. SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
  256. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
  257. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
  258. SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  259. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
  260. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  261. #
  262. # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically
  263. #
  264. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
  265. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize - gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
  266. #
  267. # FV Layout (You should not need to modify this section)
  268. #
  269. gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
  270. FV = FvOprom
  271. gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
  272. FV = FvAcm
  273. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
  274. FV = FvMicrocode
  275. gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
  276. FV = FvVPD
  277. gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
  278. FV = FvWhea
  279. #
  280. # Do not modify.
  281. # See comments in size discussion above. These four areas are tightly coupled and should be modified with utmost care.
  282. #
  283. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  284. !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf
  285. gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
  286. DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
  287. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  288. !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf
  289. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  290. DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
  291. #
  292. # Calculate base addresses (You should not need to modify this section)
  293. # Each base is the prior region's base plus the prior region's size.
  294. #
  295. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset
  296. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
  297. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
  298. SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE)
  299. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE)
  300. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
  301. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  302. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
  303. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  304. #
  305. # ACM details
  306. #
  307. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000
  308. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize = 0x3000
  309. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000
  310. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize = 0x00040000
  311. #
  312. # Other duplicate PCD
  313. #
  314. SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
  315. SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
  316. SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
  317. SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
  318. ################################################################################
  319. #
  320. # FD FPGA
  321. #
  322. # Contains the FPGA modules
  323. #
  324. ################################################################################
  325. [FD.Fpga]
  326. BaseAddress = 0xFD000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase #The base address of the FPGA Device ( 4G - 48M )
  327. Size = 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize #The size in bytes of the FPGA Device ( 32M )
  328. ErasePolarity = 1
  329. BlockSize = 0x1000
  330. NumBlocks = 0x2000
  331. 0x00000000|0x02000000
  332. gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize
  333. FV = FvFpga
  334. ################################################################################
  335. #
  336. # FV Section
  337. #
  338. # [FV] section is used to define what components or modules are placed within a flash
  339. # device file. This section also defines order the components and modules are positioned
  340. # within the image. The [FV] section consists of define statements, set statements and
  341. # module statements.
  342. #
  343. ################################################################################
  344. [FV.FvSecurityPreMemory]
  345. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  346. FvNameGuid = 40ab290f-8494-41cf-b302-31b178b4ce0b
  347. [FV.FvPreMemory]
  348. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  349. FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
  350. INF UefiCpuPkg/SecCore/SecCore.inf
  351. INF MdeModulePkg/Core/Pei/PeiMain.inf
  352. INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
  353. INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
  354. INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
  355. INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf
  356. INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
  357. INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
  358. INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf
  359. INF WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
  360. FILE PEIM = ac4b7f1b-e057-47d3-b2b5-1137493c0f38 {
  361. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex
  362. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi
  363. SECTION UI = "DynamicSiLibraryPei"
  364. }
  365. INF WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
  366. INF WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
  367. INF WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf
  368. #
  369. # UBA common and board specific components
  370. #
  371. !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf
  372. INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
  373. INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
  374. FILE PEIM = ca8efb69-d7dc-4e94-aad6-9fb373649161 {
  375. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex
  376. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi
  377. SECTION UI = "SiliconPolicyInitPreAndPostMem"
  378. }
  379. INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
  380. !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePreMemory.fdf
  381. INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
  382. INF RuleOverride = LzmaCompress UefiCpuPkg/CpuMpPei/CpuMpPei.inf
  383. !if $(FSP_MODE) == 0
  384. FILE PEIM = 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 {
  385. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex
  386. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi
  387. SECTION UI = "CsrPseudoOffsetInitPeim"
  388. }
  389. FILE PEIM = 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 {
  390. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex
  391. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi
  392. SECTION UI = "RegAccessPeim"
  393. }
  394. FILE PEIM = C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F {
  395. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex
  396. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi
  397. SECTION UI = "SiliconDataInitPeim"
  398. }
  399. INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
  400. INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
  401. INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
  402. INF WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
  403. !endif
  404. FILE FV_IMAGE = 40ab290f-8494-41cf-b302-31b178b4ce0b {
  405. SECTION FV_IMAGE = FvSecurityPreMemory
  406. }
  407. [FV.FvAdvancedPreMemory]
  408. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  409. FvNameGuid = 09f25d44-b2ef-4225-8b2e-e0e094b51775
  410. !include AdvancedFeaturePkg/Include/PreMemory.fdf
  411. [FV.FvBspPreMemory]
  412. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  413. FvNameGuid = e6c65995-8c2d-4119-a52d-7dbf1acb45a1
  414. FILE FV_IMAGE = 09f25d44-b2ef-4225-8b2e-e0e094b51775 {
  415. SECTION FV_IMAGE = FvAdvancedPreMemory
  416. }
  417. #
  418. # FvPostMemory includes common hardware, common core variable services, load and invoke DXE etc
  419. #
  420. [FV.FvPostMemoryUncompressed]
  421. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  422. FvNameGuid = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA
  423. [FV.FvPostMemory]
  424. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  425. FvNameGuid = 3298afc4-c484-47f1-a65a-5917a54b5e8c
  426. FILE FV_IMAGE = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA {
  427. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  428. SECTION FV_IMAGE = FvPostMemoryUncompressed
  429. }
  430. }
  431. #
  432. # FvBsp includes board specific components
  433. #
  434. [FV.FvBspUncompressed]
  435. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  436. FvNameGuid = e4c65347-fd90-4143-8a41-113e1015fe07
  437. [FV.FvBsp]
  438. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  439. FvNameGuid = 9e151cf3-ca90-444f-b33b-a9941cbc772f
  440. FILE FV_IMAGE = e4c65347-fd90-4143-8a41-113e1015fe07 {
  441. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  442. SECTION FV_IMAGE = FvBspUncompressed
  443. }
  444. }
  445. [FV.FvUefiBootUncompressed]
  446. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  447. FvNameGuid = C4D3B0E2-FB26-44f8-A05B-E95895FCB960
  448. INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
  449. INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
  450. INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
  451. INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
  452. INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
  453. INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
  454. INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
  455. INF MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf
  456. INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
  457. INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
  458. INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
  459. INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
  460. INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
  461. INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
  462. INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
  463. INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
  464. INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
  465. INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf
  466. #ATA for IDE/AHCI/RAID support
  467. INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
  468. INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
  469. INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
  470. INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
  471. [FV.FvUefiBoot]
  472. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  473. FvNameGuid = ab9fe87b-1e37-440c-91cc-9aea03ce7bec
  474. FILE FV_IMAGE = C4D3B0E2-FB26-44f8-A05B-E95895FCB960 {
  475. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  476. SECTION FV_IMAGE = FvUefiBootUncompressed
  477. }
  478. }
  479. [FV.FvOsBootUncompressed]
  480. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  481. FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0
  482. #
  483. # DXE Phase modules
  484. #
  485. INF MdeModulePkg/Core/Dxe/DxeMain.inf
  486. INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
  487. INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
  488. INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
  489. FILE FV_IMAGE = B7C9F0CB-15D8-26FC-CA3F-C63947B12831 {
  490. SECTION UI = "FvLateSilicon"
  491. SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateSilicon.fv
  492. }
  493. INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
  494. !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePostMemory.fdf
  495. #
  496. # UBA DXE common and board specific components
  497. #
  498. !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf
  499. !include WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
  500. INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf
  501. INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
  502. !if ($(FSP_MODE) == 1)
  503. INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf
  504. !else
  505. INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
  506. !endif
  507. INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
  508. INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
  509. INF WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
  510. INF UefiCpuPkg/CpuDxe/CpuDxe.inf
  511. INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
  512. FILE FV_IMAGE = a0277d07-a725-4823-90f9-6cba00782111 {
  513. SECTION UI = "FvLateOpenBoard"
  514. SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateOpenBoard.fv
  515. }
  516. INF MdeModulePkg/Universal/Metronome/Metronome.inf
  517. INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
  518. INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
  519. INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
  520. INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
  521. INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
  522. INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
  523. INF RuleOverride = UI MdeModulePkg/Application/UiApp/UiApp.inf
  524. INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
  525. INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
  526. #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV.
  527. INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
  528. INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
  529. INF FatPkg/EnhancedFatDxe/Fat.inf
  530. INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
  531. INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
  532. INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
  533. INF ShellPkg/Application/Shell/Shell.inf
  534. INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
  535. INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
  536. INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
  537. INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
  538. INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
  539. INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
  540. INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
  541. INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
  542. INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
  543. INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
  544. INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
  545. INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
  546. INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf
  547. INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
  548. INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
  549. # UEFI USB stack
  550. INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
  551. INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
  552. INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
  553. INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
  554. !if $(CPUTARGET) == "ICX"
  555. INF RuleOverride = ACPITABLE WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf
  556. INF WhitleyOpenBoardPkg/Features/Acpi/AcpiPlatform/AcpiPlatform.inf
  557. !endif
  558. INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf
  559. INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
  560. [FV.FvOsBoot]
  561. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  562. FvNameGuid = c7488640-5f51-4969-b63b-89fc369e1725
  563. FILE FV_IMAGE = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 {
  564. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  565. SECTION FV_IMAGE = FvOsBootUncompressed
  566. }
  567. }
  568. [FV.FvSecuritySilicon]
  569. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  570. FvNameGuid = AD262F8D-BDED-4668-A8D4-8BC73516652F
  571. [FV.FvSecurityUncompressed]
  572. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  573. FvNameGuid = 03E25550-89A5-4ee6-AF60-DB0553D91FD2
  574. FILE FV_IMAGE = 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 {
  575. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  576. SECTION FV_IMAGE = FvSecuritySilicon
  577. }
  578. }
  579. [FV.FvSecurity]
  580. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  581. FvNameGuid = 68134833-2ff6-4d22-973b-575d0eae8ffd
  582. FILE FV_IMAGE = 03E25550-89A5-4ee6-AF60-DB0553D91FD2 {
  583. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  584. SECTION FV_IMAGE = FvSecurityUncompressed
  585. }
  586. }
  587. [FV.FvAdvancedUncompressed]
  588. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  589. FvNameGuid = 70aeaf57-4997-49ce-a4f7-122980745670
  590. !include AdvancedFeaturePkg/Include/PostMemory.fdf
  591. [FV.FvAdvanced]
  592. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  593. FvNameGuid = f21ee7a1-53a9-453d-aee3-b6a5c25bada5
  594. FILE FV_IMAGE = 70aeaf57-4997-49ce-a4f7-122980745670 {
  595. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  596. SECTION FV_IMAGE = FvAdvancedUncompressed
  597. }
  598. }
  599. #
  600. # FV for all Microcode Updates.
  601. #
  602. [FV.FvMicrocode]
  603. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  604. LOCK_STATUS = FALSE
  605. FvNameGuid = D2C29BA7-3809-480F-9C3D-DE389C61425A
  606. !if $(CPUTARGET) == "CPX"
  607. INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
  608. !else
  609. INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
  610. !endif
  611. [FV.FvVPD]
  612. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  613. LOCK_STATUS = FALSE
  614. FvNameGuid = FFC29BA7-3809-480F-9C3D-DE389C61425A
  615. FILE RAW = FF7DB236-F856-4924-90F8-CDF12FB875F3 {
  616. $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin
  617. }
  618. #
  619. # Various Vendor UEFI Drivers (OROMs).
  620. #
  621. [FV.FvOpromUncompressed]
  622. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  623. FvNameGuid = B6EDE22C-DE30-45fa-BB09-CA202C1654B7
  624. [FV.FvOprom]
  625. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  626. FvNameGuid = 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD
  627. FILE FV_IMAGE = B6EDE22C-DE30-45fa-BB09-CA202C1654B7 {
  628. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  629. SECTION FV_IMAGE = FvOpromUncompressed
  630. }
  631. }
  632. [FV.FvWhea]
  633. BlockSize = 0x1000
  634. NumBlocks = 0x30
  635. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  636. FvNameGuid = d6a1cd70-4b33-4994-a6ea-375f2ccc5437
  637. #
  638. # FV For ACM Binary.
  639. #
  640. [FV.FvAcm]
  641. BlockSize = 0x1000
  642. NumBlocks = 0x50
  643. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  644. FvNameGuid = 11668261-8A8D-47ca-9893-052D24435E59
  645. [FV.FvFpga]
  646. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  647. FvNameGuid = 974650E7-6DFE-4998-A124-CEDEC5C9B47D
  648. ################################################################################
  649. #
  650. # Rules are use with the [FV] section's module INF type to define
  651. # how an FFS file is created for a given INF file. The following Rule are the default
  652. # rules for the different module type. User can add the customized rules to define the
  653. # content of the FFS file.
  654. #
  655. ################################################################################
  656. !include MinPlatformPkg/Include/Fdf/RuleInclude.fdf
  657. [Rule.Common.USER_DEFINED.ACPITABLE]
  658. FILE FREEFORM = $(NAMED_GUID) {
  659. RAW ACPI Optional |.acpi
  660. RAW ASL Optional |.aml
  661. }
  662. [Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE]
  663. FILE DRIVER = $(NAMED_GUID) {
  664. DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
  665. PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
  666. RAW ACPI Optional |.acpi
  667. RAW ASL Optional |.aml
  668. UI STRING="$(MODULE_NAME)" Optional
  669. VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
  670. }