PlatformPkg.fdf 41 KB

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  1. ## @file
  2. # FDF file of platform with 64-bit DXE
  3. # This package provides platform specific modules and flash layout information.
  4. #
  5. # @copyright
  6. # Copyright 2006 - 2021 Intel Corporation. <BR>
  7. # Copyright (c) 2021, American Megatrends International LLC. <BR>
  8. #
  9. # SPDX-License-Identifier: BSD-2-Clause-Patent
  10. ##
  11. [Defines]
  12. DEFINE PLATFORM_PKG = MinPlatformPkg
  13. # 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
  14. DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060
  15. SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x90 # FV Header plus FFS header
  16. DEFINE VPD_HEADER_SIZE = 0x00000090
  17. !if $(FSP_MODE) == 0
  18. DEFINE FSP_BIN_DIR = Api
  19. !else
  20. DEFINE FSP_BIN_DIR = Dispatch
  21. !endif
  22. #
  23. # Note: FlashNv PCD naming conventions are as follows:
  24. # Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for
  25. # Others should be examined with an effort to work toward this guideline.
  26. # PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
  27. # PcdFlash*Size is a hex count of the length of the FD or FV
  28. # All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
  29. #
  30. # Also all values will have a PCD assigned so that they can be used in the system, and
  31. # the FlashMap edit tool can be used to change the values here, without effecting the code.
  32. # This requires all code to only use the PCD tokens to recover the values.
  33. #
  34. # 16MiB Total FLASH Image (visible in memory mapped IO)
  35. #
  36. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF000000
  37. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
  38. ################################################################################
  39. #
  40. # FD SECPEI
  41. #
  42. # Contains all the SEC and PEI modules
  43. #
  44. # Layout: (Low address to high address)
  45. #
  46. # FvBsp for board specific components
  47. # FvPostMemory for compressed post memory MinPlatform spec required components
  48. # FvFspS for compressed post memory silicon initialization components
  49. # FvPostMemorySilicon for silicon components
  50. # FvFspM for pre memory silicon initialization components
  51. # FvPreMemorySilicon for silicon components
  52. # FvFspT for temp RAM silicon initilization components
  53. # FvBspPreMemory for board specific components required to intialize memory
  54. # FvAdvancedPreMemory FV for advanced features components
  55. # FvPreMemory for components required by MinPlatform spec and to initialize memory
  56. # FvPreMemorySecurity FV for stage 6 required components
  57. # Contains reset vector
  58. #
  59. ################################################################################
  60. [FD.SecPei]
  61. BaseAddress = 0xFFCA0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase #The base address of the FLASH Device
  62. Size = 0x00360000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize #The size in bytes of the FLASH Device
  63. ErasePolarity = 1
  64. BlockSize = 0x1000
  65. NumBlocks = 0x360
  66. #
  67. # These must add up to the FD Size.
  68. # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
  69. # At this time, the FSP FV must be aligned at the same address they were built to, 0xFFD00000
  70. # This will be corrected in the future.
  71. #
  72. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
  73. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
  74. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00040000 # Size must match WhitleyFspPkg.fdf content
  75. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x00221000 # Size must match WhitleyFspPkg.fdf content
  76. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00006000 # Size must match WhitleyFspPkg.fdf content
  77. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize = 0x00009000
  78. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
  79. #
  80. # Calculate Offsets Once (Do not modify)
  81. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  82. # Each offset is the prior region's offset plus the prior region's size.
  83. #
  84. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset = 0x00000000
  85. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
  86. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  87. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  88. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  89. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  90. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
  91. #
  92. # FV Layout (Do not modify)
  93. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  94. #
  95. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
  96. FV = FvBsp
  97. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  98. FV = FvPostMemory
  99. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  100. FILE = $(FSP_BIN_PKG)/Fsp_Rebased_S.fd
  101. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  102. FILE = $(FSP_BIN_PKG)/Fsp_Rebased_M.fd
  103. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  104. FILE = $(FSP_BIN_PKG)/Fsp_Rebased_T.fd
  105. #
  106. # Shared FV layout
  107. #
  108. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
  109. FV = FvBspPreMemory
  110. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  111. FV = FvPreMemory
  112. #
  113. # Calculate base addresses (Do not modify)
  114. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  115. # Each base is the prior region's base plus the prior region's size.
  116. #
  117. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset
  118. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
  119. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  120. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  121. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  122. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  123. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
  124. #
  125. # Set duplicate PCD
  126. # These should not need to be changed
  127. #
  128. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
  129. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  130. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
  131. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  132. #
  133. # For API mode, wrappers have some duplicate PCD as well
  134. #
  135. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
  136. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
  137. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
  138. ################################################################################
  139. #
  140. # FD Main
  141. #
  142. # All DXE modules and other regions
  143. #
  144. # Layout: (Low address to high address)
  145. #
  146. # FvAdvanced for advanced feature components
  147. # Assorted advanced feature FV
  148. # FvSecurity for MinPlatform spec required components needed to boot securely
  149. # FvOsBoot for MinPlatform spec required components needed to boot OS
  150. # FvLateSilicon for silicon specific components
  151. # FvUefiBoot for MinPlatform spec required components needed to boot to UEFI shell
  152. #
  153. ################################################################################
  154. [FD.Main]
  155. BaseAddress = 0xFF2E0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase # The base address of the FLASH Device
  156. Size = 0x009C0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize # The size in bytes of the FLASH Device
  157. ErasePolarity = 1
  158. BlockSize = 0x1000
  159. NumBlocks = 0x9C0
  160. #
  161. # These must add up to the FD Size.
  162. # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
  163. # These are out of flash layout order because FvAdvanced gets any remaining space
  164. #
  165. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00040000
  166. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00230000
  167. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x0004C000
  168. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  169. #
  170. # Calculate Offsets Once (Do not modify)
  171. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  172. # Each offset is the prior region's offset plus the prior region's size.
  173. #
  174. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00000000
  175. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  176. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  177. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  178. #
  179. # FV Layout (Do not modify)
  180. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  181. #
  182. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  183. FV = FvAdvanced
  184. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  185. FV = FvSecurity
  186. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  187. FV = FvOsBoot
  188. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  189. FV = FvUefiBoot
  190. #
  191. # Calculate base addresses (Do not modify)
  192. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  193. # Each base is the prior region's base plus the prior region's size.
  194. #
  195. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset
  196. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  197. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  198. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  199. ################################################################################
  200. #
  201. # FD BINARY
  202. #
  203. # Contains the OPROM and other binary modules
  204. #
  205. # Layout: (Low address to high address)
  206. #
  207. # FvOpRom containing pre-built components
  208. # FvAcmRegion containing ACM related content
  209. # FV Header + Blank Space (1K)
  210. # Policy block (3K)
  211. # Blank space to align ACM on 64K boundary (60K)
  212. # ACM binary
  213. # FvMicrocode containing microcode update patches
  214. # Unformatted region for PCI Gen 3 Data
  215. # FvVpd containing PCD VPD data
  216. # FvWhea for WHEA data recording
  217. # FvNvStorageVariable for UEFI Variable storage
  218. # FvNvStorageEventLog for NV Store management
  219. # FvNvStorageFtwWorking for Fault Tolerant Write solution
  220. # FvNvStorageFtwSpare for Fault Tolerant Write solution
  221. #
  222. ################################################################################
  223. [FD.Binary]
  224. BaseAddress = 0xFF000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase
  225. Size = 0x002E0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize
  226. ErasePolarity = 1
  227. BlockSize = 0x1000
  228. NumBlocks = 0x2E0
  229. #
  230. # These must add up to the FD Size.
  231. # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
  232. #
  233. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize = 0x00100000
  234. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize = 0x00050000
  235. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = 0x000D0000
  236. SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize = 0x00010000
  237. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize = 0x00030000
  238. #
  239. # These four items are tightly coupled.
  240. # The spare area size must be >= the first three areas.
  241. #
  242. # There isn't really a benefit to a larger spare area unless the FLASH device
  243. # block size is larger than the size specified.
  244. #
  245. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0003C000
  246. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize = 0x00002000
  247. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000
  248. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  249. #
  250. # Calculate Offsets Once (You should not need to modify this section)
  251. # Each offset is the prior region's offset plus the prior region's size.
  252. #
  253. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset = 0x00000000
  254. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
  255. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
  256. SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
  257. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
  258. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
  259. SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  260. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
  261. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  262. #
  263. # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically
  264. #
  265. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
  266. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize - gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
  267. #
  268. # FV Layout (You should not need to modify this section)
  269. #
  270. gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
  271. FV = FvOprom
  272. gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
  273. FV = FvAcm
  274. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
  275. FV = FvMicrocode
  276. gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
  277. FV = FvVPD
  278. gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
  279. FV = FvWhea
  280. #
  281. # Do not modify.
  282. # See comments in size discussion above. These four areas are tightly coupled and should be modified with utmost care.
  283. #
  284. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  285. !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf
  286. gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
  287. DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
  288. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  289. !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf
  290. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  291. DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
  292. #
  293. # Calculate base addresses (You should not need to modify this section)
  294. # Each base is the prior region's base plus the prior region's size.
  295. #
  296. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset
  297. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
  298. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
  299. SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE)
  300. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE)
  301. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
  302. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  303. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
  304. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  305. #
  306. # ACM details
  307. #
  308. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000
  309. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize = 0x3000
  310. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000
  311. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize = 0x00040000
  312. #
  313. # Other duplicate PCD
  314. #
  315. SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
  316. SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
  317. SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
  318. SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
  319. ################################################################################
  320. #
  321. # FD FPGA
  322. #
  323. # Contains the FPGA modules
  324. #
  325. ################################################################################
  326. [FD.Fpga]
  327. BaseAddress = 0xFD000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase #The base address of the FPGA Device ( 4G - 48M )
  328. Size = 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize #The size in bytes of the FPGA Device ( 32M )
  329. ErasePolarity = 1
  330. BlockSize = 0x1000
  331. NumBlocks = 0x2000
  332. 0x00000000|0x02000000
  333. gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize
  334. FV = FvFpga
  335. ################################################################################
  336. #
  337. # FV Section
  338. #
  339. # [FV] section is used to define what components or modules are placed within a flash
  340. # device file. This section also defines order the components and modules are positioned
  341. # within the image. The [FV] section consists of define statements, set statements and
  342. # module statements.
  343. #
  344. ################################################################################
  345. [FV.FvSecurityPreMemory]
  346. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  347. FvNameGuid = 40ab290f-8494-41cf-b302-31b178b4ce0b
  348. !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
  349. [FV.FvPreMemory]
  350. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  351. FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
  352. INF UefiCpuPkg/SecCore/SecCore.inf
  353. INF MdeModulePkg/Core/Pei/PeiMain.inf
  354. INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
  355. INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
  356. INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
  357. INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf
  358. INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
  359. INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
  360. INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf
  361. INF WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
  362. FILE PEIM = ac4b7f1b-e057-47d3-b2b5-1137493c0f38 {
  363. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex
  364. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi
  365. SECTION UI = "DynamicSiLibraryPei"
  366. }
  367. INF WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
  368. INF WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
  369. INF WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf
  370. #
  371. # UBA common and board specific components
  372. #
  373. !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf
  374. INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
  375. INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
  376. FILE PEIM = ca8efb69-d7dc-4e94-aad6-9fb373649161 {
  377. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex
  378. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi
  379. SECTION UI = "SiliconPolicyInitPreAndPostMem"
  380. }
  381. INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
  382. !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePreMemory.fdf
  383. INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
  384. INF RuleOverride = LzmaCompress UefiCpuPkg/CpuMpPei/CpuMpPei.inf
  385. !if $(FSP_MODE) == 0
  386. FILE PEIM = 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 {
  387. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex
  388. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi
  389. SECTION UI = "CsrPseudoOffsetInitPeim"
  390. }
  391. FILE PEIM = 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 {
  392. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex
  393. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi
  394. SECTION UI = "RegAccessPeim"
  395. }
  396. FILE PEIM = C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F {
  397. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex
  398. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi
  399. SECTION UI = "SiliconDataInitPeim"
  400. }
  401. INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
  402. INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
  403. INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
  404. INF WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
  405. !endif
  406. FILE FV_IMAGE = 40ab290f-8494-41cf-b302-31b178b4ce0b {
  407. SECTION FV_IMAGE = FvSecurityPreMemory
  408. }
  409. [FV.FvAdvancedPreMemory]
  410. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  411. FvNameGuid = 09f25d44-b2ef-4225-8b2e-e0e094b51775
  412. !include AdvancedFeaturePkg/Include/PreMemory.fdf
  413. [FV.FvBspPreMemory]
  414. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  415. FvNameGuid = e6c65995-8c2d-4119-a52d-7dbf1acb45a1
  416. FILE FV_IMAGE = 09f25d44-b2ef-4225-8b2e-e0e094b51775 {
  417. SECTION FV_IMAGE = FvAdvancedPreMemory
  418. }
  419. #
  420. # FvPostMemory includes common hardware, common core variable services, load and invoke DXE etc
  421. #
  422. [FV.FvPostMemoryUncompressed]
  423. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  424. FvNameGuid = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA
  425. [FV.FvPostMemory]
  426. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  427. FvNameGuid = 3298afc4-c484-47f1-a65a-5917a54b5e8c
  428. FILE FV_IMAGE = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA {
  429. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  430. SECTION FV_IMAGE = FvPostMemoryUncompressed
  431. }
  432. }
  433. #
  434. # FvBsp includes board specific components
  435. #
  436. [FV.FvBspUncompressed]
  437. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  438. FvNameGuid = e4c65347-fd90-4143-8a41-113e1015fe07
  439. [FV.FvBsp]
  440. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  441. FvNameGuid = 9e151cf3-ca90-444f-b33b-a9941cbc772f
  442. FILE FV_IMAGE = e4c65347-fd90-4143-8a41-113e1015fe07 {
  443. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  444. SECTION FV_IMAGE = FvBspUncompressed
  445. }
  446. }
  447. [FV.FvUefiBootUncompressed]
  448. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  449. FvNameGuid = C4D3B0E2-FB26-44f8-A05B-E95895FCB960
  450. INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
  451. INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
  452. INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
  453. INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
  454. INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
  455. INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
  456. INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
  457. INF MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf
  458. INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
  459. INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
  460. INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
  461. INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
  462. INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
  463. INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
  464. INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
  465. INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
  466. INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
  467. INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf
  468. #ATA for IDE/AHCI/RAID support
  469. INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
  470. INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
  471. INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
  472. INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
  473. INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
  474. FILE DRIVER = 85299F8F-F2B9-4487-AF60-231434A5EFF6 {
  475. SECTION PE32 = edk2-non-osi/Drivers/ASpeed/ASpeedGopBinPkg/X64/ASpeedAst2500Gop.efi
  476. }
  477. [FV.FvUefiBoot]
  478. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  479. FvNameGuid = ab9fe87b-1e37-440c-91cc-9aea03ce7bec
  480. FILE FV_IMAGE = C4D3B0E2-FB26-44f8-A05B-E95895FCB960 {
  481. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  482. SECTION FV_IMAGE = FvUefiBootUncompressed
  483. }
  484. }
  485. [FV.FvOsBootUncompressed]
  486. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  487. FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0
  488. #
  489. # DXE Phase modules
  490. #
  491. INF MdeModulePkg/Core/Dxe/DxeMain.inf
  492. INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
  493. INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
  494. INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
  495. FILE FV_IMAGE = B7C9F0CB-15D8-26FC-CA3F-C63947B12831 {
  496. SECTION UI = "FvLateSilicon"
  497. SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateSilicon.fv
  498. }
  499. INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
  500. !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePostMemory.fdf
  501. #
  502. # UBA DXE common and board specific components
  503. #
  504. !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf
  505. INF $(RP_PKG)/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf
  506. INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
  507. INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
  508. INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
  509. INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf
  510. INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
  511. !if ($(FSP_MODE) == 1)
  512. INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf
  513. !else
  514. INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
  515. !endif
  516. INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
  517. INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
  518. INF WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
  519. INF UefiCpuPkg/CpuDxe/CpuDxe.inf
  520. INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
  521. FILE FV_IMAGE = a0277d07-a725-4823-90f9-6cba00782111 {
  522. SECTION UI = "FvLateOpenBoard"
  523. SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateOpenBoard.fv
  524. }
  525. INF MdeModulePkg/Universal/Metronome/Metronome.inf
  526. INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
  527. INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
  528. INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
  529. INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
  530. INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
  531. INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
  532. INF RuleOverride = UI MdeModulePkg/Application/UiApp/UiApp.inf
  533. INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
  534. INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
  535. #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV.
  536. INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
  537. INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
  538. INF FatPkg/EnhancedFatDxe/Fat.inf
  539. INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
  540. INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
  541. INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
  542. INF ShellPkg/Application/Shell/Shell.inf
  543. INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
  544. INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
  545. INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
  546. INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
  547. INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
  548. INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
  549. INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
  550. INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
  551. INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
  552. INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
  553. INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
  554. INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
  555. INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf
  556. INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
  557. INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
  558. # UEFI USB stack
  559. INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
  560. INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
  561. INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
  562. INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
  563. INF RuleOverride = ACPITABLE WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf
  564. INF WhitleyOpenBoardPkg/Features/Acpi/AcpiPlatform/AcpiPlatform.inf
  565. INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf
  566. INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
  567. [FV.FvOsBoot]
  568. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  569. FvNameGuid = c7488640-5f51-4969-b63b-89fc369e1725
  570. FILE FV_IMAGE = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 {
  571. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  572. SECTION FV_IMAGE = FvOsBootUncompressed
  573. }
  574. }
  575. [FV.FvSecuritySilicon]
  576. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  577. FvNameGuid = AD262F8D-BDED-4668-A8D4-8BC73516652F
  578. !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf
  579. [FV.FvSecurityUncompressed]
  580. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  581. FvNameGuid = 03E25550-89A5-4ee6-AF60-DB0553D91FD2
  582. FILE FV_IMAGE = 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 {
  583. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  584. SECTION FV_IMAGE = FvSecuritySilicon
  585. }
  586. }
  587. [FV.FvSecurity]
  588. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  589. FvNameGuid = 68134833-2ff6-4d22-973b-575d0eae8ffd
  590. FILE FV_IMAGE = 03E25550-89A5-4ee6-AF60-DB0553D91FD2 {
  591. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  592. SECTION FV_IMAGE = FvSecurityUncompressed
  593. }
  594. }
  595. [FV.FvAdvancedUncompressed]
  596. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  597. FvNameGuid = 70aeaf57-4997-49ce-a4f7-122980745670
  598. !include AdvancedFeaturePkg/Include/PostMemory.fdf
  599. [FV.FvAdvanced]
  600. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  601. FvNameGuid = f21ee7a1-53a9-453d-aee3-b6a5c25bada5
  602. FILE FV_IMAGE = 70aeaf57-4997-49ce-a4f7-122980745670 {
  603. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  604. SECTION FV_IMAGE = FvAdvancedUncompressed
  605. }
  606. }
  607. #
  608. # FV for all Microcode Updates.
  609. #
  610. [FV.FvMicrocode]
  611. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  612. LOCK_STATUS = FALSE
  613. FvNameGuid = D2C29BA7-3809-480F-9C3D-DE389C61425A
  614. !if $(CPUTARGET) == "CPX"
  615. INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
  616. !else
  617. INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
  618. !endif
  619. [FV.FvVPD]
  620. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  621. LOCK_STATUS = FALSE
  622. FvNameGuid = FFC29BA7-3809-480F-9C3D-DE389C61425A
  623. FILE RAW = FF7DB236-F856-4924-90F8-CDF12FB875F3 {
  624. $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin
  625. }
  626. #
  627. # Various Vendor UEFI Drivers (OROMs).
  628. #
  629. [FV.FvOpromUncompressed]
  630. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  631. FvNameGuid = B6EDE22C-DE30-45fa-BB09-CA202C1654B7
  632. [FV.FvOprom]
  633. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  634. FvNameGuid = 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD
  635. FILE FV_IMAGE = B6EDE22C-DE30-45fa-BB09-CA202C1654B7 {
  636. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  637. SECTION FV_IMAGE = FvOpromUncompressed
  638. }
  639. }
  640. [FV.FvWhea]
  641. BlockSize = 0x1000
  642. NumBlocks = 0x30
  643. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  644. FvNameGuid = d6a1cd70-4b33-4994-a6ea-375f2ccc5437
  645. #
  646. # FV For ACM Binary.
  647. #
  648. [FV.FvAcm]
  649. BlockSize = 0x1000
  650. NumBlocks = 0x50
  651. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  652. FvNameGuid = 11668261-8A8D-47ca-9893-052D24435E59
  653. [FV.FvFpga]
  654. !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  655. FvNameGuid = 974650E7-6DFE-4998-A124-CEDEC5C9B47D
  656. ################################################################################
  657. #
  658. # Rules are use with the [FV] section's module INF type to define
  659. # how an FFS file is created for a given INF file. The following Rule are the default
  660. # rules for the different module type. User can add the customized rules to define the
  661. # content of the FFS file.
  662. #
  663. ################################################################################
  664. !include MinPlatformPkg/Include/Fdf/RuleInclude.fdf
  665. [Rule.Common.USER_DEFINED.ACPITABLE]
  666. FILE FREEFORM = $(NAMED_GUID) {
  667. RAW ACPI Optional |.acpi
  668. RAW ASL Optional |.aml
  669. }
  670. [Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE]
  671. FILE DRIVER = $(NAMED_GUID) {
  672. DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
  673. PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
  674. RAW ACPI Optional |.acpi
  675. RAW ASL Optional |.aml
  676. UI STRING="$(MODULE_NAME)" Optional
  677. VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
  678. }