IioCfgUpdateDxe.h 6.0 KB

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  1. /** @file
  2. @copyright
  3. Copyright 2016 - 2021 Intel Corporation. <BR>
  4. Copyright (c) 2021, American Megatrends International LLC. <BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #ifndef _IIOCFG_UPDATE_DXE_H_
  8. #define _IIOCFG_UPDATE_DXE_H_
  9. #include <Base.h>
  10. #include <Uefi.h>
  11. #include <Protocol/UbaCfgDb.h>
  12. #include <Library/UefiDriverEntryPoint.h>
  13. #include <Library/UefiBootServicesTableLib.h>
  14. #include <Library/DebugLib.h>
  15. #include <Library/BaseLib.h>
  16. #include <Library/BaseMemoryLib.h>
  17. #include <Library/MemoryAllocationLib.h>
  18. #include <Library/PciLib.h>
  19. #include <Library/UbaIioConfigLib.h>
  20. #include <IioPlatformData.h>
  21. typedef enum {
  22. Iio_Socket0 = 0,
  23. Iio_Socket1,
  24. Iio_Socket2,
  25. Iio_Socket3,
  26. Iio_Socket4,
  27. Iio_Socket5,
  28. Iio_Socket6,
  29. Iio_Socket7
  30. } IIO_SOCKETS;
  31. typedef enum {
  32. Iio_Iou0 =0,
  33. Iio_Iou1,
  34. Iio_Iou2,
  35. Iio_Mcp0,
  36. Iio_Mcp1,
  37. Iio_IouMax
  38. } IIO_IOUS;
  39. typedef enum {
  40. VPP_PORT_0 = 0,
  41. VPP_PORT_1,
  42. VPP_PORT_2,
  43. VPP_PORT_3
  44. } VPP_PORT;
  45. #define ENABLE 1
  46. #define DISABLE 0
  47. #define NO_SLT_IMP 0xFF
  48. #define SLT_IMP 1
  49. #define HIDE 1
  50. #define NOT_HIDE 0
  51. #define VPP_PORT_0 0
  52. #define VPP_PORT_1 1
  53. #define VPP_PORT_MAX 0xFF
  54. #define VPP_ADDR_MAX 0xFF
  55. #define PWR_VAL_MAX 0xFF
  56. #define PWR_SCL_MAX 0xFF
  57. static IIO_BIFURCATION_DATA_ENTRY IioBifurcationTable[] =
  58. {
  59. // Neon City IIO bifurcation table (Based on Neon City Block Diagram rev 0.6)
  60. { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxx8x4x4 },
  61. { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
  62. { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 },
  63. { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
  64. { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
  65. { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 },
  66. { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
  67. { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 },
  68. { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
  69. { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
  70. };
  71. static IIO_SLOT_CONFIG_DATA_ENTRY IioSlotTable[] = {
  72. // Port | Slot | Inter | Power Limit | Power Limit | Hot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD | Hidden
  73. // Index | | lock | Scale | Value | Plug | Port | Addr | Cap | VppPort | VppAddr |
  74. { PORT_1A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4C , HIDE },//Oculink
  75. { PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x4C , HIDE },//Oculink
  76. { PORT_1C_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
  77. { PORT_2A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
  78. // Slot 2 supports HP: PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P 118 (MRL in J65)
  79. { PORT_3A_INDEX, 2 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE },
  80. { PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 , HIDE },
  81. { PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , HIDE },
  82. { PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 , HIDE },
  83. { SOCKET_1_INDEX +
  84. PORT_0_INDEX , 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
  85. // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 121 (MRL in J287)
  86. { SOCKET_1_INDEX +
  87. PORT_1A_INDEX, 4 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE },
  88. { SOCKET_1_INDEX +
  89. PORT_1B_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 , HIDE },
  90. { SOCKET_1_INDEX +
  91. PORT_1C_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , HIDE },
  92. { SOCKET_1_INDEX +
  93. PORT_1D_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 , HIDE },
  94. { SOCKET_1_INDEX +
  95. PORT_2A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_1 , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x44 , NOT_HIDE },
  96. { SOCKET_1_INDEX +
  97. PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x44 , HIDE },
  98. { SOCKET_1_INDEX +
  99. PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x46 , HIDE },
  100. { SOCKET_1_INDEX +
  101. PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x46 , HIDE },
  102. { SOCKET_1_INDEX +
  103. PORT_3A_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
  104. { SOCKET_1_INDEX +
  105. PORT_3C_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
  106. // Note: On Neon City, Slot 3 is assigned to PCH's PCIE port
  107. };
  108. #endif //_IIOCFG_UPDATE_DXE_H_