PchPolicyCommon.h 99 KB

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  1. /** @file
  2. PCH configuration based on PCH policy
  3. @copyright
  4. Copyright 2009 - 2021 Intel Corporation. <BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #ifndef _PCH_POLICY_COMMON_H_
  8. #define _PCH_POLICY_COMMON_H_
  9. #include "PchLimits.h"
  10. #include <ConfigBlock/UsbConfig.h>
  11. #include <ConfigBlock/Usb2PhyConfig.h>
  12. #include <ConfigBlock/TraceHubConfig.h>
  13. #define FLASH_PROTECTION_CONFIG_REVISION 1
  14. extern EFI_GUID gFlashProtectionConfigGuid;
  15. #pragma pack (push,1)
  16. //
  17. // ---------------------------- PCH General Config -------------------------------
  18. //
  19. /**
  20. PCH General Configuration
  21. **/
  22. typedef struct {
  23. /**
  24. Subsystem Vendor ID and Subsystem ID of the PCH devices.
  25. This fields will be ignored if the value of SubSystemVendorId and SubSystemId
  26. are both 0.
  27. **/
  28. UINT16 SubSystemVendorId; ///< Default Subsystem Vendor ID of the PCH devices. Default is <b>0x8086</b>
  29. UINT16 SubSystemId; ///< Default Subsystem ID of the PCH devices. Default is <b>0x7270</b>
  30. /**
  31. This member describes whether or not the Compatibility Revision ID (CRID) feature
  32. of PCH should be enabled. <b>0: Disable</b>; 1: Enable
  33. **/
  34. UINT32 Crid : 1;
  35. UINT32 EnableClockSpreadSpec : 1;
  36. UINT32 Serm : 1;
  37. UINT32 RsvdBits0 : 29; ///< Reserved bits
  38. UINT32 Rsvd0[2]; ///< Reserved bytes
  39. } PCH_GENERAL_CONFIG;
  40. #define FORCE_ENABLE 1
  41. #define FORCE_DISABLE 2
  42. #define PLATFORM_POR 0
  43. #define AUTO 0
  44. #define DCI_DISABLE 0
  45. //
  46. // ---------------------------- Reserved Page Config -----------------------------
  47. //
  48. enum PCH_RESERVED_PAGE_ROUTE {
  49. PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC.
  50. PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe.
  51. };
  52. //
  53. // ---------------------------- PCI Express Config ----------------------
  54. //
  55. enum PCH_PCIE_SPEED {
  56. PchPcieAuto,
  57. PchPcieGen1,
  58. PchPcieGen2,
  59. PchPcieGen3
  60. };
  61. ///
  62. /// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
  63. ///
  64. typedef enum {
  65. PchPcieAspmDisabled,
  66. PchPcieAspmL0s,
  67. PchPcieAspmL1,
  68. PchPcieAspmL0sL1,
  69. PchPcieAspmAutoConfig,
  70. PchPcieAspmMax
  71. } PCH_PCIE_ASPM_CONTROL;
  72. /**
  73. Refer to PCH EDS for the PCH implementation values corresponding
  74. to below PCI-E spec defined ranges
  75. **/
  76. typedef enum {
  77. PchPcieL1SubstatesDisabled,
  78. PchPcieL1SubstatesL1_1,
  79. PchPcieL1SubstatesL1_2,
  80. PchPcieL1SubstatesL1_1_2,
  81. PchPcieL1SubstatesMax
  82. } PCH_PCIE_L1SUBSTATES_CONTROL;
  83. enum PCH_PCIE_MAX_PAYLOAD {
  84. PchPcieMaxPayload128 = 0,
  85. PchPcieMaxPayload256,
  86. PchPcieMaxPayloadMax
  87. };
  88. enum PCH_PCIE_COMPLETION_TIMEOUT {
  89. PchPcieCompletionTO_Default,
  90. PchPcieCompletionTO_50_100us,
  91. PchPcieCompletionTO_1_10ms,
  92. PchPcieCompletionTO_16_55ms,
  93. PchPcieCompletionTO_65_210ms,
  94. PchPcieCompletionTO_260_900ms,
  95. PchPcieCompletionTO_1_3P5s,
  96. PchPcieCompletionTO_4_13s,
  97. PchPcieCompletionTO_17_64s,
  98. PchPcieCompletionTO_Disabled
  99. };
  100. enum PCH_PCIE_MPL {
  101. PchPcieMaxPayLoad128B,
  102. PchPcieMaxPayLoad256B,
  103. PchPcieMaxPayLoad512B,
  104. };
  105. typedef enum {
  106. PchPcieEqDefault = 0, ///< Use reference code default (software margining)
  107. PchPcieEqHardware = 1, ///< Hardware equalization (experimental), note this requires PCH-LP C0 or PCH-H D0 or newer
  108. PchPcieEqSoftware = 2, ///< Use software margining flow
  109. PchPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient settings per lane)
  110. } PCH_PCIE_EQ_METHOD;
  111. /**
  112. Represent lane specific PCIe Gen3 equalization parameters.
  113. **/
  114. typedef struct {
  115. UINT8 Cm; ///< Coefficient C-1
  116. UINT8 Cp; ///< Coefficient C+1
  117. UINT8 Rsvd0[2]; ///< Reserved bytes
  118. } PCH_PCIE_EQ_LANE_PARAM, PCH_PCIE_EQ_PARAM;
  119. /**
  120. The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
  121. **/
  122. typedef struct {
  123. UINT32 Enable : 1; ///< Root Port enabling, 0: Disable; <b>1: Enable</b>.
  124. UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
  125. UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
  126. UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
  127. UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
  128. UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
  129. UINT32 RsvdBits0 : 5; ///< Reserved bits.
  130. UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported by the port.
  131. /**
  132. The ClkReq Signal mapped to this root port. Default is zero. Valid if ClkReqSupported is TRUE.
  133. This Number should not exceed the Maximum Available ClkReq Signals for LP and H.
  134. **/
  135. UINT32 ClkReqNumber : 4;
  136. /**
  137. Probe CLKREQ# signal before enabling CLKREQ# based power management.
  138. Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
  139. to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
  140. In particular this helps to avoid issues with open-ended PCIe slots.
  141. This is only applicable to non hot-plug ports.
  142. <b>0: Disable</b>; 1: Enable.
  143. **/
  144. UINT32 ClkReqDetect : 1;
  145. //
  146. // Error handlings
  147. //
  148. UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
  149. UINT32 RsvdBits1 : 3; ///< Reserved fields for future expansion w/o protocol change
  150. UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
  151. UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
  152. UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
  153. UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
  154. UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
  155. UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
  156. UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
  157. /**
  158. Max Payload Size supported, Default <b>128B</b>, see enum PCH_PCIE_MAX_PAYLOAD
  159. Changes Max Payload Size Supported field in Device Capabilities of the root port.
  160. **/
  161. UINT32 MaxPayload : 2;
  162. /**
  163. Indicates how this root port is connected to endpoint.
  164. 0: built-in device;
  165. 1: slot
  166. Built-in is incompatible with hotplug-capable ports
  167. **/
  168. UINT32 SlotImplemented : 1;
  169. UINT32 DeviceResetPadActiveHigh : 1; ///< Indicated whether PERST# is active <b>0: Low</b>; 1: High, See: DeviceResetPad
  170. /**
  171. Determines each PCIE Port speed capability.
  172. <b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)
  173. **/
  174. UINT8 PcieSpeed;
  175. /**
  176. PCIe Gen3 Equalization Phase 3 Method (see PCH_PCIE_EQ_METHOD).
  177. <b>0: Default</b>; 2: Software Search; 4: Fixed Coeficients
  178. **/
  179. UINT8 Gen3EqPh3Method;
  180. UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
  181. UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: PCH_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
  182. /**
  183. The PCH pin assigned to device PERST# signal if available, zero otherwise.
  184. This entry is used mainly in Gen3 software equalization flow. It is necessary for some devices
  185. (mainly some graphic adapters) to successfully complete the software equalization flow.
  186. See also DeviceResetPadActiveHigh
  187. **/
  188. UINT32 DeviceResetPad;
  189. UINT32 Rsvd1; ///< Reserved bytes
  190. //
  191. // Power Management
  192. //
  193. UINT8 Aspm; ///< The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>.
  194. UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
  195. UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
  196. UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
  197. UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
  198. UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
  199. UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
  200. UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
  201. UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
  202. UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
  203. UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
  204. UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
  205. UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
  206. UINT32 SlotPowerLimitValue : 12; ///< <b>(Test)</b> Specifies upper limit on power supplie by slot. Leave as 0 to set to default. Default is <b>zero</b>.
  207. UINT32 HsioRxSetCtleEnable : 1; ///< @deprecated, please use HsioRxSetCtleEnable from PCH_HSIO_PCIE_LANE_CONFIG
  208. UINT32 HsioRxSetCtle : 6; ///< @deprecated, please use HsioRxSetCtle from PCH_HSIO_PCIE_LANE_CONFIG
  209. //
  210. // Gen3 Equaliztion settings
  211. //
  212. UINT32 Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>5</b>.
  213. UINT32 Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
  214. UINT32 RsvdBits3 : 3; ///< Reserved Bits
  215. UINT32 Rsvd2[16]; ///< Reserved bytes
  216. } PCH_PCIE_ROOT_PORT_CONFIG;
  217. ///
  218. /// The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
  219. ///
  220. typedef struct {
  221. ///
  222. /// These members describe the configuration of each PCH PCIe root port.
  223. ///
  224. PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
  225. ///
  226. /// Pci Delay (Latency) Optimization ECR - Engineering Change Request
  227. ///
  228. UINT8 PciDelayOptimizationEcr;
  229. ///
  230. /// Pch Pcie Max Read Request Size
  231. ///
  232. UINT8 MaxReadRequestSize;
  233. ///
  234. /// Gen3 Equalization settings for physiacal PCIe lane, index 0 represents PCIe lane 1, etc.
  235. /// Correstponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).
  236. ///
  237. PCH_PCIE_EQ_LANE_PARAM EqPh3LaneParam[PCH_MAX_PCIE_ROOT_PORTS];
  238. ///
  239. /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable.
  240. ///
  241. UINT32 EnablePort8xhDecode : 1;
  242. ///
  243. /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
  244. ///
  245. UINT32 PchPciePort8xhDecodePortIndex : 5;
  246. ///
  247. /// This member describes whether the PCI Express Clock Gating for each root port
  248. /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
  249. ///
  250. UINT32 DisableRootPortClockGating : 1;
  251. ///
  252. /// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
  253. ///
  254. UINT32 EnablePeerMemoryWrite : 1;
  255. /**
  256. This member allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable
  257. or leaving untouched.
  258. - <b>0: Disable, ICC PLL Shutdown is determined by PCIe device LTR capablility.</b>
  259. - To allow ICC PLL shutdown if all present PCIe devices are LTR capable or if no PCIe devices are
  260. presented for maximum power savings where possible.
  261. - To disable ICC PLL shutdown when BIOS detects any non-LTR capable PCIe device for ensuring device
  262. functionality.
  263. - 1: Enable, To allow ICC PLL shutdown even if some devices do not support LTR capability.
  264. **/
  265. UINT32 AllowNoLtrIccPllShutdown : 1;
  266. /**
  267. Compliance Test Mode shall be enabled when using Compliance Load Board.
  268. <b>0: Disable</b>, 1: Enable
  269. **/
  270. UINT32 ComplianceTestMode : 1;
  271. /**
  272. RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
  273. A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
  274. BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
  275. - <b>Enabled: One of enabled root ports get assigned to Function0.</b>
  276. This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
  277. - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
  278. That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
  279. NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage
  280. NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
  281. be used when each one of root ports 1, 9, 17:
  282. - is configured as PCIe and has correctly configured ClkReq signal, or
  283. - does not own any mPhy lanes (they are configured as SATA or USB)
  284. **/
  285. UINT32 RpFunctionSwap : 1;
  286. UINT32 RsvdBits0 : 21;
  287. /**
  288. The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
  289. before assuming there is no device and potentially disabling the port.
  290. It's assumed that the link will exit detect state before root port initialization (sufficient time
  291. elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
  292. if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
  293. I case of non-common clock enabled the default timout is 15ms.
  294. <b>Default: 0</b>
  295. **/
  296. UINT16 DetectTimeoutMs;
  297. ///
  298. /// These are Competions Timeout settings for Uplink ports in Server PCH
  299. ///
  300. UINT8 PchPcieUX16CompletionTimeout;
  301. UINT8 PchPcieUX8CompletionTimeout;
  302. ///
  303. /// Max Payload Size settings for Upling ports in Server PCH
  304. ///
  305. UINT8 PchPcieUX16MaxPayload;
  306. UINT8 PchPcieUX8MaxPayload;
  307. ///
  308. /// Intel+ Virtual Technology for Directed I/O (VT-d) Support
  309. ///
  310. UINT8 VTdSupport;
  311. UINT16 Rsvd0; ///< Reserved bytes
  312. UINT32 Rsvd1[2]; ///< Reserved bytes
  313. } PCH_PCIE_CONFIG;
  314. ///
  315. /// The PCH_PCIE_CONFIG2 block describes the additional configuration of the PCH PCI Express controllers
  316. ///
  317. typedef struct {
  318. PCH_PCIE_EQ_PARAM SwEqCoeffList[PCH_PCIE_SWEQ_COEFFS_MAX]; ///< List of coefficients used during equalization (applicable to both software and hardware EQ)
  319. PCH_PCIE_EQ_PARAM Rsvd0[3];
  320. UINT32 Rsvd1[4];
  321. } PCH_PCIE_CONFIG2;
  322. typedef struct {
  323. UINT8 PchAdrEn;
  324. UINT8 AdrTimerEn;
  325. UINT8 AdrTimerVal;
  326. UINT8 AdrMultiplierVal;
  327. UINT8 AdrGpioSel;
  328. UINT8 AdrHostPartitionReset;
  329. UINT8 AdrSysPwrOk;
  330. UINT8 AdrOverClockingWdt;
  331. UINT8 AdrCpuThermalWdt;
  332. UINT8 AdrPmcParityError;
  333. } PCH_ADR_CONFIG;
  334. /**
  335. The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane
  336. **/
  337. typedef struct {
  338. //
  339. // HSIO Rx Eq
  340. // Refer to the EDS for recommended values.
  341. // Note that these setting are per-lane and not per-port
  342. //
  343. UINT32 HsioRxSetCtleEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 3 Set CTLE Value
  344. UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set CTLE Value
  345. UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value override
  346. UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value
  347. UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value override
  348. UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value
  349. UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value override
  350. UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value
  351. UINT32 RsvdBits0 : 4; ///< Reserved Bits
  352. UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value override
  353. UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting
  354. UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting value override
  355. UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting
  356. UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting value override
  357. UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting
  358. UINT32 RsvdBits1 : 11; ///< Reserved Bits
  359. //
  360. // Server specific offsets
  361. //
  362. UINT32 HsioIcfgAdjLimitLoEnable : 1; /// < <b>0: Disable</b>; 1: Enable Set the floor on how many ticks the autovref can take.
  363. UINT32 HsioIcfgAdjLimitLo : 5; /// < Set the floor on how many ticks the autovref can take. (offset 0x9c)
  364. UINT32 HsioSampOffstEvenErrSpEnable : 1; /// < <b>0: Disable</b>; 1: Enable EVEN ERR P sampler manual offset.
  365. UINT32 HsioSampOffstEvenErrSp : 8; /// < EVEN ERR P sampler manual offset. (offset 0xA0)
  366. UINT32 RsvdBits2 : 17; ///< Reserved Bits
  367. UINT32 HsioRemainingSamplerOffEnable : 1; /// < <b>0: Disable</b>; 1: Enable Remaining EVEN/ODD ERR P and N sampler manual offset.
  368. UINT32 HsioRemainingSamplerOff : 24; /// < Remaining EVEN/ODD ERR P and N sampler manual offset. (offset 0xA4)
  369. UINT32 HsioVgaGainCalEnable : 1; /// < <b>0: Disable</b>; 1: Enable VGA Gain CAL
  370. UINT32 HsioVgaGainCal : 5; /// < VGA Gain Calibration Value (offset 0x1C)
  371. UINT32 RsvdBits3 : 1; ///< Reserved Bits
  372. UINT32 Rsvd4[12]; ///< Reserved bytes
  373. } PCH_HSIO_PCIE_LANE_CONFIG;
  374. ///
  375. /// The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes
  376. ///
  377. typedef struct {
  378. ///
  379. /// These members describe the configuration of HSIO for PCIe lanes.
  380. ///
  381. PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS];
  382. UINT32 Rsvd0[3]; ///< Reserved bytes
  383. } PCH_HSIO_PCIE_CONFIG;
  384. ///
  385. /// The PCH_HSIO_PCIE_WM20_CONFIG block describes the configuration of the HSIO for PCIe lanes
  386. ///
  387. typedef struct {
  388. ///
  389. /// These members describe the configuration of HSIO for PCIe lanes.
  390. ///
  391. PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_WM20_LANES_NUMBER];
  392. UINT32 Rsvd0[3]; ///< Reserved bytes
  393. } PCH_HSIO_PCIE_WM20_CONFIG;
  394. //
  395. // ---------------------------- EVA Config -----------------------------
  396. //
  397. // EVA port function hide registers.
  398. typedef union {
  399. UINT32 FuncHideVal;
  400. struct _FuncHideBits {
  401. UINT32 PchEvaMROM0Enable : 1; ///< MROM is never hidden
  402. UINT32 PchEvaMROM1Hidden : 1; ///< Enable/disable MROM1 funcion, 1 - hidden
  403. UINT32 RsvdBits1 : 3;
  404. UINT32 PchEvasSata1Hidden : 1; ///< Enable/disable sSata1, 1 - hidden
  405. UINT32 RsvdBits2 : 25;
  406. UINT32 PchEvaLock : 1; ///< Lock registers in EVA
  407. } FuncHideBits;
  408. }
  409. PCH_EVA_DNDEVFUNCHIDE;
  410. typedef struct {
  411. PCH_EVA_DNDEVFUNCHIDE FuncHide;
  412. UINT8 LockDown;
  413. }
  414. PCH_EVA_CONFIG;
  415. //
  416. // ---------------------------- SATA Config -----------------------------
  417. //
  418. typedef enum {
  419. PchSataModeAhci,
  420. PchSataModeRaid,
  421. PchSataModeMax
  422. } PCH_SATA_MODE;
  423. typedef enum {
  424. PchSataOromDelay2sec,
  425. PchSataOromDelay4sec,
  426. PchSataOromDelay6sec,
  427. PchSataOromDelay8sec
  428. } PCH_SATA_OROM_DELAY;
  429. typedef enum {
  430. PchSataSpeedDefault,
  431. PchSataSpeedGen1,
  432. PchSataSpeedGen2,
  433. PchSataSpeedGen3
  434. } PCH_SATA_SPEED;
  435. /**
  436. This structure configures the features, property, and capability for each SATA port.
  437. **/
  438. typedef struct {
  439. /**
  440. Enable SATA port.
  441. It is highly recommended to disable unused ports for power savings
  442. **/
  443. UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>
  444. UINT32 HotPlug : 1; ///< <b>0: Disable</b>; 1: Enable
  445. UINT32 InterlockSw : 1; ///< <b>0: Disable</b>; 1: Enable
  446. UINT32 External : 1; ///< <b>0: Disable</b>; 1: Enable
  447. UINT32 SpinUp : 1; ///< <b>0: Disable</b>; 1: Enable the COMRESET initialization Sequence to the device
  448. UINT32 SolidStateDrive : 1; ///< <b>0: HDD</b>; 1: SSD
  449. UINT32 DevSlp : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP on the port
  450. UINT32 EnableDitoConfig : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
  451. UINT32 DmVal : 4; ///< DITO multiplier. Default is <b>15</b>.
  452. UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO), Default is <b>625</b>.
  453. /**
  454. Support zero power ODD <b>0: Disable</b>, 1: Enable.
  455. This is also used to disable ModPHY dynamic power gate.
  456. **/
  457. UINT32 ZpOdd : 1;
  458. UINT32 RsvdBits0 : 9; ///< Reserved fields for future expansion w/o protocol change
  459. UINT32 HsioRxEqBoostMagAdEnable : 1; ///< @deprecated, please use HsioRxGen3EqBoostMagEnable
  460. UINT32 HsioRxEqBoostMagAd : 6; ///< @deprecated, please use HsioRxGen3EqBoostMag
  461. UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< @deprecated, please use HsioTxGen1DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE
  462. UINT32 HsioTxGen1DownscaleAmp : 6; ///< @deprecated, please use HsioTxGen1DownscaleAmp in PCH_HSIO_SATA_PORT_LANE
  463. UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< @deprecated, please use HsioTxGen2DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE
  464. UINT32 HsioTxGen2DownscaleAmp : 6; ///< @deprecated, please use HsioTxGen2DownscaleAmp in PCH_HSIO_SATA_PORT_LANE
  465. UINT32 Rsvd0 : 11; ///< Reserved bits
  466. } PCH_SATA_PORT_CONFIG;
  467. /**
  468. Rapid Storage Technology settings.
  469. **/
  470. typedef struct {
  471. UINT32 RaidAlternateId : 1; ///< <b>0: Disable</b>; 1: Enable RAID Alternate ID
  472. UINT32 Raid0 : 1; ///< 0: Disable; <b>1: Enable</b> RAID0
  473. UINT32 Raid1 : 1; ///< 0: Disable; <b>1: Enable</b> RAID1
  474. UINT32 Raid10 : 1; ///< 0: Disable; <b>1: Enable</b> RAID10
  475. UINT32 Raid5 : 1; ///< 0: Disable; <b>1: Enable</b> RAID5
  476. UINT32 Irrt : 1; ///< 0: Disable; <b>1: Enable</b> Intel Rapid Recovery Technology
  477. UINT32 OromUiBanner : 1; ///< 0: Disable; <b>1: Enable</b> OROM UI and BANNER
  478. UINT32 OromUiDelay : 2; ///< <b>00b: 2 secs</b>; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY)
  479. UINT32 HddUnlock : 1; ///< 0: Disable; <b>1: Enable</b>. Indicates that the HDD password unlock in the OS is enabled
  480. UINT32 LedLocate : 1; ///< 0: Disable; <b>1: Enable</b>. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
  481. UINT32 IrrtOnly : 1; ///< 0: Disable; <b>1: Enable</b>. Allow only IRRT drives to span internal and external ports
  482. UINT32 SmartStorage : 1; ///< 0: Disable; <b>1: Enable</b> RST Smart Storage caching Bit
  483. UINT32 EfiRaidDriverLoad :1; ///< 0: Dont load EFI RST/RSTe driver; <b>1: Load EFI RST/RSTe driver
  484. UINT32 Resvdbits : 18; ///< Reserved Bits
  485. } PCH_SATA_RST_CONFIG;
  486. /**
  487. This structure describes the details of Intel RST for PCIe Storage remapping
  488. Note: In order to use this feature, Intel RST Driver is required
  489. **/
  490. typedef struct {
  491. /**
  492. This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. <b>0: Disable</b>; 1: Enable.
  493. Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well
  494. Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID
  495. **/
  496. UINT32 Enable : 1;
  497. /**
  498. Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <b>0 = autodetect</b>)
  499. The supported ports for PCIe Storage remapping is different depend on the platform and cycle router, the assignments are as below:
  500. SKL PCH-LP RST PCIe Storage Cycle Router Assignment:
  501. i.) RST PCIe Storage Cycle Router 2 -> RP5 - RP8
  502. ii.) RST PCIe Storage Cycle Router 3 -> RP9 - RP12
  503. SKL PCH-H RST PCIe Storage Cycle Router Assignment:
  504. i.) RST PCIe Storage Cycle Router 1 -> RP9 - RP12
  505. ii.) RST PCIe Storage Cycle Router 2 -> RP13 - RP16
  506. iii.) RST PCIe Storage Cycle Router 3 -> RP17 - RP20
  507. **/
  508. UINT32 RstPcieStoragePort : 5;
  509. UINT32 RsvdBits0 : 2; ///< Reserved bit
  510. /**
  511. PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled
  512. before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step.
  513. Default value is <b>100ms</b>.
  514. **/
  515. UINT32 DeviceResetDelay : 8;
  516. UINT32 RsvdBits1 : 16; ///< Reserved bits
  517. UINT32 Rsvd0[2]; ///< Reserved bytes
  518. } PCH_RST_PCIE_STORAGE_CONFIG;
  519. ///
  520. /// The PCH_SATA_CONFIG block describes the expected configuration of the SATA controllers.
  521. ///
  522. typedef struct {
  523. ///
  524. /// This member describes whether or not the SATA controllers should be enabled. 0: Disable; <b>1: Enable</b>.
  525. ///
  526. UINT32 Enable : 1;
  527. UINT32 TestMode : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Allow entrance to the PCH SATA test modes
  528. UINT32 SalpSupport : 1; ///< 0: Disable; <b>1: Enable</b> Aggressive Link Power Management
  529. UINT32 PwrOptEnable : 1; ///< 0: Disable; <b>1: Enable</b> SATA Power Optimizer on PCH side.
  530. /**
  531. eSATASpeedLimit
  532. When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
  533. Please be noted, this setting could be cleared by HBA reset, which might be issued
  534. by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after POST.
  535. To support the Speed Limitation when POST, the EFI AHCI driver should preserve the
  536. setting before and after initialization. For support it after POST, it's dependent on
  537. driver's behavior.
  538. <b>0: Disable</b>; 1: Enable
  539. **/
  540. UINT32 eSATASpeedLimit : 1;
  541. UINT32 EnclosureSupport : 1; ///< 0: Disable; 1: Enable Enclosure Management Support
  542. UINT32 Rsvdbits : 26; ///< Reserved bits
  543. /**
  544. Determines the system will be configured to which SATA mode (PCH_SATA_MODE). Default is <b>PchSataModeAhci</b>.
  545. **/
  546. PCH_SATA_MODE SataMode;
  547. /**
  548. Indicates the maximum speed the SATA controller can support
  549. <b>0h: PchSataSpeedDefault</b>; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1)
  550. **/
  551. PCH_SATA_SPEED SpeedLimit;
  552. /**
  553. This member configures the features, property, and capability for each SATA port.
  554. **/
  555. PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS];
  556. PCH_SATA_RST_CONFIG Rst; ///< Setting applicable to Rapid Storage Technology
  557. /**
  558. This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required)
  559. **/
  560. PCH_RST_PCIE_STORAGE_CONFIG RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR];
  561. UINT32 Rsvd0[4]; ///< Reserved fields for future expansion
  562. } PCH_SATA_CONFIG;
  563. /**
  564. The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane
  565. **/
  566. typedef struct {
  567. //
  568. // HSIO Rx Eq
  569. //
  570. UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
  571. UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value
  572. UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
  573. UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value
  574. UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
  575. UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value
  576. //
  577. // HSIO Tx Eq
  578. //
  579. UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
  580. UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
  581. UINT32 RsvdBits0 : 4; ///< Reserved bits
  582. UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
  583. UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment
  584. UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
  585. UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment
  586. UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
  587. UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
  588. UINT32 HsioTxGen2DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
  589. UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
  590. UINT32 RsvdBits1 : 4; ///< Reserved bits
  591. UINT32 HsioTxGen3DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
  592. UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
  593. UINT32 RsvdBits2 : 25; ///< Reserved bits
  594. UINT32 Rsvd0[8]; ///< Reserved bytes
  595. } PCH_HSIO_SATA_PORT_LANE;
  596. ///
  597. /// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller.
  598. ///
  599. typedef struct {
  600. ///
  601. /// These members describe the configuration of HSIO for SATA lanes.
  602. ///
  603. PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS];
  604. UINT32 Rsvd0[8]; ///< Reserved bytes
  605. } PCH_HSIO_SATA_CONFIG;
  606. //
  607. // --------------------------- IO APIC Config ------------------------------
  608. //
  609. /**
  610. The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH
  611. IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is
  612. not TRUE. Bus:device:function fields will be programmed to the register
  613. P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose:
  614. As the Requester ID when initiating Interrupt Messages to the processor.
  615. As the Completer ID when responding to the reads targeting the IOxAPI's
  616. Memory-Mapped I/O registers.
  617. This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can
  618. program this field to provide a unique Bus:Device:Function number for the
  619. internal IOxAPIC.
  620. The address resource range of IOAPIC must be reserved in E820 and ACPI as
  621. system resource.
  622. **/
  623. typedef struct {
  624. UINT32 BdfValid : 1; ///< Set to 1 if BDF value is valid, PCH code will not program these fields if this bit is not TRUE. <b>0: Disable</b>; 1: Enable.
  625. UINT32 RsvdBits0 : 7; ///< Reserved bits
  626. UINT32 BusNumber : 8; ///< Bus/Device/Function used as Requestor / Completer ID. Default is <b>0xF0</b>.
  627. UINT32 DeviceNumber : 5; ///< Bus/Device/Function used as Requestor / Completer ID. Default is <b>0x1F</b>.
  628. UINT32 FunctionNumber : 3; ///< Bus/Device/Function used as Requestor / Completer ID. Default is <b>0x00</b>.
  629. UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; <b>1: Enable</b> IOAPIC Entry 24-119
  630. UINT32 RsvdBits1 : 7; ///< Reserved bits
  631. UINT8 IoApicId; ///< This member determines IOAPIC ID. Default is <b>0x02</b>.
  632. UINT8 ApicRangeSelect; ///< Define address bits 19:12 for the IOxAPIC range. Default is <b>0</b>
  633. UINT8 Rsvd0[2]; ///< Reserved bytes
  634. } PCH_IOAPIC_CONFIG;
  635. //
  636. // ---------------------------- HPET Config -----------------------------
  637. //
  638. /**
  639. The PCH_HPET_CONFIG block passes the bus/device/function value for HPET.
  640. The address resource range of HPET must be reserved in E820 and ACPI as
  641. system resource.
  642. **/
  643. typedef struct {
  644. /**
  645. Determines if enable HPET timer. 0: Disable; <b>1: Enable</b>.
  646. The HPET timer address decode is always enabled.
  647. This policy is used to configure the HPET timer count, and also the _STA of HPET device in ACPI.
  648. While enabled, the HPET timer is started, else the HPET timer is halted.
  649. **/
  650. UINT32 Enable : 1;
  651. UINT32 BdfValid : 1; ///< Whether the BDF value is valid. <b>0: Disable</b>; 1: Enable.
  652. UINT32 RsvdBits0 : 6; ///< Reserved bits
  653. UINT32 BusNumber : 8; ///< Bus Number HPETn used as Requestor / Completer ID. Default is <b>0xF0</b>.
  654. UINT32 DeviceNumber : 5; ///< Device Number HPETn used as Requestor / Completer ID. Default is <b>0x1F</b>.
  655. UINT32 FunctionNumber : 3; ///< Function Number HPETn used as Requestor / Completer ID. Default is <b>0x00</b>.
  656. UINT32 RsvdBits1 : 8; ///< Reserved bits
  657. UINT32 Base; ///< The HPET base address. Default is <b>0xFED00000</b>.
  658. } PCH_HPET_CONFIG;
  659. //
  660. // --------------------------- HD-Audio Config ------------------------------
  661. //
  662. ///
  663. /// The PCH_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature.
  664. ///
  665. #define PCH_HDAUDIO_AUTO 2
  666. enum PCH_HDAUDIO_IO_BUFFER_OWNERSHIP {
  667. PchHdaIoBufOwnerHdaLink = 0, ///< HD-Audio link owns all the I/O buffers.
  668. PchHdaIoBufOwnerHdaLinkI2sPort = 1, ///< HD-Audio link owns 4 and I2S port owns 4 of the I/O buffers.
  669. PchHdaIoBufOwnerI2sPort = 3 ///< I2S0 and I2S1 ports own all the I/O buffers.
  670. };
  671. enum PCH_HDAUDIO_IO_BUFFER_VOLTAGE {
  672. PchHdaIoBuf33V = 0,
  673. PchHdaIoBuf18V = 1
  674. };
  675. enum PCH_HDAUDIO_VC_TYPE {
  676. PchHdaVc0 = 0,
  677. PchHdaVc1 = 1
  678. };
  679. enum PCH_HDAUDIO_DMIC_TYPE {
  680. PchHdaDmicDisabled = 0,
  681. PchHdaDmic2chArray = 1,
  682. PchHdaDmic4chArray = 2,
  683. PchHdaDmic1chArray = 3
  684. };
  685. typedef enum {
  686. PchHdaLinkFreq6MHz = 0,
  687. PchHdaLinkFreq12MHz = 1,
  688. PchHdaLinkFreq24MHz = 2,
  689. PchHdaLinkFreq48MHz = 3,
  690. PchHdaLinkFreq96MHz = 4,
  691. PchHdaLinkFreqInvalid
  692. } PCH_HDAUDIO_LINK_FREQUENCY;
  693. typedef enum {
  694. PchHdaIDispMode2T = 0,
  695. PchHdaIDispMode1T = 1
  696. } PCH_HDAUDIO_IDISP_TMODE;
  697. /**
  698. This structure contains the policies which are related to HD Audio device (cAVS).
  699. **/
  700. typedef struct {
  701. /**
  702. This member describes whether or not Intel HD Audio (Azalia) should be enabled.
  703. If enabled (in Auto mode) and no codec exists the reference code will automatically disable
  704. the HD Audio device.
  705. 0: Disable, 1: Enable, <b>2: Auto (enabled if codec detected and initialized, disabled otherwise)</b>
  706. **/
  707. UINT32 Enable : 2;
  708. UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1: Enable</b>
  709. UINT32 Pme : 1; ///< Azalia wake-on-ring, <b>0: Disable</b>; 1: Enable
  710. UINT32 IoBufferOwnership : 2; ///< I/O Buffer Ownership Select: <b>0: HD-A Link</b>; 1: Shared, HD-A Link and I2S Port; 3: I2S Ports
  711. UINT32 IoBufferVoltage : 1; ///< I/O Buffer Voltage Mode Select: <b>0: 3.3V</b>; 1: 1.8V
  712. UINT32 VcType : 1; ///< Virtual Channel Type Select: <b>0: VC0</b>, 1: VC1
  713. UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>2: 24MHz</b>, 1: 12MHz, 0: 6MHz
  714. UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>4: 96MHz</b>, 3: 48MHz
  715. UINT32 IDispLinkTmode : 1; ///< iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): <b>0: 2T</b>, 1: 1T
  716. /**
  717. Universal Audio Architecture compliance for DSP enabled system:
  718. <b>0: Not-UAA Compliant (Intel SST driver supported only)</b>,
  719. 1: UAA Compliant (HDA Inbox driver or SST driver supported)
  720. **/
  721. UINT32 DspUaaCompliance : 1;
  722. UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconnection, <b>0: Not disconnected, enumerable</b>; 1: Disconnected SDI, not enumerable
  723. UINT32 RsvdBits0 : 13; ///< Reserved bits 1
  724. /**
  725. Bitmask of supported DSP endpoint configuration exposed via NHLT ACPI table:
  726. **/
  727. UINT32 DspEndpointDmic : 2; ///< DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum): 0: Disable; 1: 2ch array; <b>2: 4ch array</b>; 3: 1ch array
  728. UINT32 DspEndpointBluetooth : 1; ///< Bluetooth enablement: <b>0: Disable</b>; 1: Enable
  729. UINT32 DspEndpointI2s : 1; ///< I2S enablement: <b>0: Disable</b>; 1: Enable
  730. UINT32 RsvdBits1 : 28; ///< Reserved bits 2
  731. /**
  732. Bitmask of supported DSP features:
  733. [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP
  734. [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation
  735. Default is <b>zero</b>.
  736. **/
  737. UINT32 DspFeatureMask;
  738. /**
  739. Bitmask of supported DSP Pre/Post-Processing Modules.
  740. Specific pre/post-processing module bit position must be coherent with the ACPI implementation:
  741. \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing Module Support.
  742. DspPpModuleMask is passed to ACPI as 'ADPM' NVS variable
  743. Default is <b>zero</b>.
  744. **/
  745. UINT32 DspPpModuleMask;
  746. UINT16 ResetWaitTimer; ///< <b>(Test)</b> The delay timer after Azalia reset, the value is number of microseconds. Default is <b>600</b>.
  747. UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4
  748. } PCH_HDAUDIO_CONFIG;
  749. //
  750. // ------------------------------ LAN Config ---------------------------------
  751. //
  752. /**
  753. PCH intergrated LAN controller configuration settings.
  754. **/
  755. typedef struct {
  756. /**
  757. Determines if enable PCH internal LAN, 0: Disable; <b>1: Enable</b>.
  758. When Enable is changed (from disabled to enabled or from enabled to disabled),
  759. it needs to set LAN Disable regsiter, which might be locked by FDSWL register.
  760. So it's recommendated to issue a global reset when changing the status for PCH Internal LAN.
  761. **/
  762. UINT32 Enable : 1;
  763. UINT32 K1OffEnable : 1; ///< Use CLKREQ for GbE power management; 1: Enabled, <b>0: Disabled</b>;
  764. UINT32 RsvdBits0 : 4; ///< Reserved bits
  765. UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported; 1: Enabled, <b>0: Disabled</b>;
  766. UINT32 ClkReqNumber : 4; ///< CLKREQ# used by GbE. Valid if ClkReqSupported is TRUE.
  767. UINT32 RsvdBits1 : 21; ///< Reserved bits
  768. UINT32 Rsvd0; ///< Reserved bytes
  769. } PCH_LAN_CONFIG;
  770. //
  771. // --------------------------- SMBUS Config ------------------------------
  772. //
  773. #define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
  774. ///
  775. /// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
  776. ///
  777. typedef struct {
  778. /**
  779. This member describes whether or not the SMBus controller of PCH should be enabled.
  780. 0: Disable; <b>1: Enable</b>.
  781. **/
  782. UINT32 Enable : 1;
  783. UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable.
  784. UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating.
  785. UINT32 RsvdBits0 : 29; ///< Reserved bits
  786. UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>.
  787. UINT8 Rsvd0; ///< Reserved bytes
  788. UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
  789. /**
  790. Array of addresses reserved for non-ARP-capable SMBus devices.
  791. **/
  792. UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
  793. } PCH_SMBUS_CONFIG;
  794. //
  795. // --------------------------- Lock Down Config ------------------------------
  796. //
  797. /**
  798. The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH
  799. for security requirement.
  800. **/
  801. typedef struct {
  802. /**
  803. <b>(Test)</b> Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0: Disable; <b>1: Enable</b>.
  804. **/
  805. UINT32 GlobalSmi : 1;
  806. /**
  807. <b>(Test)</b> Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register
  808. Top Swap bit and the General Control and Status Registers Boot BIOS Straps. 0: Disable; <b>1: Enable</b>.
  809. **/
  810. UINT32 BiosInterface : 1;
  811. /**
  812. <b>(Test)</b> Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
  813. and lower 128-byte bank of RTC RAM. 0: Disable; <b>1: Enable</b>.
  814. **/
  815. UINT32 RtcLock : 1;
  816. /**
  817. Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5])
  818. for the BIOS region protection. When it is enabled, the BIOS Region can only be
  819. modified from SMM after EndOfDxe protocol is installed.
  820. Note: When BiosLock is enabled, platform code also needs to update to take care
  821. of BIOS modification (including SetVariable) in DXE or runtime phase after
  822. EndOfDxe protocol is installed. <b>0: Disable</b>; 1: Enable.
  823. **/
  824. UINT32 BiosLock : 1;
  825. /**
  826. Enable InSMM.STS (EISS) in SPI
  827. If this bit is set, then WPD must be a '1' and InSMM.STS must be '1' also
  828. in order to write to BIOS regions of SPI Flash. If this bit is clear,
  829. then the InSMM.STS is a don't care.
  830. The BIOS must set the EISS bit while BIOS Guard support is enabled.
  831. In recovery path, platform can temporary disable EISS for SPI programming in
  832. PEI phase or early DXE phase.
  833. 0: Clear EISS bit; <b>1: Set EISS bit</b>.
  834. **/
  835. UINT32 SpiEiss : 1;
  836. /**
  837. Lock configuration and/or state of vendor-defined set of GPIOs.
  838. 0: Don't lock; 1: Lock
  839. **/
  840. UINT32 GpioLockDown : 1;
  841. /**
  842. Lock TCO Base Address.
  843. D31:F4 (SMBus Controller) Offset 54h: TCOCTL (TCO Control Register) Bit 0: TCO_BASE_LOCK (TCO Base Lock)
  844. 0: Don't lock; 1: Lock
  845. **/
  846. UINT32 TcoLock : 1;
  847. /**
  848. <b>(Test)</b> Enable Lock bit for Device Function Hide Register in
  849. MS Unit Device Function Hide Control Register (MSDEVFUNCHIDE)
  850. 0: Disable; <b>1: Enable</b>.
  851. **/
  852. UINT32 EvaLockDown : 1;
  853. UINT32 RsvdBits0 : 24; ///< Reserved bits
  854. } PCH_LOCK_DOWN_CONFIG;
  855. //
  856. // --------------------------- Thermal Config ------------------------------------
  857. //
  858. /**
  859. This structure lists PCH supported throttling register setting for custimization.
  860. When the SuggestedSetting is enabled, the customized values are ignored.
  861. **/
  862. typedef struct {
  863. UINT32 T0Level : 9; ///< Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
  864. UINT32 T1Level : 9; ///< Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
  865. UINT32 T2Level : 9; ///< Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
  866. UINT32 TTEnable : 1; ///< Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
  867. /**
  868. When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.
  869. If SuggestedSetting is used, this setting is ignored.
  870. **/
  871. UINT32 TTState13Enable : 1;
  872. /**
  873. When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.
  874. If SuggestedSetting is used, this setting is ignored.
  875. **/
  876. UINT32 TTLock : 1;
  877. UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values.
  878. /**
  879. ULT processors support thermal management and cross thermal throttling between the processor package
  880. and LP PCH. The PMSYNC message from PCH to CPU includes specific bit fields to update the PCH
  881. thermal status to the processor which is factored into the processor throttling.
  882. Enable/Disable PCH Cross Throttling; 0: Disabled, 1: <b>Enabled</b>.
  883. **/
  884. UINT32 PchCrossThrottling : 1;
  885. UINT32 Rsvd0; ///< Reserved bytes
  886. } THERMAL_THROTTLE_LEVELS;
  887. /**
  888. This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design.
  889. When the SuggestedSetting is enabled, the customized values are ignored.
  890. **/
  891. typedef struct {
  892. UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous Width Enable
  893. UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
  894. UINT32 RsvdBits0 : 6; ///< Reserved bits
  895. UINT32 TS0TW : 2; ///< Thermal Sensor 0 Target Width
  896. UINT32 TS1TW : 2; ///< Thermal Sensor 1 Target Width
  897. UINT32 TS2TW : 2; ///< Thermal Sensor 2 Target Width
  898. UINT32 TS3TW : 2; ///< Thermal Sensor 3 Target Width
  899. UINT32 RsvdBits1 : 16; ///< Reserved bits
  900. } DMI_HW_WIDTH_CONTROL;
  901. /**
  902. This structure lists PCH supported SATA thermal throttling register setting for custimization.
  903. The settings is programmed through SATA Index/Data registers.
  904. When the SuggestedSetting is enabled, the customized values are ignored.
  905. **/
  906. typedef struct {
  907. UINT32 P0T1M : 2; ///< Port 0 T1 Multipler
  908. UINT32 P0T2M : 2; ///< Port 0 T2 Multipler
  909. UINT32 P0T3M : 2; ///< Port 0 T3 Multipler
  910. UINT32 P0TDisp : 2; ///< Port 0 Tdispatch
  911. UINT32 P1T1M : 2; ///< Port 1 T1 Multipler
  912. UINT32 P1T2M : 2; ///< Port 1 T2 Multipler
  913. UINT32 P1T3M : 2; ///< Port 1 T3 Multipler
  914. UINT32 P1TDisp : 2; ///< Port 1 Tdispatch
  915. UINT32 P0Tinact : 2; ///< Port 0 Tinactive
  916. UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Tdispatch
  917. UINT32 P1Tinact : 2; ///< Port 1 Tinactive
  918. UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Tdispatch
  919. UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
  920. UINT32 RsvdBits0 : 9; ///< Reserved bits
  921. } SATA_THERMAL_THROTTLE;
  922. /**
  923. This structure decides the settings of PCH Thermal throttling. When the Suggested Setting
  924. is enabled, PCH RC will use the suggested representative values.
  925. **/
  926. typedef struct {
  927. THERMAL_THROTTLE_LEVELS TTLevels;
  928. DMI_HW_WIDTH_CONTROL DmiHaAWC;
  929. SATA_THERMAL_THROTTLE SataTT;
  930. SATA_THERMAL_THROTTLE sSataTT;
  931. } PCH_THERMAL_THROTTLING;
  932. /**
  933. This structure configures PCH memory throttling thermal sensor GPIO PIN settings
  934. **/
  935. typedef struct {
  936. /**
  937. GPIO PM_SYNC enable, 0:Diabled, 1:<b>Enabled</b>
  938. When enabled, RC will overrides the selected GPIO native mode.
  939. For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1
  940. For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2
  941. For SKL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, CPU_GP_3 is GPP_B4.
  942. **/
  943. UINT32 PmsyncEnable : 1;
  944. UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 state, 0:Disabled, 1:<b>Enabled</b>
  945. UINT32 PinSelection : 1; ///< GPIO Pin assignment selection, <b>0: default</b>, 1: secondary
  946. UINT32 RsvdBits0 : 29;
  947. } TS_GPIO_PIN_SETTING;
  948. enum PCH_PMSYNC_GPIO_X_SELECTION {
  949. TsGpioC,
  950. TsGpioD,
  951. MaxTsGpioPin
  952. };
  953. /**
  954. This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board).
  955. **/
  956. typedef struct {
  957. /**
  958. This will enable PCH memory throttling.
  959. While this policy is enabled, must also enable EnableExtts in SA policy.
  960. <b>0: Disable</b>; 1: Enable
  961. **/
  962. UINT32 Enable : 1;
  963. UINT32 RsvdBits0 : 31;
  964. /**
  965. GPIO_C and GPIO_D selection for memory throttling.
  966. It's strongly recommended to choose GPIO_C and GPIO_D for memory throttling feature,
  967. and route EXTTS# accordingly.
  968. **/
  969. TS_GPIO_PIN_SETTING TsGpioPinSetting[2];
  970. } PCH_MEMORY_THROTTLING;
  971. /**
  972. The PCH_THERMAL_CONFIG block describes the expected configuration of the PCH for Thermal.
  973. **/
  974. typedef struct {
  975. /**
  976. This field reports the status of Thermal Device. When it reports ThermalDevice
  977. is disabled, the PCI configuration space of thermal device will be hidden by
  978. setting TCFD and PCR[PSF2] TRH PCIEN[8] prior to end of POST.
  979. **/
  980. UINT32 ThermalDeviceEnable : 2; ///< 0: Disabled, <b>1: Enabled in PCI mode</b>, 2: Enabled in ACPI mode
  981. UINT32 TsmicLock : 1; ///< This locks down "SMI Enable on Alert Thermal Sensor Trip". 0: Disabled, 1: <b>Enabled</b>.
  982. UINT32 RsvdBits0 : 29;
  983. /**
  984. This field decides the settings of Thermal throttling. When the Suggested Setting
  985. is enabled, PCH RC will use the suggested representative values.
  986. **/
  987. PCH_THERMAL_THROTTLING ThermalThrottling;
  988. /**
  989. Memory Thermal Management settings
  990. **/
  991. PCH_MEMORY_THROTTLING MemoryThrottling;
  992. /**
  993. This field decides the temperature, default is <b>zero</b>.
  994. - 0x00 is the hottest
  995. - 0x1FF is the lowest temperature
  996. **/
  997. UINT16 PchHotLevel;
  998. UINT8 Rsvd0[6];
  999. } PCH_THERMAL_CONFIG;
  1000. enum PCH_THERMAL_DEVICE {
  1001. PchThermalDeviceDisabled,
  1002. PchThermalDeviceEnabledPci,
  1003. PchThermalDeviceEnabledAcpi,
  1004. PchThermalDeviceAuto
  1005. };
  1006. //
  1007. // ---------------------- Power Management Config --------------------------
  1008. //
  1009. /**
  1010. This PCH_POWER_RESET_STATUS Specifies which Power/Reset bits need to be cleared by the PCH Init Driver.
  1011. Usually platform drivers take care of these bits, but if not, let PCH Init driver clear the bits.
  1012. **/
  1013. typedef struct {
  1014. UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
  1015. UINT32 MeHrstColdSts : 1; ///< Clear the ME_HRST_COLD_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
  1016. UINT32 MeHrstWarmSts : 1; ///< Clear the ME_HRST_WARM_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
  1017. UINT32 MeHostPowerDn : 1; ///< Clear the ME_HOST_PWRDN bit in the Power and Reset Status (PRSTS) register. <b>0: Disable</b>; 1: Enable.
  1018. UINT32 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
  1019. UINT32 RsvdBits0 : 27;
  1020. } PCH_POWER_RESET_STATUS;
  1021. /**
  1022. This PCH_GBL2HOST_EN specifes enable bits related to the "Convert Global Resets to Host Resets" (G2H) feature
  1023. **/
  1024. typedef union {
  1025. struct {
  1026. UINT32 G2H_FEA : 1; ///< G2H Feature Enable: 0: Disable; <b>1: Enable</b>.
  1027. UINT32 LTRESET : 1; ///< LT RESET G2H Enable: 0: Disable; <b>1: Enable</b>.
  1028. UINT32 PMCGBL : 1; ///< PMC FW-Initiated Global Reset G2H Enable: 0: Disable; <b>1: Enable</b>.
  1029. UINT32 CPUTHRM : 1; ///< CPU Thermal Trip G2H Enable: 0: Disable; <b>1: Enable</b>.
  1030. UINT32 PCHTHRM : 1; ///< PCH Internal Thermal Trip G2H Enable: Disable; <b>1: Enable</b>.
  1031. UINT32 PBO : 1; ///< Power Button Override G2H Enable: 0: Disable; <b>1: Enable</b>.
  1032. UINT32 MEPBO : 1; ///< ME-Initiated Power Button Override G2H: 0: Disable; <b>1: Enable</b>.
  1033. UINT32 MEWDT : 1; ///< ME FW Watchdog Timer G2H Enable: 0: Disable; <b>1: Enable</b>.
  1034. UINT32 MEGBL : 1; ///< ME-Initiated Global Reset G2H Enable: Disable; <b>1: Enable</b>.
  1035. UINT32 CTWDT : 1; ///< CPU Thermal Watchdog Timer G2H Enable: Disable; <b>1: Enable</b>.
  1036. UINT32 PMCWDT : 1; ///< PMC FW Watchdog Timer G2H Enable: Disable; <b>1: Enable</b>.
  1037. UINT32 ME_UERR : 1; ///< ME Uncorrectable Error G2H Enable: Disable; <b>1: Enable</b>.
  1038. UINT32 SYSPWR : 1; ///< SYS_PWROK Failure G2H Enable: Disable; <b>1: Enable</b>.
  1039. UINT32 OCWDT : 1; ///< Over-Clocking WDT G2H Enable: Disable; <b>1: Enable</b>.
  1040. UINT32 PMC_PARERR : 1; ///< PMC Parity Error G2H Enable: 0: Disable; <b>1: Enable</b>.
  1041. UINT32 Reserved : 1; ///< Reserved
  1042. UINT32 IEPBO : 1; ///< IE-Initiated Power Button Override G2H: 0: Disable; <b>1: Enable</b>.
  1043. UINT32 IEWDT : 1; ///< IE FW Watchdog Timer G2H Enable: 0: Disable; <b>1: Enable</b>.
  1044. UINT32 IEGBLN : 1; ///< IE-Initiated Global Reset G2H Enable: 0: Disable; <b>1: Enable</b>.
  1045. UINT32 IE_UERRN : 1; ///< IE Uncorrectable Error G2H Enable: 0: Disable; <b>1: Enable</b>.
  1046. UINT32 ACRU_ERR_2H_EN : 1; ///< AC RU Error G2H Enable: 0: Disable; <b>1: Enable</b>.
  1047. } Bits;
  1048. UINT32 Value;
  1049. } PCH_GBL2HOST_EN;
  1050. /**
  1051. This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events.
  1052. **/
  1053. typedef struct {
  1054. /**
  1055. Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.
  1056. When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN.
  1057. When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. <b>0: Disable</b>; 1: Enable.
  1058. **/
  1059. UINT32 PmeB0S5Dis : 1;
  1060. UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; <b>1: Enable</b>.
  1061. UINT32 Gp27WakeFromDeepSx : 1; ///< @deprecated
  1062. UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to wake from deep Sx. <b>0: Disable</b>; 1: Enable.
  1063. UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
  1064. UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
  1065. UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wake from deep Sx. 0: Disable; <b>1: Enable</b>.
  1066. UINT32 RsvdBits0 : 25;
  1067. } PCH_WAKE_CONFIG;
  1068. typedef enum {
  1069. PchDeepSxPolDisable,
  1070. PchDpS5BatteryEn,
  1071. PchDpS5AlwaysEn,
  1072. PchDpS4S5BatteryEn,
  1073. PchDpS4S5AlwaysEn,
  1074. PchDpS3S4S5BatteryEn,
  1075. PchDpS3S4S5AlwaysEn
  1076. } PCH_DEEP_SX_CONFIG;
  1077. typedef enum {
  1078. PchSlpS360us,
  1079. PchSlpS31ms,
  1080. PchSlpS350ms,
  1081. PchSlpS32s
  1082. } PCH_SLP_S3_MIN_ASSERT;
  1083. typedef enum {
  1084. PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing and Reset Signal Timings table
  1085. PchSlpS41s,
  1086. PchSlpS42s,
  1087. PchSlpS43s,
  1088. PchSlpS44s
  1089. } PCH_SLP_S4_MIN_ASSERT;
  1090. typedef enum {
  1091. PchSlpSus0ms,
  1092. PchSlpSus500ms,
  1093. PchSlpSus1s,
  1094. PchSlpSus4s
  1095. } PCH_SLP_SUS_MIN_ASSERT;
  1096. typedef enum {
  1097. PchSlpA0ms,
  1098. PchSlpA4s,
  1099. PchSlpA98ms,
  1100. PchSlpA2s
  1101. } PCH_SLP_A_MIN_ASSERT;
  1102. typedef enum {
  1103. PchPmGrPfetDur1us,
  1104. PchPmGrPfetDur2us,
  1105. PchPmGrPfetDur5us,
  1106. PchPmGrPfetDur20us
  1107. } PCH_PM_GR_PFET_DUR;
  1108. /**
  1109. The PCH_PM_CONFIG block describes expected miscellaneous power management settings.
  1110. The PowerResetStatusClear field would clear the Power/Reset status bits, please
  1111. set the bits if you want PCH Init driver to clear it, if you want to check the
  1112. status later then clear the bits.
  1113. **/
  1114. typedef struct {
  1115. /**
  1116. Specify which Power/Reset bits need to be cleared by
  1117. the PCH Init Driver.
  1118. Usually platform drivers take care of these bits, but if
  1119. not, let PCH Init driver clear the bits.
  1120. **/
  1121. PCH_POWER_RESET_STATUS PowerResetStatusClear;
  1122. PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy
  1123. PCH_DEEP_SX_CONFIG PchDeepSxPol; ///< Deep Sx Policy. Default is <b>PchDeepSxPolDisable</b>.
  1124. PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert; ///< SLP_S3 Minimum Assertion Width Policy. Default is <b>PchSlpS350ms</b>.
  1125. PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert; ///< SLP_S4 Minimum Assertion Width Policy. Default is <b>PchSlpS44s</b>.
  1126. PCH_SLP_SUS_MIN_ASSERT PchSlpSusMinAssert; ///< SLP_SUS Minimum Assertion Width Policy. Default is <b>PchSlpSus4s</b>.
  1127. PCH_SLP_A_MIN_ASSERT PchSlpAMinAssert; ///< SLP_A Minimum Assertion Width Policy. Default is <b>PchSlpA2s</b>.
  1128. /**
  1129. This member describes whether or not the PCI ClockRun feature of PCH should
  1130. be enabled. <b>0: Disable</b>; 1: Enable
  1131. **/
  1132. UINT32 PciClockRun : 1;
  1133. UINT32 SlpStrchSusUp : 1; ///< <b>0: Disable</b>; 1: Enable SLP_X Stretching After SUS Well Power Up
  1134. /**
  1135. Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; <b>1: Enable</b>.
  1136. Configure On DC PHY Power Diable according to policy SlpLanLowDc.
  1137. When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low.
  1138. This indicates that LAN PHY should be powered off on battery mode.
  1139. This will override the DC_PP_DIS setting by WolEnableOverride.
  1140. **/
  1141. UINT32 SlpLanLowDc : 1;
  1142. /**
  1143. PCH power button override period.
  1144. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s
  1145. <b>Default is 0: 4s</b>
  1146. **/
  1147. UINT32 PwrBtnOverridePeriod : 3;
  1148. /**
  1149. <b>(Test)</b>
  1150. Disable/Enable PCH to CPU enery report feature. <b>0: Disable</b>; 1: Enable.
  1151. Enery Report is must have feature. Wihtout Energy Report, the performance report
  1152. by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted
  1153. in power/performance management algorithm.
  1154. If for some reason PCH energy report is too high, which forces CPU to try to reduce
  1155. its power by throttling, then it could try to disable Energy Report to do first debug.
  1156. This might be due to energy scaling factors are not correct or the LPM settings are not
  1157. kicking in.
  1158. **/
  1159. UINT32 DisableEnergyReport : 1;
  1160. /**
  1161. When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
  1162. When set to Enable, PCH will not pull down AC_PRESENT.
  1163. This setting is ignored when DeepSx is not supported.
  1164. Default is <b>0:Disable</b>
  1165. **/
  1166. UINT32 DisableDsxAcPresentPulldown : 1;
  1167. /**
  1168. <b>(Test)</b>
  1169. When set to true, this bit disallows Host reads to PMC XRAM.
  1170. BIOS must set this bit (to disable and lock the feature) prior to passing control to OS
  1171. 0:Disable, <b>1:Enable</b>
  1172. **/
  1173. UINT32 PmcReadDisable : 1;
  1174. /**
  1175. This determines the type of reset issued during the capsule update process by UpdateCapsule().
  1176. The default is <b>0:S3 Resume</b>, 1:Warm reset.
  1177. **/
  1178. UINT32 CapsuleResetType : 1;
  1179. /**
  1180. Power button native mode disable.
  1181. While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal.
  1182. While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted.
  1183. <b>Default is FALSE.</b>
  1184. **/
  1185. UINT32 DisableNativePowerButton : 1;
  1186. /**
  1187. Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
  1188. When set to one SLP_S0# will be asserted in idle state.
  1189. When set to zero SLP_S0# will not toggle and is always drivern high.
  1190. 0:Disable, <b>1:Enable</b>
  1191. Warning: In SKL PCH VCCPRIM_CORE must NOT be reduced based on SLP_S0# being asserted.
  1192. If a platform is using SLP_S0 to lower PCH voltage the below policy must be disabled.
  1193. **/
  1194. UINT32 SlpS0Enable : 1;
  1195. UINT32 DirtyWarmReset : 1; ///< DirtyWarmReset enable
  1196. UINT32 StallDirtyWarmReset : 1; ///< Stall during DWR
  1197. UINT32 GrPfetDurOnDef : 2; ///< Global Reset PFET duration
  1198. UINT32 Dwr_MeResetPrepDone : 1; ///< ME Reset Prep Done
  1199. UINT32 Dwr_IeResetPrepDone : 1; ///< IE Reset Prep Done
  1200. UINT32 Dwr_BmcRootPort : 8; ///< Root port where BMC is connected to
  1201. UINT32 RsvdBits0 : 6; ///< @todo ADD DESCRIPTION
  1202. PCH_GBL2HOST_EN PchGbl2HostEn;
  1203. /**
  1204. Reset Power Cycle Duration could be customized in the unit of second. Please refer to EDS
  1205. for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where
  1206. <b>0 is default</b>, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds.
  1207. And make sure the setting correct, which never less than the following register.
  1208. - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH
  1209. - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH
  1210. - PWRM_CFG.SLP_A_MIN_ASST_WDTH
  1211. - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH
  1212. **/
  1213. UINT8 PchPwrCycDur;
  1214. /**
  1215. Specifies the Pcie Pll Spread Spectrum Percentage
  1216. The value of this policy is in 1/10th percent units.
  1217. Valid spread range is 0-20. A value of 0xFF is reserved for AUTO.
  1218. A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%
  1219. The default is <b>0xFF: AUTO - No BIOS override</b>.
  1220. **/
  1221. UINT8 PciePllSsc;
  1222. UINT8 Rsvd0[2]; ///< Reserved bytes
  1223. } PCH_PM_CONFIG;
  1224. //
  1225. // ---------------------------- DMI Config -----------------------------
  1226. //
  1227. ///
  1228. /// The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
  1229. ///
  1230. typedef struct {
  1231. /**
  1232. 0: Disable; <b>1: Enable</b> ASPM on PCH side of the DMI Link.
  1233. While DmiAspm is enabled, DMI ASPM will be set to Intel recommended value.
  1234. **/
  1235. UINT32 DmiAspm : 1;
  1236. UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side.
  1237. BOOLEAN DmiStopAndScreamEnable : 1;
  1238. UINT32 DmiLinkDownHangBypass : 1;
  1239. UINT32 Rsvdbits : 29;
  1240. UINT32 Rsvd0[6]; ///< Reserved bytes
  1241. } PCH_DMI_CONFIG;
  1242. //
  1243. // --------------------------- Serial IRQ Config ------------------------------
  1244. //
  1245. typedef enum {
  1246. PchQuietMode,
  1247. PchContinuousMode
  1248. } PCH_SIRQ_MODE;
  1249. ///
  1250. /// Refer to PCH EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode
  1251. ///
  1252. typedef enum {
  1253. PchSfpw4Clk,
  1254. PchSfpw6Clk,
  1255. PchSfpw8Clk
  1256. } PCH_START_FRAME_PULSE;
  1257. ///
  1258. /// The PCH_LPC_SIRQ_CONFIG block describes the expected configuration of the PCH for Serial IRQ.
  1259. ///
  1260. typedef struct {
  1261. UINT32 SirqEnable : 1; ///< Determines if enable Serial IRQ. 0: Disable; <b>1: Enable</b>.
  1262. UINT32 RsvdBits0 : 31; ///< Reserved bits
  1263. PCH_SIRQ_MODE SirqMode; ///< Serial IRQ Mode Select. <b>0: quiet mode</b> 1: continuous mode.
  1264. PCH_START_FRAME_PULSE StartFramePulse; ///< Start Frame Pulse Width. Default is <b>PchSfpw4Clk</b>.
  1265. UINT32 Rsvd0; ///< Reserved bytes
  1266. } PCH_LPC_SIRQ_CONFIG;
  1267. //
  1268. // --------------------------- Port 61h Emulation in SMM ------------------------------
  1269. //
  1270. /**
  1271. This structure is used for the emulation feature for Port61h read. The port is trapped
  1272. and the SMI handler will toggle bit4 according to the handler's internal state.
  1273. **/
  1274. typedef struct {
  1275. UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b> the emulation
  1276. UINT32 RsvdBits0 : 31; ///< Reserved bits
  1277. } PCH_PORT61H_SMM_CONFIG;
  1278. //
  1279. // --------------------- Interrupts Config ------------------------------
  1280. //
  1281. typedef enum {
  1282. PchNoInt, ///< No Interrupt Pin
  1283. PchIntA,
  1284. PchIntB,
  1285. PchIntC,
  1286. PchIntD
  1287. } PCH_INT_PIN;
  1288. ///
  1289. /// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
  1290. ///
  1291. typedef struct {
  1292. UINT8 Device; ///< Device number
  1293. UINT8 Function; ///< Device function
  1294. UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN)
  1295. UINT8 Irq; ///< IRQ to be set for device.
  1296. } PCH_DEVICE_INTERRUPT_CONFIG;
  1297. #define PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
  1298. #define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers in ITSS
  1299. ///
  1300. /// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.
  1301. ///
  1302. typedef struct {
  1303. UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table
  1304. UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4.
  1305. PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings
  1306. UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG]; ///< Array which stores interrupt routing for 8259 controller
  1307. UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is <b>14</b>.
  1308. UINT8 SciIrqSelect; ///< Interrupt select for SCI. Default is <b>9</b>.
  1309. UINT8 TcoIrqSelect; ///< Interrupt select for TCO. Default is <b>9</b>.
  1310. UINT8 TcoIrqEnable; ///< Enable IRQ generation for TCO. <b>0: Disable</b>; 1: Enable.
  1311. UINT8 ShutdownPolicySelect; ///< Shutdown mode 0: PCH will drive INIT#; 1: PCH will drive PLTRST# active
  1312. } PCH_INTERRUPT_CONFIG;
  1313. //
  1314. // --------------------- TraceHub Config ------------------------------
  1315. //
  1316. ///
  1317. /// The PCH_TRACE_HUB_CONFIG block describes TraceHub settings for PCH.
  1318. ///
  1319. typedef struct {
  1320. TRACE_HUB_CONFIG TraceHub;
  1321. UINT32 AetEnableMode : 2;
  1322. UINT32 PchTraceHubHide : 1;
  1323. } PCH_TRACE_HUB_CONFIG;
  1324. //
  1325. // ------------------- CIO2 FLIS registers Config --------------------
  1326. //
  1327. ///
  1328. /// The PCH_SKYCAM_CIO2_FLS_CONFIG block describes SkyCam CIO2 FLS registers configuration.
  1329. ///
  1330. typedef struct {
  1331. UINT32 PortATrimEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port A Clk Trim
  1332. UINT32 PortBTrimEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port B Clk Trim
  1333. UINT32 PortCTrimEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port C Clk Trim
  1334. UINT32 PortDTrimEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port D Clk Trim
  1335. UINT32 PortACtleEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port A Ctle
  1336. UINT32 PortBCtleEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port B Ctle
  1337. UINT32 PortCDCtleEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port C/D Ctle
  1338. UINT32 RsvdBits0 : 25;
  1339. UINT32 PortACtleCapValue : 4; /// Port A Ctle Cap Value
  1340. UINT32 PortBCtleCapValue : 4; /// Port B Ctle Cap Value
  1341. UINT32 PortCDCtleCapValue : 4; /// Port C/D Ctle Cap Value
  1342. UINT32 PortACtleResValue : 5; /// Port A Ctle Res Value
  1343. UINT32 PortBCtleResValue : 5; /// Port B Ctle Res Value
  1344. UINT32 PortCDCtleResValue : 5; /// Port C/D Ctle Res Value
  1345. UINT32 RsvdBits1 : 5;
  1346. UINT32 PortAClkTrimValue : 4; /// Port A Clk Trim Value
  1347. UINT32 PortBClkTrimValue : 4; /// Port B Clk Trim Value
  1348. UINT32 PortCClkTrimValue : 4; /// Port C Clk Trim Value
  1349. UINT32 PortDClkTrimValue : 4; /// Port D Clk Trim Value
  1350. UINT32 PortADataTrimValue : 16; /// Port A Data Trim Value
  1351. UINT32 PortBDataTrimValue : 16; /// Port B Data Trim Value
  1352. UINT32 PortCDDataTrimValue : 16; /// Port C/D Data Trim Value
  1353. } PCH_SKYCAM_CIO2_FLS_CONFIG;
  1354. //
  1355. // ---------------------------- USB Config -----------------------------
  1356. //
  1357. ///
  1358. /// The location of the USB connectors. This information is use to decide eye diagram tuning value for Usb 2.0 motherboard trace.
  1359. ///
  1360. enum PCH_USB_PORT_LOCATION{
  1361. PchUsbPortLocationBackPanel = 0,
  1362. PchUsbPortLocationFrontPanel,
  1363. PchUsbPortLocationDock,
  1364. PchUsbPortLocationMiniPciE,
  1365. PchUsbPortLocationFlex,
  1366. PchUsbPortLocationInternalTopology,
  1367. PchUsbPortLocationSkip,
  1368. PchUsbPortLocationMax
  1369. };
  1370. /**
  1371. This structure configures per USB2 port physical settings.
  1372. It allows to setup the port location and port length, and configures the port strength accordingly.
  1373. **/
  1374. typedef struct {
  1375. UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
  1376. UINT32 RsvdBits0 : 31; ///< Reserved bits
  1377. /**
  1378. These members describe the specific over current pin number of USB 2.0 Port N.
  1379. It is SW's responsibility to ensure that a given port's bit map is set only for
  1380. one OC pin Description. USB2 and USB3 on the same combo Port must use the same
  1381. OC pin (see: USB_OVERCURRENT_PIN).
  1382. **/
  1383. UINT8 OverCurrentPin;
  1384. UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4.
  1385. USB2_PHY_PARAMETERS Afe; ///< USB2 AFE settings
  1386. UINT32 Rsvd1[1]; ///< Reserved bytes
  1387. } PCH_USB20_PORT_CONFIG;
  1388. /**
  1389. This structure describes whether the USB3 Port N of PCH is enabled by platform modules.
  1390. **/
  1391. typedef struct {
  1392. UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
  1393. UINT32 RsvdBits0 : 31; ///< Reserved bits
  1394. /**
  1395. These members describe the specific over current pin number of USB 3.0 Port N.
  1396. It is SW's responsibility to ensure that a given port's bit map is set only for
  1397. one OC pin Description. USB2 and USB3 on the same combo Port must use the same
  1398. OC pin (see: USB_OVERCURRENT_PIN).
  1399. **/
  1400. UINT8 OverCurrentPin;
  1401. UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4
  1402. UINT32 HsioTxDeEmphEnable : 1; ///< Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, <b>0: Disable</b>; 1: Enable.
  1403. /**
  1404. USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5)
  1405. HSIO_TX_DWORD5[21:16]
  1406. <b>Default = 29h</b> (approximately -3.5dB De-Emphasis)
  1407. **/
  1408. UINT32 HsioTxDeEmph : 6;
  1409. UINT32 HsioTxDownscaleAmpEnable : 1; ///< Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, <b>0: Disable</b>; 1: Enable.
  1410. /**
  1411. USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin)
  1412. HSIO_TX_DWORD8[21:16]
  1413. <b>Default = 00h</b>
  1414. **/
  1415. UINT32 HsioTxDownscaleAmp : 6;
  1416. UINT32 RsvdBits1 : 18; ///< Reserved bits
  1417. UINT32 Rsvd1[1]; ///< Reserved bytes
  1418. } PCH_USB30_PORT_CONFIG;
  1419. #define PCH_XHCI_MODE_OFF 0
  1420. #define PCH_XHCI_MODE_ON 1
  1421. /**
  1422. These members describe some settings which are related to the SSIC ports.
  1423. **/
  1424. typedef struct {
  1425. /**
  1426. 0: Disable; <b>1: Enable</b> SSIC support.
  1427. **/
  1428. UINT32 Enable : 1;
  1429. UINT32 RsvdBits1 : 31;
  1430. } PCH_XHCI_SSIC_PORT;
  1431. /**
  1432. These members describe some settings which are related to the SSIC ports.
  1433. **/
  1434. typedef struct {
  1435. PCH_XHCI_SSIC_PORT SsicPort[PCH_XHCI_MAX_SSIC_PORT_COUNT];
  1436. } PCH_SSIC_CONFIG;
  1437. /**
  1438. The PCH_XDCI_CONFIG block describes the configurations
  1439. of the xDCI Usb Device controller.
  1440. **/
  1441. typedef struct {
  1442. /**
  1443. This member describes whether or not the xDCI controller should be enabled.
  1444. 0: Disable; <b>1: Enable</b>.
  1445. **/
  1446. UINT32 Enable : 1;
  1447. UINT32 RsvdBits0 : 31; ///< Reserved bits
  1448. } PCH_XDCI_CONFIG;
  1449. /**
  1450. This member describes the expected configuration of the PCH USB controllers,
  1451. Platform modules may need to refer Setup options, schematic, BIOS specification
  1452. to update this field.
  1453. The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated by referring
  1454. the schematic.
  1455. **/
  1456. typedef struct {
  1457. /**
  1458. This feature intends to reduce the necessary initialization time for USB HC
  1459. and devices on root ports. It is assembled by PCHInit drivers in PEI and DXE phase.
  1460. In PEI phase, the feature resets all USB HCs on PCH bus, including Intel EHCI
  1461. and XHCI. After reset USB HC, continue the system initialization without waiting
  1462. for the USB XHC reset ready. After running to DXE phase, the feature resets
  1463. those USB devices installed on each USB HC root port in parallel, including
  1464. any non USB3 speed devices on XHCI root port if XHCI is enabled.
  1465. For USB3 protocol root port, USB3 speed devices will be advanced to
  1466. enable state if link training succeeds after XHC reset.
  1467. UsbPrecondition = Enable , Force USB Init happen in PEI as part of 2Sec Fast Boot bios optimization.
  1468. UsbPrecondition = Disable, USB Init happen in DXE just like traditionally where it happen.
  1469. Remark: With Precondition Enabled some USB2 devices which are not compliant with usb2 specification
  1470. are not being detected if installed in the system during S4/S5.
  1471. <b>0: Disable</b>; 1: Enable.
  1472. **/
  1473. UINT32 UsbPrecondition : 1;
  1474. /**
  1475. This policy will disable XHCI compliance mode on all ports. Complicance Mode should be default enabled.
  1476. For the platform that support USB Type-C, it can disable Compliance Mode, and enable Compliance Mode when testing.
  1477. <b>0:Disable</b> , 1: Enable
  1478. **/
  1479. UINT32 DisableComplianceMode : 1;
  1480. // Following option is now exposed since there are no restricted registers used.
  1481. UINT32 XhciOcMapEnabled : 1; ///< 0: To disable OC mapping for USB XHCI ports 1: Set Xhci OC registers, Set Xhci OCCDone bit, XHCI Access Control Bit.
  1482. UINT32 XhciWakeOnUsb : 1; ///< 0: To disable Wake on USB connect/Disconnect 1: Enables Wake on USB connect/disconnect event.
  1483. UINT32 XhciDisMSICapability : 1;
  1484. UINT32 RsvdBits0 : 27; ///< Reserved bits
  1485. /**
  1486. These members describe whether the USB2 Port N of PCH is enabled by platform modules.
  1487. Panel and Dock are used to describe the layout of USB port. Panel is only available for Desktop PCH.
  1488. Dock is only available for Mobile LPT.
  1489. **/
  1490. PCH_USB20_PORT_CONFIG PortUsb20[PCH_MAX_USB2_PORTS];
  1491. /**
  1492. These members describe whether the USB3 Port N of PCH is enabled by platform modules.
  1493. **/
  1494. PCH_USB30_PORT_CONFIG PortUsb30[PCH_MAX_USB3_PORTS];
  1495. /**
  1496. This member describes whether or not the xDCI controller should be enabled.
  1497. **/
  1498. PCH_XDCI_CONFIG XdciConfig;
  1499. /**
  1500. These members describe some settings which are related to the SSIC ports.
  1501. **/
  1502. PCH_SSIC_CONFIG SsicConfig;
  1503. UINT32 Rsvd0[6]; ///< Reserved bytes
  1504. } PCH_USB_CONFIG;
  1505. //
  1506. // --------------------------- Flash Protection Range Registers ------------------------------
  1507. //
  1508. /**
  1509. The PCH provides a method for blocking writes and reads to specific ranges
  1510. in the SPI flash when the Protected Ranges are enabled.
  1511. PROTECTED_RANGE is used to specify if flash protection are enabled,
  1512. the write protection enable bit and the read protection enable bit,
  1513. and to specify the upper limit and lower base for each register
  1514. Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine,
  1515. and set the limit and base accordingly.
  1516. **/
  1517. typedef struct {
  1518. UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
  1519. UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
  1520. UINT32 RsvdBits : 30; ///< Reserved
  1521. /**
  1522. The address of the upper limit of protection
  1523. This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
  1524. **/
  1525. UINT16 ProtectedRangeLimit;
  1526. /**
  1527. The address of the upper limit of protection
  1528. This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
  1529. **/
  1530. UINT16 ProtectedRangeBase;
  1531. } PROTECTED_RANGE;
  1532. /**
  1533. PCH Flash Protection Configuration
  1534. **/
  1535. typedef struct {
  1536. PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES];
  1537. } PCH_FLASH_PROTECTION_CONFIG;
  1538. //
  1539. // --------------------- WatchDog (WDT) Configuration ------------------------------
  1540. //
  1541. /**
  1542. This policy clears status bits and disable watchdog, then lock the
  1543. WDT registers.
  1544. while WDT is designed to be disabled and locked by Policy,
  1545. bios should not enable WDT by WDT PPI. In such case, bios shows the
  1546. warning message but not disable and lock WDT register to make sure
  1547. WDT event trigger correctly.
  1548. **/
  1549. typedef struct {
  1550. UINT32 DisableAndLock : 1; ///< <b>(Test)</b> Set 1 to clear WDT status, then disable and lock WDT registers. <b>0: Disable</b>; 1: Enable.
  1551. UINT32 RsvdBits : 31;
  1552. } PCH_WDT_CONFIG;
  1553. //
  1554. // --------------------- P2SB Configuration ------------------------------
  1555. //
  1556. /**
  1557. This structure contains the policies which are related to P2SB device.
  1558. **/
  1559. typedef struct {
  1560. /**
  1561. <b>(Test)</b>
  1562. This unlock the SBI lock bit to allow SBI after post time. <b>0: Disable</b>; 1: Enable.
  1563. NOTE: Do not set this policy "SbiUnlock" unless necessary.
  1564. **/
  1565. UINT32 SbiUnlock : 1;
  1566. /**
  1567. <b>(Test)</b>
  1568. The PSF registers will be locked before 3rd party code execution.
  1569. This policy unlock the PSF space. <b>0: Disable</b>; 1: Enable.
  1570. NOTE: Do not set this policy "PsfUnlock" unless necessary.
  1571. **/
  1572. UINT32 PsfUnlock : 1;
  1573. /**
  1574. <b>Debug</b>
  1575. The P2SB PCIe device will be hidden at end of PEI stage.
  1576. This policy reveal P2SB PCIe device at end of EXE. <b>0: Disable (hidden)</b>; 1: Enable (visible).
  1577. NOTE: Do not set this policy "P2SbReveal" unless necessary.
  1578. **/
  1579. UINT32 P2SbReveal : 1;
  1580. UINT32 RsvdBits : 29;
  1581. } PCH_P2SB_CONFIG;
  1582. //
  1583. // --------------------- DCI Configuration ------------------------------
  1584. //
  1585. /**
  1586. This structure contains the policies which are related to Direct Connection Interface (DCI).
  1587. **/
  1588. typedef struct {
  1589. /**
  1590. <b>(Test)</b> DCI enable (HDCIEN bit)
  1591. when Enabled, allow DCI to be enabled. When Disabled, the Host control is not enabling DCI feature.
  1592. BIOS provides policy to enable or disable DCI, and user would be able to use BIOS option to change this policy.
  1593. The user changing the setting from disable to enable, is taken as a consent from the user to enable this DCI feature.
  1594. <b>0:Disabled</b>; 1:Enabled
  1595. **/
  1596. UINT32 DciEn : 1;
  1597. /**
  1598. <b>(Test)</b> When set to Auto detect mode, it detects DCI being connected during BIOS post time and enable DCI.
  1599. Else it disable DCI. This policy only apply when DciEn is disabled.
  1600. NOTE: this policy should not be visible to end customer.
  1601. 0: Disable AUTO mode, <b>1: Enable AUTO mode</b>
  1602. **/
  1603. UINT32 DciAutoDetect : 1;
  1604. UINT32 RsvdBits : 30; ///< Reserved bits
  1605. } PCH_DCI_CONFIG;
  1606. //
  1607. // --------------------- LPC Configuration ------------------------------
  1608. //
  1609. /**
  1610. This structure contains the policies which are related to LPC.
  1611. **/
  1612. typedef struct {
  1613. /**
  1614. Enhance the port 8xh decoding.
  1615. Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h.
  1616. @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00.
  1617. 0: Disable, <b>1: Enable</b>
  1618. **/
  1619. UINT32 EnhancePort8xhDecoding : 1;
  1620. UINT32 RsvdBits : 30; ///< Reserved bits
  1621. } PCH_LPC_CONFIG;
  1622. //
  1623. // --------------------- SPI Configuration ------------------------------
  1624. //
  1625. /**
  1626. This structure contains the policies which are related to SPI.
  1627. **/
  1628. typedef struct {
  1629. /**
  1630. Force to show SPI controller.
  1631. <b>0: FALSE</b>, 1: TRUE
  1632. NOTE: For Windows OS, it MUST BE false. It's optional for other OSs.
  1633. **/
  1634. UINT32 ShowSpiController : 1;
  1635. UINT32 RsvdBits : 31; ///< Reserved bits
  1636. } PCH_SPI_CONFIG;
  1637. //
  1638. // ---------------------------------------------------------------------
  1639. //
  1640. /**
  1641. PCH Policy revision number
  1642. Any backwards compatible changes to this structure will result in an update in the revision number
  1643. **/
  1644. #define PCH_POLICY_REVISION 15
  1645. /**
  1646. The PCH Policy allows the platform code to publish a set of
  1647. configuration information that the PCH drivers will use to configure the PCH hardware.
  1648. The Revision field is used to accommodate backward compatible changes to the PPI/protocol.
  1649. The Revision should be initialized to PCH_POLICY_REVISION_X
  1650. by the PPI producer.
  1651. The BusNumber field is used for platform to assign Bus number with multiple instances.
  1652. All reserved/unused fields must be initialized with zeros.
  1653. **/
  1654. struct _PCH_POLICY {
  1655. /**
  1656. This member specifies the revision of the PCH policy PPI. This field is used to
  1657. indicate backwards compatible changes to the protocol. Platform code that produces
  1658. this PPI must fill with the correct revision value for the PCH reference code
  1659. to correctly interpret the content of the PPI fields.
  1660. Revision 1: Original version
  1661. - Add DciAutoDetect policy in PCH_GENERAL_CONFIG.
  1662. - Add SbiUnlock policy in PCH_P2SB_CONFIG.
  1663. - Add the following policies in PCH_ISH_CONFIG:
  1664. - SpiGpioAssign
  1665. - Uart0GpioAssign
  1666. - Uart1GpioAssign
  1667. - I2c0GpioAssign
  1668. - I2c1GpioAssign
  1669. - I2c2GpioAssign
  1670. - Gp0GpioAssign
  1671. - Gp1GpioAssign
  1672. - Gp2GpioAssign
  1673. - Gp3GpioAssign
  1674. - Gp4GpioAssign
  1675. - Gp5GpioAssign
  1676. - Gp6GpioAssign
  1677. - Gp7GpioAssign
  1678. - Add ClkReqSupported and ClkReqDetect in PCH_PCIE_ROOT_PORT_CONFIG.
  1679. - Add the following in PCH_SKYCAM_CIO2_CONFIG
  1680. - SkyCamPortATermOvrEnable
  1681. - SkyCamPortBTermOvrEnable
  1682. - SkyCamPortCTermOvrEnable
  1683. - SkyCamPortDTermOvrEnable
  1684. - Add UartHwFlowCtrl in PCH_SERIAL_IO
  1685. - Move DciEn and DciAutoDetect to PCH_DCI_CONFIG
  1686. Revision 2: Updated version
  1687. - Add Enable policy in PCH_SSIC_CONFIG
  1688. - Deprecated Target Debugger option of EnableMode in PCH_TRACE_HUB_CONFIG
  1689. - Deprecated the following policies in PCH_TRACE_HUB_CONFIG
  1690. - MemReg0WrapEnable
  1691. - MemReg1WrapEnable
  1692. - TraceDestination
  1693. - PtiMode
  1694. - PtiSpeed
  1695. - PtiTraining
  1696. - Deprecated the Usb3PinsTermination and ManualModeUsb30PerPinEnable in PCH_XHCI_CONFIG
  1697. - Redefine the Enable policy in PCH_HPET_CONFIG
  1698. - Add EnhancePort8xhDecoding in PCH_LPC_CONFIG
  1699. - Add PsfUnlock in PCH_P2SB_CONFIG
  1700. - Add AllowNoLtrIccPllShutdown in PCH_PCIE_CONFIG
  1701. - Add PdtUnlock in PCH_ISH_CONFIG
  1702. - Remove PwrmBase from policy since the base address is predefined.
  1703. - Add DspEndpointDmic, DspEndpointBluetooth, DspEndpointI2s in PCH_HDAUDIO_CONFIG
  1704. - Add Gen3EqPh3Method abd EqPh3LaneParam in PCH_PCIE_ROOT_PORT_CONFIG/PCH_PCIE_CONFIG
  1705. - Remove SlotImplemented and PmeInterrupt from PCH_PCIE_ROOT_PORT_CONFIG
  1706. Revision 3: Updated version
  1707. - Add PwrBtnOverridePeriod policy in PCH_PM_CONFIG
  1708. - Add USB20_AFE in PCH_USB20_PORT_CONFIG
  1709. - Add ClkReqSupported in PCH_LAN_CONFIG
  1710. Revision 4: Updated version
  1711. - Add DeviceResetPad and DeviceResetPadActiveHigh in PCH_PCIE_ROOT_PORT_CONFIG
  1712. Revision 5: Updated version
  1713. - Deprecated ScsSdioMode in PCH_SCS_CONFIG
  1714. - Deprecated PchScsSdioMode (PCH_SCS_DEV_SD_MODE enum) for ScsSdSwitch in PCH_SCS_CONFIG
  1715. - Add HSIO RX and TX EQ policy for PCIe and SATA
  1716. - Add ComplianceTestMode in PCH_PCIE_CONFIG
  1717. Revision 6: Updated version
  1718. - Add DisableEnergyReport in PCH_PM_CONFIG
  1719. Revision 7: Updated version
  1720. - Deprecated Enabled as Acpi device option of DeviceEnable in PCH_SKYCAM_CIO2_CONFIG
  1721. - Add PCH_SKYCAM_CIO2_FLS_CONFIG with the following elements:
  1722. - PortACtleEnable
  1723. - PortBCtleEnable
  1724. - PortCCtleEnable
  1725. - PortDCtleEnable
  1726. - PortACtleCapValue
  1727. - PortBCtleCapValue
  1728. - PortCCtleCapValue
  1729. - PortDCtleCapValue
  1730. - PortACtleResValue
  1731. - PortBCtleResValue
  1732. - PortCCtleResValue
  1733. - PortDCtleResValue
  1734. - PortATrimEnable
  1735. - PortBTrimEnable
  1736. - PortCTrimEnable
  1737. - PortDTrimEnable
  1738. - PortADataTrimValue
  1739. - PortBDataTrimValue
  1740. - PortCDataTrimValue
  1741. - PortDDataTrimValue
  1742. - PortAClkTrimValue
  1743. - PortBClkTrimValue
  1744. - PortCClkTrimValue
  1745. - PortDClkTrimValue
  1746. - Rename and reorder the policies for better understanding.
  1747. - HsioTxOutDownscaleAmpAd3GbsEnable to HsioTxGen1DownscaleAmpEnable
  1748. - HsioTxOutDownscaleAmpAd6GbsEnable to HsioTxGen2DownscaleAmpEnable
  1749. - HsioTxOutDownscaleAmpAd3Gbs to HsioTxGen2DownscaleAmp
  1750. - HsioTxOutDownscaleAmpAd6Gbs to HsioTxGen2DownscaleAmp
  1751. - Update SerialIo DevMode default to PCI mode.
  1752. Revision 8: Updated version
  1753. - Deprecate GP27WakeFromDeepSx and add LanWakeFromDeepSx to align EDS naming
  1754. - Add ShowSpiController policy and PCH_SPI_CONFIG.
  1755. - Add DspUaaCompliance in PCH_HDAUDIO_CONFIG
  1756. - Add PchPcieEqHardware support in PCH_PCIE_EQ_METHOD
  1757. Revision 9: Updated version
  1758. - Add DebugUartNumber and EnableDebugUartAfterPost in PCH_SERIAL_IO_CONFIG
  1759. - Add DetectTimeoutMs in PCH_PCIE_CONFIG
  1760. - Add PciePllSsc in PCH_PM_CONFIG
  1761. Revision 10: Updated version
  1762. - Add HsioTxDeEmph in PCH_USB30_PORT_CONFIG
  1763. - Add HsioTxDownscaleAmp in PCH_USB30_PORT_CONFIG
  1764. - Add HsioTxDeEmphEnable in PCH_USB30_PORT_CONFIG
  1765. - Add HsioTxDownscaleAmpEnable in PCH_USB30_PORT_CONFIG
  1766. - Deprecated PCH_SATA_PORT_CONFIG.HsioRxEqBoostMagAdEnable
  1767. - Deprecated PCH_SATA_PORT_CONFIG.HsioRxEqBoostMagAd
  1768. - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen1DownscaleAmpEnable
  1769. - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen1DownscaleAmp
  1770. - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen2DownscaleAmpEnable
  1771. - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen2DownscaleAmp
  1772. - Add PCH_HSIO_SATA_CONFIG HsioSataConfig in PCH_POLICY
  1773. - Add HsioRxGen1EqBoostMagEnable in PCH_HSIO_SATA_PORT_LANE
  1774. - Add HsioRxGen1EqBoostMag in PCH_HSIO_SATA_PORT_LANE
  1775. - Add HsioRxGen2EqBoostMagEnable in PCH_HSIO_SATA_PORT_LANE
  1776. - Add HsioRxGen2EqBoostMag in PCH_HSIO_SATA_PORT_LANE
  1777. - Add HsioTxGen1DeEmphEnable in PCH_HSIO_SATA_PORT_LANE
  1778. - Add HsioTxGen1DeEmph in PCH_HSIO_SATA_PORT_LANE
  1779. - Add HsioTxGen2DeEmphEnable in PCH_HSIO_SATA_PORT_LANE
  1780. - Add HsioTxGen2DeEmph in PCH_HSIO_SATA_PORT_LANE
  1781. - Add HsioTxGen3DeEmphEnable in PCH_HSIO_SATA_PORT_LANE
  1782. - Add HsioTxGen3DeEmph in PCH_HSIO_SATA_PORT_LANE
  1783. - Add HsioTxGen3DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE
  1784. - Add HsioTxGen3DownscaleAmp in PCH_HSIO_SATA_PORT_LANE
  1785. - Add PCH_HSIO_PCIE_CONFIG HsioPcieConfig in PCH_POLICY
  1786. - Deprecated PCH_PCIE_ROOT_PORT_CONFIG.HsioRxSetCtleEnable
  1787. - Deprecated PCH_PCIE_ROOT_PORT_CONFIG.HsioRxSetCtle
  1788. - Add HsioRxSetCtleEnable in PCH_HSIO_PCIE_LANE_CONFIG
  1789. - Add HsioRxSetCtle in PCH_HSIO_PCIE_LANE_CONFIG
  1790. - Add HsioTxGen1DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_CONFIG
  1791. - Add HsioTxGen1DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG
  1792. - Add HsioTxGen2DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_CONFIG
  1793. - Add HsioTxGen2DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG
  1794. - Add HsioTxGen3DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_CONFIG
  1795. - Add HsioTxGen3DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG
  1796. - Add HsioTxGen1DeEmphEnable in PCH_HSIO_PCIE_LANE_CONFIG
  1797. - Add HsioTxGen1DeEmph in PCH_HSIO_PCIE_LANE_CONFIG
  1798. - Add HsioTxGen2DeEmph3p5Enable in PCH_HSIO_PCIE_LANE_CONFIG
  1799. - Add HsioTxGen2DeEmph3p5 in PCH_HSIO_PCIE_LANE_CONFIG
  1800. - Add HsioTxGen2DeEmph6p0Enable in PCH_HSIO_PCIE_LANE_CONFIG
  1801. - Add HsioTxGen2DeEmph6p0 in PCH_HSIO_PCIE_LANE_CONFIG
  1802. - Add DisableDsxAcPresentPulldown in PCH_PM_CONFIG
  1803. - Add DynamicPowerGating in PCH_SMBUS_CONFIG
  1804. - Add ZpOdd in PCH_SATA_PORT_CONFIG
  1805. - Add Uptp and Dptp in PCH_PCIE_ROOT_PORT_CONFIG
  1806. - Add PCH_PCIE_CONFIG2 PcieConfig2 in PCH_POLICY
  1807. Revision 11: Updated version
  1808. - Add DisableComplianceMode in PCH_USB_CONFIG
  1809. Revision 12: Updated version
  1810. - Add PmcReadDisable in PCH_PM_CONFIG
  1811. - Add CapsuleResetType in PCH_PM_CONFIG
  1812. - Add RpFunctionSwap in PCH_PCIE_CONFIG
  1813. Revision 13: Update version
  1814. - Add DisableNativePowerButton in PCH_PM_CONFIG
  1815. - Add MaxPayload in PCH_PCIE_ROOT_PORT_CONFIG
  1816. - Add IDispCodecDisconnect in PCH_HDAUDIO_CONFIG
  1817. Revision 13a: Server updates
  1818. - Add HsioIcfgAdjLimitLoEnable
  1819. - Add HsioIcfgAdjLimitLo
  1820. - Add HsioSampOffstEvenErrSpEnable
  1821. - Add HsioSampOffstEvenErrSp
  1822. - Add HsioRemainingSamplerOffEnable
  1823. - Add HsioRemainingSamplerOff
  1824. - Add HsioVgaGainCal
  1825. in PCH_HSIO_PCIE_LANE_CONFIG
  1826. **/
  1827. UINT8 Revision;
  1828. UINT8 Port80Route; ///< Control where the Port 80h cycles are sent, <b>0: LPC</b>; 1: PCI.
  1829. UINT16 AcpiBase; ///< Power management I/O base address. Default is <b>0x1800</b>.
  1830. UINT32 Rsvd;
  1831. ///
  1832. /// PCH General configuration
  1833. ///
  1834. PCH_GENERAL_CONFIG PchConfig;
  1835. ///
  1836. /// This member describes PCI Express controller's related configuration.
  1837. ///
  1838. PCH_PCIE_CONFIG PcieConfig;
  1839. /**
  1840. SATA controller's related configuration.
  1841. SATA configuration that decides which Mode the SATA controller should operate in
  1842. and whether PCH SATA TEST mode is enabled.
  1843. **/
  1844. PCH_SATA_CONFIG SataConfig;
  1845. ///
  1846. /// This member describes USB controller's related configuration.
  1847. ///
  1848. PCH_USB_CONFIG UsbConfig;
  1849. /**
  1850. This member describes IOAPIC related configuration.
  1851. Determines IO APIC ID and IO APIC Range.
  1852. **/
  1853. PCH_IOAPIC_CONFIG IoApicConfig;
  1854. ///
  1855. /// This member describes HPET related configuration.
  1856. ///
  1857. PCH_HPET_CONFIG HpetConfig;
  1858. ///
  1859. /// This member describes the Intel HD Audio (Azalia) related configuration.
  1860. ///
  1861. PCH_HDAUDIO_CONFIG HdAudioConfig;
  1862. ///
  1863. /// LAN controller settings
  1864. ///
  1865. PCH_LAN_CONFIG LanConfig;
  1866. ///
  1867. /// This member describes SMBus related configuration.
  1868. ///
  1869. PCH_SMBUS_CONFIG SmbusConfig;
  1870. ///
  1871. /// This member describes LockDown related configuration.
  1872. ///
  1873. PCH_LOCK_DOWN_CONFIG LockDownConfig;
  1874. ///
  1875. /// This member describes Thermal related configuration.
  1876. ///
  1877. PCH_THERMAL_CONFIG ThermalConfig;
  1878. ///
  1879. /// This member describes miscellaneous platform power management configurations.
  1880. ///
  1881. PCH_PM_CONFIG PmConfig;
  1882. ///
  1883. /// This member describes DMI related configuration.
  1884. ///
  1885. PCH_DMI_CONFIG DmiConfig;
  1886. ///
  1887. /// This member describes the expected configuration of the PCH for Serial IRQ.
  1888. ///
  1889. PCH_LPC_SIRQ_CONFIG SerialIrqConfig;
  1890. ///
  1891. /// This member describes interrupt settings for PCH.
  1892. ///
  1893. PCH_INTERRUPT_CONFIG PchInterruptConfig;
  1894. ///
  1895. /// This member describes TraceHub settings for PCH.
  1896. ///
  1897. PCH_TRACE_HUB_CONFIG PchTraceHubConfig;
  1898. ///
  1899. /// This member describes the enabling of emulation for port 61h
  1900. ///
  1901. PCH_PORT61H_SMM_CONFIG Port61hSmmConfig;
  1902. ///
  1903. /// This member describes the Flash Protection related configuration
  1904. ///
  1905. PCH_FLASH_PROTECTION_CONFIG FlashProtectConfig;
  1906. ///
  1907. /// This member describes the sSata related configuration
  1908. ///
  1909. PCH_SATA_CONFIG sSataConfig;
  1910. ///
  1911. /// This member contains WDT enable configuration.
  1912. ///
  1913. PCH_WDT_CONFIG WdtConfig;
  1914. ///
  1915. /// This member contains P2SB configuration.
  1916. ///
  1917. PCH_P2SB_CONFIG P2sbConfig;
  1918. ///
  1919. /// This member contains DCI configuration.
  1920. ///
  1921. PCH_DCI_CONFIG DciConfig;
  1922. ///
  1923. /// Platform specific common policies that used by several silicon components.
  1924. ///
  1925. ///
  1926. /// Temp Bus Number range available to be assigned to each root port and its downstream
  1927. /// devices for initialization of these devices before PCI Bus enumeration.
  1928. ///
  1929. UINT8 TempPciBusMin;
  1930. UINT8 TempPciBusMax;
  1931. ///
  1932. /// Temporary Memory Base Address for PCI devices to be used to initialize MMIO registers.
  1933. /// Minimum size is 2MB bytes
  1934. ///
  1935. UINT32 TempMemBaseAddr;
  1936. ///
  1937. /// This member contains LPC configuration.
  1938. ///
  1939. PCH_LPC_CONFIG LpcConfig;
  1940. ///
  1941. /// This member describes SkyCam CIO2 FLS registers configuration.
  1942. ///
  1943. PCH_SKYCAM_CIO2_FLS_CONFIG PchCio2FlsConfig;
  1944. ///
  1945. /// This member contains SPI configuration.
  1946. ///
  1947. PCH_SPI_CONFIG SpiConfig;
  1948. ///
  1949. /// This member describes HSIO settings for SATA controller
  1950. ///
  1951. PCH_HSIO_SATA_CONFIG HsioSataConfig;
  1952. ///
  1953. /// This member describes HSIO settings for second SATA controller
  1954. ///
  1955. PCH_HSIO_SATA_CONFIG HsiosSataConfig;
  1956. ///
  1957. /// This member describes HSIO settings for PCIe controller
  1958. ///
  1959. PCH_HSIO_PCIE_CONFIG HsioPcieConfig;
  1960. ///
  1961. /// This member describes HSIO settings for FIA WM20 PCIe
  1962. ///
  1963. PCH_HSIO_PCIE_WM20_CONFIG HsioPcieConfigFIAWM20;
  1964. ///
  1965. /// This is the extension of PCIE CONFIG
  1966. ///
  1967. PCH_PCIE_CONFIG2 PcieConfig2;
  1968. PCH_ADR_CONFIG AdrConfig;
  1969. };
  1970. #pragma pack (pop)
  1971. #endif // _PCH_POLICY_COMMON_H_