KtiHost.h 14 KB

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  1. /** @file
  2. @copyright
  3. Copyright 2004 - 2021 Intel Corporation. <BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. // Definition Flag:
  7. // 1. KTI_SW_SIMULATION -> run with KTIRC Simulation
  8. // 2. IA32 -> run with IA32 mode
  9. #ifndef _KTI_HOST_H_
  10. #define _KTI_HOST_H_
  11. #include "DataTypes.h"
  12. #include "PlatformHost.h"
  13. #include <Upi/KtiSi.h>
  14. #include <Upi/KtiDisc.h>
  15. #include "MemHostChipCommon.h"
  16. #pragma pack(1)
  17. /*********************************************************
  18. KTIRC Host Structure Related
  19. *********************************************************/
  20. typedef enum {
  21. KTI_LINK0 = 0x0,
  22. KTI_LINK1,
  23. KTI_LINK2,
  24. KTI_LINK3,
  25. KTI_LINK4,
  26. KTI_LINK5
  27. } KTI_LOGIC_LINK;
  28. typedef struct {
  29. UINT8 Reserved1;
  30. UINT8 Reserved2;
  31. UINT8 Reserved3;
  32. UINT8 Reserved4;
  33. UINT8 Reserved5;
  34. UINT8 Reserved6;
  35. UINT8 Reserved7;
  36. UINT8 Reserved8;
  37. UINT8 Reserved9;
  38. UINT8 Reserved10;
  39. UINT8 Reserved11;
  40. UINT8 Reserved12;
  41. UINT8 Reserved13;
  42. UINT8 Reserved14;
  43. UINT8 Reserved15;
  44. UINT8 Reserved16;
  45. UINT8 Reserved17;
  46. UINT8 Reserved18;
  47. UINT8 Reserved19;
  48. UINT8 Reserved20;
  49. UINT8 Reserved21;
  50. UINT8 Reserved22;
  51. UINT8 Reserved23;
  52. UINT8 Reserved24;
  53. UINT8 Reserved25;
  54. UINT8 Reserved26;
  55. UINT8 Reserved27;
  56. UINT8 Reserved28;
  57. UINT8 Reserved29;
  58. UINT8 Reserved30;
  59. UINT8 Reserved31;
  60. UINT8 Reserved32;
  61. UINT8 Reserved33;
  62. UINT8 Reserved34;
  63. UINT8 Reserved35;
  64. UINT8 Reserved36;
  65. UINT8 Reserved37;
  66. UINT32 Reserved38;
  67. UINT8 Reserved39;
  68. UINT8 Reserved40;
  69. } KTI_RESERVED_3;
  70. typedef struct {
  71. UINT32 Reserved1:2;
  72. UINT32 Reserved2:2;
  73. UINT32 Reserved3:2;
  74. UINT32 Rsvd1 : 26;
  75. } KTI_RESERVED_1;
  76. typedef struct {
  77. UINT8 Reserved4 : 2;
  78. UINT8 Rsvd1 : 6;
  79. } KTI_RESERVED_2;
  80. typedef struct {
  81. KTI_RESERVED_1 Link[MAX_FW_KTI_PORTS];
  82. KTI_RESERVED_2 Phy[MAX_FW_KTI_PORTS];
  83. } KTI_RESERVED_4;
  84. /**
  85. Per Lane PHY Configuration
  86. These PHY settings are system dependent. Every socket/link/freq requires an instance of this structure.
  87. **/
  88. typedef struct {
  89. UINT8 SocketID; ///< Socket ID
  90. UINT8 AllLanesUseSameTxeq; ///< Use same TXEQ on all lanes
  91. UINT8 Freq; ///< The Link Speed these TXEQ settings should be used for
  92. UINT32 Link; ///< Port Number
  93. UINT32 TXEQL[20]; ///< TXEQ Settings
  94. UINT32 CTLEPEAK[5]; ///< CTLE Peaking Settings
  95. } PER_LANE_EPARAM_LINK_INFO;
  96. /**
  97. All Lanes PHY Configuration
  98. This is for full speed mode, all lanes have the same TXEQ setting
  99. **/
  100. typedef struct {
  101. UINT8 SocketID; ///< Socket ID
  102. UINT8 Freq; ///< The Link Speed these TXEQ settings should be used for
  103. UINT32 Link; ///< Port Number
  104. UINT32 AllLanesTXEQ; ///< TXEQ Setting
  105. UINT8 CTLEPEAK; ///< CTLE Peaking Setting
  106. } ALL_LANES_EPARAM_LINK_INFO;
  107. #define ADAPTIVE_CTLE 0x3f
  108. typedef enum {
  109. TYPE_UBOX = 0,
  110. TYPE_UBOX_IIO,
  111. TYPE_MCP,
  112. TYPE_FPGA,
  113. TYPE_HFI,
  114. TYPE_NAC,
  115. TYPE_GRAPHICS,
  116. TYPE_DINO,
  117. TYPE_RESERVED,
  118. TYPE_DISABLED, // This item must be prior to stack specific disable types
  119. TYPE_UBOX_IIO_DIS,
  120. TYPE_MCP_DIS,
  121. TYPE_FPGA_DIS,
  122. TYPE_HFI_DIS,
  123. TYPE_NAC_DIS,
  124. TYPE_GRAPHICS_DIS,
  125. TYPE_DINO_DIS,
  126. TYPE_RESERVED_DIS,
  127. TYPE_NONE
  128. } STACK_TYPE;
  129. //
  130. // Link layer settings, per link
  131. //
  132. typedef struct {
  133. UINT8 KtiPortDisable:1; // TRUE - Port disabled; FALSE- Port enabled (default)
  134. UINT8 KtiLinkVnaOverride:7; // Numeric value 0x00-0x7f
  135. UINT8 Rsvd:8;
  136. } KTI_CPU_LINK_SETTING;
  137. //
  138. // Phy general setting, per link
  139. //
  140. typedef struct {
  141. UINT32 KtiLinkSpeed:3;
  142. UINT32 Rsvd:29;
  143. } KTI_CPU_PHY_SETTING;
  144. //
  145. // Per CPU setting
  146. //
  147. typedef struct {
  148. KTI_CPU_LINK_SETTING Link[MAX_FW_KTI_PORTS];
  149. KTI_CPU_PHY_SETTING Phy[MAX_FW_KTI_PORTS];
  150. } KTI_CPU_SETTING;
  151. /**
  152. KTIRC input structure
  153. **/
  154. typedef struct {
  155. //
  156. // Protocol layer and other general options; note that "Auto" is provided only options whose value will change depending
  157. // on the topology, not for all options.
  158. //
  159. /**
  160. Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO.
  161. Value 0 indicates, that CPU is not relevant for the system. If resource is
  162. requested for an CPU that is not currently populated, KTIRC will assume
  163. that the ratio is 0 for that CPU and won't allocate any resources for it.
  164. If resource is not requested for a CPU that is populated, KTIRC will force
  165. the ratio for that CPU to 1.
  166. **/
  167. UINT8 BusRatio[MAX_SOCKET];
  168. UINT8 D2KCreditConfig; ///< 1 - Min, 2 - Med (Default), 3- Max
  169. UINT8 SnoopThrottleConfig; ///< 0 - Disabled (Default), 1 - Min, 2 - Med, 3- Max
  170. UINT8 SnoopAllCores; ///< 0 - Disabled, 1 - Enabled, 2 - Auto
  171. UINT8 LegacyVgaSoc; ///< Socket that claims the legacy VGA range; valid values are 0-7; 0 is default.
  172. UINT8 LegacyVgaStack; ///< Stack that claims the legacy VGA range; valid values are 0-3; 0 is default.
  173. UINT8 ColdResetRequestStart; ///< @deprecated Reserved.
  174. UINT8 P2pRelaxedOrdering; ///< 0 - Disable(default) 1 - Enable
  175. UINT8 DebugPrintLevel; ///< Bit 0 - Fatal, Bit1 - Warning, Bit2 - Info Summary; Bit 3 - Info detailed. 1 - Enable; 0 - Disable
  176. UINT8 SncEn; ///< 0 - Disable, (default) 1 - Enable
  177. UINT8 UmaClustering; ///< 0 - Disable, 2 - 2Clusters UMA, 4 - 4Clusters UMA
  178. UINT8 IoDcMode; ///< 0 - Disable IODC, 1 - AUTO (default), 2 - IODC_EN_REM_INVITOM_PUSH, 3 - IODC_EN_REM_INVITOM_ALLOCFLOW
  179. ///< 4 - IODC_EN_REM_INVITOM_ALLOC_NONALLOC, 5 - IODC_EN_REM_INVITOM_AND_WCILF
  180. UINT8 DegradePrecedence; ///< Use DEGRADE_PRECEDENCE definition; TOPOLOGY_PRECEDENCE is default
  181. UINT8 Degrade4SPreference; ///< 4S1LFullConnect topology is default; another option is 4S2LRing topology.
  182. UINT8 DirectoryModeEn; ///< 0 - Disable; 1 - Enable (default)
  183. UINT8 XptPrefetchEn; ///< Xpt Prefetch : 1 - Enable; 0 - Disable; 2 - Auto (default)
  184. UINT8 KtiPrefetchEn; ///< Kti Prefetch : 1 - Enable; 0 - Disable; 2 - Auto (default)
  185. UINT8 XptRemotePrefetchEn; ///< Xpt Remote Prefetch : 1 - Enable; 0 - Disable; 2 - Auto (default) (ICX only)
  186. UINT8 RdCurForXptPrefetchEn; ///< RdCur for XPT Prefetch : 0 - Disable, 1 - Enable, 2- Auto (default)
  187. UINT8 KtiFpgaEnable[MAX_SOCKET]; ///< Indicate if should enable Fpga device found in this socket : 0 - Disable, 1 - Enable, 2- Auto
  188. UINT8 DdrtQosMode; ///< DDRT QoS Feature: 0 - Disable (default), 1 - M2M QoS Enable, Cha QoS Disable
  189. ///< 2 - M2M QoS Enable, Cha QoS Enable
  190. //
  191. // Phy/Link Layer Options (System-wide and per socket)
  192. //
  193. UINT8 KtiLinkSpeedMode; ///< Link speed mode selection; 0 - Slow Speed; 1- Full Speed (default)
  194. UINT8 KtiLinkSpeed; ///< Use KTI_LINKSPEED definition
  195. UINT8 KtiAdaptationEn; ///< 0 - Disable, 1 - Enable
  196. UINT8 KtiAdaptationSpeed; ///< Use KTI_LINK_SPEED definition; MAX_KTI_LINK_SPEED - Auto (i.e BIOS choosen speed)
  197. UINT8 KtiLinkL0pEn; ///< 0 - Disable, 1 - Enable, 2- Auto (default)
  198. UINT8 KtiLinkL1En; ///< 0 - Disable, 1 - Enable, 2- Auto (default)
  199. UINT8 KtiFailoverEn; ///< 0 - Disable, 1 - Enable, 2- Auto (default)
  200. UINT8 KtiLbEn; ///< 0 - Disable(default), 1 - Enable
  201. UINT8 KtiCrcMode; ///< CRC_MODE_16BIT, CRC_MODE_ROLLING_32BIT, CRC_MODE_AUTO or CRC_MODE_PER_LINK
  202. UINT8 KtiCpuSktHotPlugEn; ///< 0 - Disable (default), 1 - Enable
  203. UINT8 KtiCpuSktHotPlugTopology; ///< 0 - 4S Topology (default), 1 - 8S Topology
  204. UINT8 KtiSkuMismatchCheck; ///< 0 - No, 1 - Yes (default)
  205. UINT8 IrqThreshold; ///< IRQ Threshold setting
  206. UINT8 TorThresLoctoremNorm; ///< TOR threshold - Loctorem threshold normal
  207. UINT8 TorThresLoctoremEmpty; ///< TOR threshold - Loctorem threshold empty
  208. UINT8 MbeBwCal; ///< 0 - Linear, 1 - Biased, 2 - Legacy, 3 - AUTO (default = Linear)
  209. UINT8 TscSyncEn; ///< TSC sync in sockets: 0 - Disable, 1 - Enable, 2 - AUTO (Default)
  210. UINT8 StaleAtoSOptEn; ///< HA A to S directory optimization: 1 - Enable; 0 - Disable; 2 - Auto (Default)
  211. UINT8 LLCDeadLineAlloc; ///< LLC dead line alloc: 1 - Enable(Default); 0 - Disable
  212. UINT8 SplitLock; ///< @deprecated Reserved, must be set to 0.
  213. UINT8 ColdResetRequestEnd; ///< @deprecated Reserved.
  214. ///
  215. /// Phy/Link Layer Options (per Port)
  216. ///
  217. KTI_CPU_SETTING PhyLinkPerPortSetting[MAX_SOCKET];
  218. UINT8 mmCfgBase; ///< MMCFG Base address, must be 64MB (SKX, HSX, BDX) / 256MB (GROVEPORT) aligned. Options: {0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6: Auto}
  219. UINT8 mmCfgSize; ///< MMCFG Size address, must be 64M, 128M or 256M. Options: {0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto}
  220. UINT32 mmiolBase; ///< MMIOL Base address, must be 64MB aligned
  221. UINT32 mmiolSize; ///< MMIOL Size address
  222. UINT32 mmiohBase; ///< Address bits above 4GB, i,e, the hex value here is address Bit[45:32] for SKX family, Bit[51:32] for ICX-SP
  223. UINT8 CpuPaLimit; ///< Limits the max address to 46bits. This will take precedence over mmiohBase
  224. UINT8 lowGap; ///< @deprecated Reserved.
  225. UINT8 highGap; ///< @deprecated Reserved.
  226. UINT16 mmiohSize; ///< Number of 1GB contiguous regions to be assigned for MMIOH space per CPU. Range 1-1024
  227. UINT8 isocEn; ///< 1 - Enable; 0 - Disable (BIOS will force this for 4S)
  228. UINT8 dcaEn; ///< 1 - Enable; 0 - Disable
  229. /**
  230. BoardTypeBitmask:
  231. - Bits[3:0] - Socket0
  232. - Bits[7:4] - Socket1
  233. - Bits[11:8] - Socket2
  234. - Bits[15:12] - Socket3
  235. - Bits[19:16] - Socket4
  236. - Bits[23:20] - Socket5
  237. - Bits[27:24] - Socket6
  238. - Bits[31:28] - Socket7
  239. Within each Socket-specific field, bits mean:
  240. - Bit0 = CPU_TYPE_STD support; always 1 on Socket0
  241. - Bit1 = CPU_TYPE_F support
  242. - Bit2 = CPU_TYPE_P support
  243. - Bit3 = reserved
  244. **/
  245. UINT32 BoardTypeBitmask;
  246. UINT32 AllLanesPtr; ///< Pointer to an array of ALL_LANES_EPARAM_LINK_INFO structures.
  247. UINT32 PerLanePtr; ///< Pointer to an array of PER_LANE_EPARAM_LINK_INFO structures.
  248. UINT32 AllLanesSizeOfTable; ///< Number of elements in array pointed to by AllLanesPtr
  249. UINT32 PerLaneSizeOfTable; ///< Number of elements in array pointed to by PerLanePtr
  250. UINT32 WaitTimeForPSBP; ///< the wait time in units of 1000us for PBSP to check in.
  251. BOOLEAN IsKtiNvramDataReady; ///< Used internally, Reserved.
  252. UINT32 OemHookPostTopologyDiscovery; ///< OEM_HOOK_POST_TOPOLOGY_DISCOVERY function pointer. Invoked at the end of topology discovery, used for error reporting.
  253. UINT32 OemGetResourceMapUpdate; ///< OEM_GET_RESOURCE_MAP_UPDATE function pointer. Allows platform code to adjust the resource map.
  254. UINT32 OemGetAdaptedEqSettings; ///< @deprecated Reserved, must be set to 0.
  255. UINT32 OemCheckCpuPartsChangeSwap; ///< @deprecated Reserved, must be set to 0.
  256. BOOLEAN WaSerializationEn; ///< Enable BIOS serialization WA by PcdWaSerializationEn
  257. KTI_RESERVED_3 Reserved166;
  258. KTI_RESERVED_4 Reserved167[MAX_SOCKET];
  259. UINT8 KtiInEnableMktme; ///< 0 - Disabled; 1 - Enabled; MkTme status decides D2Kti feature state
  260. /**
  261. Pointers to the location of the CFR/SINIT binaries.
  262. Contains a pointer to a 24 byte fixed length array.
  263. The array contains the 3 instances of the following c-struct
  264. ~~~
  265. typedef struct {
  266. UINT32 CfrImagePtr;
  267. UINT32 CfrImageSize;
  268. }
  269. ~~~
  270. This allows a maximum of 3 CFR/SINIT binaries to be provided by platform code.
  271. **/
  272. UINT32 CFRImagePtr;
  273. UINT8 S3mCFRCommit; ///< 0 - Disable S3m CFR flow. 1 - Provision S3m CFR but not Commit. 2 - Provision and Commit S3M CFR.
  274. UINT8 PucodeCFRCommit; ///< 0 - Disable Pucode CFR flow. 1 - Provision Pucode CFR but not Commit. 2 - Provision and Commit Pucode CFR.
  275. } KTI_HOST_IN;
  276. #pragma pack()
  277. #endif // _KTI_HOST_H_