PchInitSmm.h 5.5 KB

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  1. /** @file
  2. Header file for PCH Init SMM Handler
  3. Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _PCH_INIT_SMM_H_
  7. #define _PCH_INIT_SMM_H_
  8. #include <PiDxe.h>
  9. #include <Library/DebugLib.h>
  10. #include <Library/IoLib.h>
  11. #include <Library/UefiDriverEntryPoint.h>
  12. #include <Library/UefiBootServicesTableLib.h>
  13. #include <Library/UefiRuntimeServicesTableLib.h>
  14. #include <Library/SmmServicesTableLib.h>
  15. #include <Library/DxeServicesTableLib.h>
  16. #include <Library/BaseMemoryLib.h>
  17. #include <Protocol/SmmSxDispatch2.h>
  18. #include <Protocol/SmmIoTrapDispatch2.h>
  19. #include <Library/S3BootScriptLib.h>
  20. #include <Library/HobLib.h>
  21. #include <Protocol/SmmCpu.h>
  22. #include <Library/TimerLib.h>
  23. #include <IndustryStandard/Pci30.h>
  24. #include <Library/PmcLib.h>
  25. #include <Library/PchPcieRpLib.h>
  26. #include <Library/PchInfoLib.h>
  27. #include <Library/SataLib.h>
  28. #include <Library/GpioLib.h>
  29. #include <Library/GpioNativeLib.h>
  30. #include <Library/PchEspiLib.h>
  31. #include <Library/PciSegmentLib.h>
  32. #include <Private/Library/PchPciExpressHelpersLib.h>
  33. #include <Protocol/PchPcieSmiDispatch.h>
  34. #include <Protocol/PchTcoSmiDispatch.h>
  35. #include <Protocol/PchSmiDispatch.h>
  36. #include <Protocol/PchEspiSmiDispatch.h>
  37. #include <Protocol/PchSmmIoTrapControl.h>
  38. #include <Private/Protocol/PchNvsArea.h>
  39. #include <Private/Protocol/PcieIoTrap.h>
  40. #include <SiConfigHob.h>
  41. #include <Private/PchConfigHob.h>
  42. #include <Private/Library/PmcPrivateLib.h>
  43. extern EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *mPchIoTrap;
  44. extern EFI_SMM_SX_DISPATCH2_PROTOCOL *mSxDispatch;
  45. extern PCH_NVS_AREA *mPchNvsArea;
  46. extern UINT16 mAcpiBaseAddr;
  47. extern EFI_PHYSICAL_ADDRESS mResvMmioBaseAddr;
  48. extern UINTN mResvMmioSize;
  49. //
  50. // NOTE: The module variables of policy here are only valid in post time, but not runtime time.
  51. //
  52. extern PCH_CONFIG_HOB *mPchConfigHob;
  53. extern SI_CONFIG_HOB_DATA *mSiConfigHobData;
  54. /**
  55. Register PCIE Hotplug SMI dispatch function to handle Hotplug enabling
  56. @param[in] ImageHandle The image handle of this module
  57. @param[in] SystemTable The EFI System Table
  58. @retval EFI_SUCCESS The function completes successfully
  59. **/
  60. EFI_STATUS
  61. EFIAPI
  62. InitializePchPcieSmm (
  63. IN EFI_HANDLE ImageHandle,
  64. IN EFI_SYSTEM_TABLE *SystemTable
  65. );
  66. /**
  67. PCIE Hotplug SMI call back function for each Root port
  68. @param[in] DispatchHandle Handle of this dispatch function
  69. @param[in] RpContext Rootport context, which contains RootPort Index,
  70. and RootPort PCI BDF.
  71. **/
  72. VOID
  73. EFIAPI
  74. PchPcieSmiRpHandlerFunction (
  75. IN EFI_HANDLE DispatchHandle,
  76. IN PCH_PCIE_SMI_RP_CONTEXT *RpContext
  77. );
  78. /**
  79. PCIE Link Active State Change Hotplug SMI call back function for all Root ports
  80. @param[in] DispatchHandle Handle of this dispatch function
  81. @param[in] RpContext Rootport context, which contains RootPort Index,
  82. and RootPort PCI BDF.
  83. **/
  84. VOID
  85. EFIAPI
  86. PchPcieLinkActiveStateChange (
  87. IN EFI_HANDLE DispatchHandle,
  88. IN PCH_PCIE_SMI_RP_CONTEXT *RpContext
  89. );
  90. /**
  91. PCIE Link Equalization Request SMI call back function for all Root ports
  92. @param[in] DispatchHandle Handle of this dispatch function
  93. @param[in] RpContext Rootport context, which contains RootPort Index,
  94. and RootPort PCI BDF.
  95. **/
  96. VOID
  97. EFIAPI
  98. PchPcieLinkEqHandlerFunction (
  99. IN EFI_HANDLE DispatchHandle,
  100. IN PCH_PCIE_SMI_RP_CONTEXT *RpContext
  101. );
  102. /**
  103. An IoTrap callback to config PCIE power management settings
  104. @param[in] DispatchHandle - The handle of this callback, obtained when registering
  105. @param[in] DispatchContext - Pointer to the EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT
  106. **/
  107. VOID
  108. EFIAPI
  109. PchPcieIoTrapSmiCallback (
  110. IN EFI_HANDLE DispatchHandle,
  111. IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext,
  112. IN OUT VOID *CommBuffer,
  113. IN OUT UINTN *CommBufferSize
  114. );
  115. /**
  116. Initializes the PCH SMM handler for PCH save and restore
  117. @param[in] ImageHandle - Handle for the image of this driver
  118. @param[in] SystemTable - Pointer to the EFI System Table
  119. @retval EFI_SUCCESS - PCH SMM handler was installed
  120. **/
  121. EFI_STATUS
  122. EFIAPI
  123. PchInitLateSmm (
  124. IN EFI_HANDLE ImageHandle,
  125. IN EFI_SYSTEM_TABLE *SystemTable
  126. );
  127. /**
  128. Register dispatch function to handle GPIO pads Sx isolation
  129. **/
  130. VOID
  131. InitializeGpioSxIsolationSmm (
  132. VOID
  133. );
  134. /**
  135. Entry point for Pch Bios Write Protect driver.
  136. @param[in] ImageHandle Image handle of this driver.
  137. @param[in] SystemTable Global system service table.
  138. @retval EFI_SUCCESS Initialization complete.
  139. **/
  140. EFI_STATUS
  141. EFIAPI
  142. InstallPchBiosWriteProtect (
  143. IN EFI_HANDLE ImageHandle,
  144. IN EFI_SYSTEM_TABLE *SystemTable
  145. );
  146. /**
  147. This fuction install SPI ASYNC SMI handler.
  148. @retval EFI_SUCCESS Initialization complete.
  149. **/
  150. EFI_STATUS
  151. EFIAPI
  152. InstallPchSpiAsyncSmiHandler (
  153. VOID
  154. );
  155. #endif