PmcPrivateLibCnl.c 8.7 KB

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  1. /** @file
  2. PCH PMC Private Library implementation for Cannon Lake PCH.
  3. All function in this library is available for PEI, DXE, and SMM,
  4. But do not support UEFI RUNTIME environment call.
  5. Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
  6. SPDX-License-Identifier: BSD-2-Clause-Patent
  7. **/
  8. #include <Base.h>
  9. #include <Uefi/UefiBaseType.h>
  10. #include <Library/IoLib.h>
  11. #include <Library/DebugLib.h>
  12. #include <Library/BaseLib.h>
  13. #include <Library/BaseMemoryLib.h>
  14. #include <Private/Library/PmcPrivateLib.h>
  15. #include <Library/SataLib.h>
  16. #include <Library/PchInfoLib.h>
  17. #include <Register/PchRegsPmc.h>
  18. #include "PmcPrivateLibInternal.h"
  19. /**
  20. This function disables Trace Hub by enabling power gating
  21. **/
  22. VOID
  23. PmcDisableTraceHub (
  24. VOID
  25. )
  26. {
  27. EFI_STATUS Status;
  28. PMC_IPC_COMMAND_BUFFER Wbuf;
  29. ZeroMem (&Wbuf, sizeof (PMC_IPC_COMMAND_BUFFER));
  30. Wbuf.Buf0 = BIT0;
  31. Status = PmcSendCommand (V_PMC_PWRM_IPC_CMD_COMMAND_NPK_STATE, 0, 4, &Wbuf, NULL);
  32. ASSERT_EFI_ERROR (Status);
  33. }
  34. /**
  35. This function enables Trace Hub by disabling power gating
  36. **/
  37. VOID
  38. PmcEnableTraceHub (
  39. VOID
  40. )
  41. {
  42. EFI_STATUS Status;
  43. PMC_IPC_COMMAND_BUFFER Wbuf;
  44. ZeroMem (&Wbuf, sizeof (PMC_IPC_COMMAND_BUFFER));
  45. Wbuf.Buf0 = BIT1;
  46. Status = PmcSendCommand (V_PMC_PWRM_IPC_CMD_COMMAND_NPK_STATE, 0, 4, &Wbuf, NULL);
  47. ASSERT_EFI_ERROR (Status);
  48. }
  49. /**
  50. This function is part of PMC init and configures which clock wake signals should
  51. set the SLOW_RING, SA, FAST_RING_CF and SLOW_RING_CF indication sent up to the CPU/PCH
  52. **/
  53. VOID
  54. PmcInitClockWakeEnable (
  55. VOID
  56. )
  57. {
  58. UINT32 PchPwrmBase;
  59. PchPwrmBase = PmcGetPwrmBase ();
  60. if (IsPchLp () && (PchStepping () < PCH_B0)) {
  61. ///
  62. /// PWRMBASE + 0x1880 = 0x0
  63. ///
  64. MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING, 0x0);
  65. } else {
  66. ///
  67. /// PWRMBASE + 0x1880 = 0x2F8FBB01
  68. ///
  69. MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING, 0x2F8FBB01);
  70. }
  71. if (IsPchLp ()) {
  72. if (PchStepping () < PCH_B0) {
  73. ///
  74. /// PWRMBASE + 0x1884 = 0x0
  75. ///
  76. MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING2, 0x0);
  77. } else {
  78. ///
  79. /// PWRMBASE + 0x1884
  80. /// PCH-LP: 0x0280C7E1
  81. ///
  82. MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING2, 0x0280C7E1);
  83. }
  84. } else {
  85. ///
  86. /// PWRMBASE + 0x1884
  87. /// PCH-H: 0x0280D7E1
  88. ///
  89. MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING2, 0x0280D7E1);
  90. }
  91. if (IsPchLp () && (PchStepping () < PCH_B0)) {
  92. ///
  93. /// PWRMBASE + 0x1888 = 0x0
  94. ///
  95. MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA, 0x0);
  96. ///
  97. /// PWRMBASE + 0x188C = 0x0
  98. ///
  99. MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA2, 0x0);
  100. } else {
  101. ///
  102. /// PWRMBASE + 0x1888 = 0x2F8FAB01
  103. ///
  104. MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA, 0x2F8FAB01);
  105. ///
  106. /// PWRMBASE + 0x188C
  107. /// PCH-LP: 0x0280C7E1
  108. /// PCH-H: 0x0280D7E1
  109. ///
  110. if (IsPchLp ()) {
  111. MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA2, 0x0280C7E1);
  112. } else {
  113. MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA2, 0x0280D7E1);
  114. }
  115. }
  116. if (IsPchLp () && (PchStepping () < PCH_B0)) {
  117. ///
  118. /// PWRMBASE + 0x1898 = 0x0
  119. ///
  120. MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING_CF, 0x0);
  121. } else {
  122. ///
  123. /// PWRMBASE + 0x1898 = 0x00018000
  124. ///
  125. MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING_CF, 0x00018000);
  126. }
  127. }
  128. /**
  129. This function configures PWRMBASE + 0x1E00 register
  130. **/
  131. VOID
  132. PmcConfigureRegPwrm1E00 (
  133. VOID
  134. )
  135. {
  136. ///
  137. /// PWRMBASE + 0x1E00[31,30] = 1,1
  138. /// PWRMBASE + 0x1E00[29] = 0
  139. /// PWRMBASE + 0x1E00[10:6] = 0
  140. /// PWRMBASE + 0x1E00[3:0] = 2
  141. ///
  142. MmioAndThenOr32 (
  143. PmcGetPwrmBase () + R_PMC_PWRM_1E00,
  144. (UINT32) ~(BIT29 | (0x1F << 6) | 0xF),
  145. BIT31 | BIT30 | 2
  146. );
  147. }
  148. /**
  149. This function configures Misc PM_SYNC events settings
  150. **/
  151. VOID
  152. PmcConfigurePmSyncEventsSettings (
  153. VOID
  154. )
  155. {
  156. ///
  157. /// PWRMBASE + 0x18C0 = 0x00000A20
  158. ///
  159. MmioWrite32 (PmcGetPwrmBase () + R_PMC_PWRM_EN_MISC_EVENT, 0x00000A20);
  160. }
  161. /**
  162. This function enables all SerailIo devices.
  163. Static power gating disabling takes place after Global Reset, G3 or DeepSx transition.
  164. **/
  165. VOID
  166. PmcEnableSerialIo (
  167. VOID
  168. )
  169. {
  170. //
  171. // Set PWRMBASE + ST_PG_FDIS_PMC_2
  172. //
  173. MmioAnd32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_2, (UINT32)~B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO);
  174. }
  175. /**
  176. This function disables (static power gating) all SerailIo devices.
  177. For SerialIo controllers they can be power gated only if all of them are to be disabled.
  178. They cannot be statically power gated separately.
  179. For static power gating to take place Global Reset, G3 or DeepSx transition must happen.
  180. **/
  181. VOID
  182. PmcStaticDisableSerialIo (
  183. VOID
  184. )
  185. {
  186. //
  187. // Set PWRMBASE + ST_PG_FDIS_PMC_2
  188. //
  189. MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_2, B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO);
  190. }
  191. /**
  192. This function checks if all SerialIo devices are statically disabled (static power gating)
  193. @retval SerialIo disable state
  194. **/
  195. BOOLEAN
  196. PmcIsSerialIoStaticallyDisabled (
  197. VOID
  198. )
  199. {
  200. //
  201. // Check if all SerialIo controllers are statically disabled in PMC
  202. //
  203. return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_2) & B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO) == B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO);
  204. }
  205. /**
  206. This function checks if SerialIo device is supported (not disabled by fuse)
  207. @retval SerialIo support state
  208. **/
  209. BOOLEAN
  210. PmcIsSerialIoSupported (
  211. VOID
  212. )
  213. {
  214. //
  215. // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2
  216. //
  217. return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_PMC_PWRM_FUSE_DIS_RD_2_SERIALIO_FUSE_SS_DIS) == 0);
  218. }
  219. /**
  220. This function disables (non-static power gating) SCS eMMC controller and enables ModPHY SPD gating (PCH-LP only).
  221. **/
  222. VOID
  223. PmcDisableScsEmmc (
  224. VOID
  225. )
  226. {
  227. ASSERT (IsPchLp ());
  228. //
  229. // Set PWRMBASE + NST_PG_FDIS_1 to disable SCS Controller in PMC
  230. //
  231. MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_NST_PG_FDIS_1, B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_EMMC_FDIS_PMC);
  232. }
  233. /**
  234. This function disables (non-static power gating) SCS SD Card controller and enables ModPHY SPD gating (PCH-LP only).
  235. **/
  236. VOID
  237. PmcDisableScsSdCard (
  238. VOID
  239. )
  240. {
  241. UINT32 ScsDevicePgMask;
  242. if (IsPchLp ()) {
  243. ScsDevicePgMask = B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_SDCARD_FDIS_PMC;
  244. } else {
  245. ScsDevicePgMask = B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_SDCARD_FDIS_PMC;
  246. }
  247. //
  248. // Set PWRMBASE + NST_PG_FDIS_1 to disable SCS Controller in PMC
  249. //
  250. MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_NST_PG_FDIS_1, ScsDevicePgMask);
  251. }
  252. /**
  253. This function disables (non-static power gating) SCS UFS controller and enables ModPHY SPD gating (PCH-LP only).
  254. @param[in] UfsNum SCS UFS Device
  255. **/
  256. VOID
  257. PmcDisableScsUfs (
  258. IN UINT32 UfsNum
  259. )
  260. {
  261. UINT32 PchPwrmBase;
  262. ASSERT ((UfsNum == 0) && IsPchLp ());
  263. PchPwrmBase = PmcGetPwrmBase ();
  264. //
  265. // Set PWRMBASE + NST_PG_FDIS_1 to disable SCS Controller in PMC
  266. //
  267. MmioOr32 (PchPwrmBase + R_PMC_PWRM_NST_PG_FDIS_1, B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_UFS_FDIS_PMC);
  268. if (PmcIsModPhySusPgSupported ()) {
  269. //
  270. // Set MSPDRTREQ:
  271. // PchPwrmBase + R_PWRM_MODPHY_PM_CFG5[16] = 1 to enable ASL code trigger request for ModPHY SPD gating.
  272. //
  273. MmioOr32 (PchPwrmBase + R_PMC_PWRM_MODPHY_PM_CFG5, B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_UFS2);
  274. }
  275. }
  276. /**
  277. This function checks if SCS eMMC device is supported (not disabled by fuse)
  278. @retval SCS device support state
  279. **/
  280. BOOLEAN
  281. PmcIsScsEmmcSupported (
  282. VOID
  283. )
  284. {
  285. //
  286. // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2
  287. //
  288. return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_PMC_PWRM_FUSE_DIS_RD_2_EMMC_FUSE_SS_DIS) == 0);
  289. }
  290. /**
  291. This function checks if SCS SD Card device is supported (not disabled by fuse)
  292. @retval SCS device support state
  293. **/
  294. BOOLEAN
  295. PmcIsScsSdCardSupported (
  296. VOID
  297. )
  298. {
  299. //
  300. // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2
  301. //
  302. return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_PMC_PWRM_FUSE_DIS_RD_2_SDX_FUSE_SS_DIS) == 0);
  303. }
  304. /**
  305. This function checks if SCS UFS device is supported (not disabled by fuse)
  306. @param[in] UfsNum SCS UFS Device
  307. @retval SCS device support state
  308. **/
  309. BOOLEAN
  310. PmcIsScsUfsSupported (
  311. IN UINT32 UfsNum
  312. )
  313. {
  314. //
  315. // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2
  316. //
  317. return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_PMC_PWRM_FUSE_DIS_RD_2_UFSX2_FUSE_SS_DIS) == 0);
  318. }