PeiPchPolicyLib.c 26 KB

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  1. /** @file
  2. This file is PeiPchPolicy library.
  3. Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "PeiPchPolicyLibrary.h"
  7. #include <Library/PchPcieRpLib.h>
  8. #include <Library/CpuPlatformLib.h>
  9. #include <Register/PchRegsLpcCnl.h>
  10. #include <Library/ConfigBlockLib.h>
  11. /**
  12. mPxRcConfig[] table contains data for 8259 routing (how PIRQx is mapped to IRQy).
  13. This information is used by systems which choose to use legacy PIC
  14. interrupt controller. Only IRQ3-7,9-12,14,15 are valid. Values from this table
  15. will be programmed into ITSS.PxRC registers.
  16. **/
  17. GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPxRcConfig[] = {
  18. 11, // PARC: PIRQA -> IRQ11
  19. 10, // PBRC: PIRQB -> IRQ10
  20. 11, // PCRC: PIRQC -> IRQ11
  21. 11, // PDRC: PIRQD -> IRQ11
  22. 11, // PERC: PIRQE -> IRQ11
  23. 11, // PFRC: PIRQF -> IRQ11
  24. 11, // PGRC: PIRQG -> IRQ11
  25. 11 // PHRC: PIRQH -> IRQ11
  26. };
  27. /**
  28. Load Config block default
  29. @param[in] ConfigBlockPointer Pointer to config block
  30. **/
  31. VOID
  32. LoadPchGeneralConfigDefault (
  33. IN VOID *ConfigBlockPointer
  34. )
  35. {
  36. PCH_GENERAL_CONFIG *PchGeneralConfig;
  37. PchGeneralConfig = ConfigBlockPointer;
  38. DEBUG ((DEBUG_INFO, "PchGeneralConfig->Header.GuidHob.Name = %g\n", &PchGeneralConfig->Header.GuidHob.Name));
  39. DEBUG ((DEBUG_INFO, "PchGeneralConfig->Header.GuidHob.Header.HobLength = 0x%x\n", PchGeneralConfig->Header.GuidHob.Header.HobLength));
  40. /********************************
  41. PCH general configuration
  42. ********************************/
  43. }
  44. /**
  45. Load Config block default
  46. @param[in] ConfigBlockPointer Pointer to config block
  47. **/
  48. VOID
  49. LoadPcieRpConfigDefault (
  50. IN VOID *ConfigBlockPointer
  51. )
  52. {
  53. UINTN Index;
  54. PCH_PCIE_CONFIG *PcieRpConfig;
  55. PcieRpConfig = ConfigBlockPointer;
  56. DEBUG ((DEBUG_INFO, "PcieRpConfig->Header.GuidHob.Name = %g\n", &PcieRpConfig->Header.GuidHob.Name));
  57. DEBUG ((DEBUG_INFO, "PcieRpConfig->Header.GuidHob.Header.HobLength = 0x%x\n", PcieRpConfig->Header.GuidHob.Header.HobLength));
  58. /********************************
  59. PCI Express related settings
  60. ********************************/
  61. PcieRpConfig->RpFunctionSwap = TRUE;
  62. for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
  63. PcieRpConfig->RootPort[Index].Aspm = PchPcieAspmAutoConfig;
  64. PcieRpConfig->RootPort[Index].PmSci = TRUE;
  65. PcieRpConfig->RootPort[Index].AcsEnabled = TRUE;
  66. PcieRpConfig->RootPort[Index].PtmEnabled = TRUE;
  67. PcieRpConfig->RootPort[Index].DpcEnabled = TRUE;
  68. PcieRpConfig->RootPort[Index].RpDpcExtensionsEnabled = TRUE;
  69. PcieRpConfig->RootPort[Index].MaxPayload = PchPcieMaxPayload256;
  70. PcieRpConfig->RootPort[Index].SlotImplemented = TRUE;
  71. PcieRpConfig->RootPort[Index].PhysicalSlotNumber = (UINT8) Index;
  72. PcieRpConfig->RootPort[Index].L1Substates = PchPcieL1SubstatesL1_1_2;
  73. PcieRpConfig->RootPort[Index].EnableCpm = TRUE;
  74. PcieRpConfig->RootPort[Index].Gen3EqPh3Method = PchPcieEqHardware;
  75. //
  76. // PCIe LTR Configuration.
  77. //
  78. PcieRpConfig->RootPort[Index].LtrEnable = TRUE;
  79. PcieRpConfig->RootPort[Index].LtrMaxSnoopLatency = 0x1003;
  80. PcieRpConfig->RootPort[Index].LtrMaxNoSnoopLatency = 0x1003;
  81. PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMode = 2;
  82. PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMultiplier = 2;
  83. PcieRpConfig->RootPort[Index].SnoopLatencyOverrideValue = 60;
  84. PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMode = 2;
  85. PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier = 2;
  86. PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideValue = 60;
  87. PcieRpConfig->RootPort[Index].Uptp = 5;
  88. PcieRpConfig->RootPort[Index].Dptp = 7;
  89. PcieRpConfig->EqPh3LaneParam[Index].Cm = 6;
  90. PcieRpConfig->EqPh3LaneParam[Index].Cp = 2;
  91. }
  92. PcieRpConfig->SwEqCoeffList[0].Cm = 4;
  93. PcieRpConfig->SwEqCoeffList[0].Cp = 8;
  94. PcieRpConfig->SwEqCoeffList[1].Cm = 6;
  95. PcieRpConfig->SwEqCoeffList[1].Cp = 2;
  96. PcieRpConfig->SwEqCoeffList[2].Cm = 8;
  97. PcieRpConfig->SwEqCoeffList[2].Cp = 6;
  98. PcieRpConfig->SwEqCoeffList[3].Cm = 10;
  99. PcieRpConfig->SwEqCoeffList[3].Cp = 8;
  100. PcieRpConfig->SwEqCoeffList[4].Cm = 12;
  101. PcieRpConfig->SwEqCoeffList[4].Cp = 2;
  102. }
  103. /**
  104. Load Config block default
  105. @param[in] ConfigBlockPointer Pointer to config block
  106. **/
  107. VOID
  108. LoadSataConfigDefault (
  109. IN VOID *ConfigBlockPointer
  110. )
  111. {
  112. UINTN PortIndex;
  113. UINTN Index;
  114. UINT32 SataCtrlIndex;
  115. PCH_SATA_CONFIG *SataConfig;
  116. SataConfig = (PCH_SATA_CONFIG *)ConfigBlockPointer;
  117. DEBUG ((DEBUG_INFO, "SataConfig->Header.GuidHob.Name = %g\n", &SataConfig->Header.GuidHob.Name));
  118. DEBUG ((DEBUG_INFO, "SataConfig->Header.GuidHob.Header.HobLength = 0x%x\n", SataConfig->Header.GuidHob.Header.HobLength));
  119. for (SataCtrlIndex = 0; SataCtrlIndex < GetPchMaxSataControllerNum (); SataCtrlIndex++, SataConfig++) {
  120. /********************************
  121. SATA related settings
  122. ********************************/
  123. SataConfig->Enable = TRUE;
  124. SataConfig->SalpSupport = TRUE;
  125. SataConfig->SataMode = PchSataModeAhci;
  126. for (PortIndex = 0; PortIndex < GetPchMaxSataPortNum (SataCtrlIndex); PortIndex++) {
  127. SataConfig->PortSettings[PortIndex].Enable = TRUE;
  128. SataConfig->PortSettings[PortIndex].DmVal = 15;
  129. SataConfig->PortSettings[PortIndex].DitoVal = 625;
  130. }
  131. SataConfig->Rst.Raid0 = TRUE;
  132. SataConfig->Rst.Raid1 = TRUE;
  133. SataConfig->Rst.Raid10 = TRUE;
  134. SataConfig->Rst.Raid5 = TRUE;
  135. SataConfig->Rst.Irrt = TRUE;
  136. SataConfig->Rst.OromUiBanner = TRUE;
  137. SataConfig->Rst.OromUiDelay = PchSataOromDelay2sec;
  138. SataConfig->Rst.HddUnlock = TRUE;
  139. SataConfig->Rst.LedLocate = TRUE;
  140. SataConfig->Rst.IrrtOnly = TRUE;
  141. SataConfig->Rst.SmartStorage = TRUE;
  142. SataConfig->Rst.OptaneMemory = TRUE;
  143. SataConfig->Rst.CpuAttachedStorage = TRUE;
  144. for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
  145. SataConfig->RstPcieStorageRemap[Index].DeviceResetDelay = 100;
  146. }
  147. SataConfig->PwrOptEnable = TRUE;
  148. SataConfig->ThermalThrottling.SuggestedSetting = TRUE;
  149. }
  150. }
  151. /**
  152. Get Sata Config Policy
  153. @param[in] SiPolicy The RC Policy PPI instance
  154. @param[in] SataCtrlIndex SATA controller index
  155. @retval SataConfig Pointer to Sata Config Policy
  156. **/
  157. PCH_SATA_CONFIG *
  158. GetPchSataConfig (
  159. IN SI_POLICY_PPI *SiPolicy,
  160. IN UINT32 SataCtrlIndex
  161. )
  162. {
  163. PCH_SATA_CONFIG *SataConfig;
  164. EFI_STATUS Status;
  165. ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ());
  166. Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig);
  167. ASSERT_EFI_ERROR (Status);
  168. SataConfig += SataCtrlIndex;
  169. return SataConfig;
  170. }
  171. /**
  172. Load Config block default
  173. @param[in] ConfigBlockPointer Pointer to config block
  174. **/
  175. VOID
  176. LoadIoApicConfigDefault (
  177. IN VOID *ConfigBlockPointer
  178. )
  179. {
  180. PCH_IOAPIC_CONFIG *IoApicConfig;
  181. IoApicConfig = ConfigBlockPointer;
  182. DEBUG ((DEBUG_INFO, "IoApicConfig->Header.GuidHob.Name = %g\n", &IoApicConfig->Header.GuidHob.Name));
  183. DEBUG ((DEBUG_INFO, "IoApicConfig->Header.GuidHob.Header.HobLength = 0x%x\n", IoApicConfig->Header.GuidHob.Header.HobLength));
  184. /********************************
  185. Io Apic configuration
  186. ********************************/
  187. IoApicConfig->IoApicId = 0x02;
  188. IoApicConfig->IoApicEntry24_119 = TRUE;
  189. IoApicConfig->Enable8254ClockGating = TRUE;
  190. IoApicConfig->Enable8254ClockGatingOnS3 = TRUE;
  191. }
  192. /**
  193. Load Config block default
  194. @param[in] ConfigBlockPointer Pointer to config block
  195. **/
  196. VOID
  197. LoadDmiConfigDefault (
  198. IN VOID *ConfigBlockPointer
  199. )
  200. {
  201. PCH_DMI_CONFIG *DmiConfig;
  202. DmiConfig = ConfigBlockPointer;
  203. DEBUG ((DEBUG_INFO, "DmiConfig->Header.GuidHob.Name = %g\n", &DmiConfig->Header.GuidHob.Name));
  204. DEBUG ((DEBUG_INFO, "DmiConfig->Header.GuidHob.Header.HobLength = 0x%x\n", DmiConfig->Header.GuidHob.Header.HobLength));
  205. /********************************
  206. DMI related settings
  207. ********************************/
  208. DmiConfig->DmiAspmCtrl = PchPcieAspmAutoConfig;
  209. }
  210. /**
  211. Load Config block default
  212. @param[in] ConfigBlockPointer Pointer to config block
  213. **/
  214. VOID
  215. LoadFlashProtectionConfigDefault (
  216. IN VOID *ConfigBlockPointer
  217. )
  218. {
  219. PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig;
  220. FlashProtectionConfig = ConfigBlockPointer;
  221. DEBUG ((DEBUG_INFO, "FlashProtectionConfig->Header.GuidHob.Name = %g\n", &FlashProtectionConfig->Header.GuidHob.Name));
  222. DEBUG ((DEBUG_INFO, "FlashProtectionConfig->Header.GuidHob.Header.HobLength = 0x%x\n", FlashProtectionConfig->Header.GuidHob.Header.HobLength));
  223. }
  224. /**
  225. Load Config block default
  226. @param[in] ConfigBlockPointer Pointer to config block
  227. **/
  228. VOID
  229. LoadHdAudioConfigDefault (
  230. IN VOID *ConfigBlockPointer
  231. )
  232. {
  233. PCH_HDAUDIO_CONFIG *HdAudioConfig;
  234. HdAudioConfig = ConfigBlockPointer;
  235. DEBUG ((DEBUG_INFO, "HdAudioConfig->Header.GuidHob.Name = %g\n", &HdAudioConfig->Header.GuidHob.Name));
  236. DEBUG ((DEBUG_INFO, "HdAudioConfig->Header.GuidHob.Header.HobLength = 0x%x\n", HdAudioConfig->Header.GuidHob.Header.HobLength));
  237. /********************************
  238. HD-Audio configuration
  239. ********************************/
  240. HdAudioConfig->DspEnable = TRUE;
  241. HdAudioConfig->HdAudioLinkFrequency = PchHdaLinkFreq24MHz;
  242. HdAudioConfig->IDispLinkFrequency = PchHdaLinkFreq96MHz;
  243. HdAudioConfig->IDispLinkTmode = PchHdaIDispMode2T;
  244. HdAudioConfig->ResetWaitTimer = 600; // Must be at least 521us (25 frames)
  245. HdAudioConfig->AudioLinkHda = TRUE;
  246. HdAudioConfig->AudioLinkDmic0 = TRUE;
  247. HdAudioConfig->AudioLinkDmic1 = TRUE;
  248. }
  249. /**
  250. Load Config block default
  251. @param[in] ConfigBlockPointer Pointer to config block
  252. **/
  253. VOID
  254. LoadInterruptConfigDefault (
  255. IN VOID *ConfigBlockPointer
  256. )
  257. {
  258. PCH_INTERRUPT_CONFIG *InterruptConfig;
  259. InterruptConfig = ConfigBlockPointer;
  260. DEBUG ((DEBUG_INFO, "InterruptConfig->Header.GuidHob.Name = %g\n", &InterruptConfig->Header.GuidHob.Name));
  261. DEBUG ((DEBUG_INFO, "InterruptConfig->Header.GuidHob.Header.HobLength = 0x%x\n", InterruptConfig->Header.GuidHob.Header.HobLength));
  262. LoadDeviceInterruptConfig (InterruptConfig);
  263. ASSERT ((sizeof (mPxRcConfig) / sizeof (UINT8)) <= PCH_MAX_PXRC_CONFIG);
  264. CopyMem (
  265. InterruptConfig->PxRcConfig,
  266. mPxRcConfig,
  267. sizeof (mPxRcConfig)
  268. );
  269. InterruptConfig->GpioIrqRoute = 14;
  270. InterruptConfig->SciIrqSelect = 9;
  271. InterruptConfig->TcoIrqSelect = 9;
  272. }
  273. /**
  274. Load Config block default
  275. @param[in] ConfigBlockPointer Pointer to config block
  276. **/
  277. VOID
  278. LoadIshConfigDefault (
  279. IN VOID *ConfigBlockPointer
  280. )
  281. {
  282. PCH_ISH_CONFIG *IshConfig;
  283. IshConfig = ConfigBlockPointer;
  284. DEBUG ((DEBUG_INFO, "IshConfig->Header.GuidHob.Name = %g\n", &IshConfig->Header.GuidHob.Name));
  285. DEBUG ((DEBUG_INFO, "IshConfig->Header.GuidHob.Header.HobLength = 0x%x\n", IshConfig->Header.GuidHob.Header.HobLength));
  286. }
  287. /**
  288. Load Config block default
  289. @param[in] ConfigBlockPointer Pointer to config block
  290. **/
  291. VOID
  292. LoadLanConfigDefault (
  293. IN VOID *ConfigBlockPointer
  294. )
  295. {
  296. PCH_LAN_CONFIG *LanConfig;
  297. LanConfig = ConfigBlockPointer;
  298. DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Name = %g\n", &LanConfig->Header.GuidHob.Name));
  299. DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Header.HobLength = 0x%x\n", LanConfig->Header.GuidHob.Header.HobLength));
  300. /********************************
  301. Lan configuration
  302. ********************************/
  303. LanConfig->Enable = TRUE;
  304. LanConfig->LtrEnable = TRUE;
  305. }
  306. /**
  307. Load Config block default
  308. @param[in] ConfigBlockPointer Pointer to config block
  309. **/
  310. VOID
  311. LoadLockDownConfigDefault (
  312. IN VOID *ConfigBlockPointer
  313. )
  314. {
  315. PCH_LOCK_DOWN_CONFIG *LockDownConfig;
  316. LockDownConfig = ConfigBlockPointer;
  317. DEBUG ((DEBUG_INFO, "LockDownConfig->Header.GuidHob.Name = %g\n", &LockDownConfig->Header.GuidHob.Name));
  318. DEBUG ((DEBUG_INFO, "LockDownConfig->Header.GuidHob.Header.HobLength = 0x%x\n", LockDownConfig->Header.GuidHob.Header.HobLength));
  319. /********************************
  320. Lockdown configuration
  321. ********************************/
  322. LockDownConfig->GlobalSmi = TRUE;
  323. LockDownConfig->BiosInterface = TRUE;
  324. LockDownConfig->RtcMemoryLock = TRUE;
  325. LockDownConfig->BiosLock = TRUE;
  326. }
  327. /**
  328. Load Config block default
  329. @param[in] ConfigBlockPointer Pointer to config block
  330. **/
  331. VOID
  332. LoadP2sbConfigDefault (
  333. IN VOID *ConfigBlockPointer
  334. )
  335. {
  336. PCH_P2SB_CONFIG *P2sbConfig;
  337. P2sbConfig = ConfigBlockPointer;
  338. DEBUG ((DEBUG_INFO, "P2sbConfig->Header.GuidHob.Name = %g\n", &P2sbConfig->Header.GuidHob.Name));
  339. DEBUG ((DEBUG_INFO, "P2sbConfig->Header.GuidHob.Header.HobLength = 0x%x\n", P2sbConfig->Header.GuidHob.Header.HobLength));
  340. }
  341. /**
  342. Load Config block default
  343. @param[in] ConfigBlockPointer Pointer to config block
  344. **/
  345. VOID
  346. LoadPmConfigDefault (
  347. IN VOID *ConfigBlockPointer
  348. )
  349. {
  350. PCH_PM_CONFIG *PmConfig;
  351. PmConfig = ConfigBlockPointer;
  352. DEBUG ((DEBUG_INFO, "PmConfig->Header.GuidHob.Name = %g\n", &PmConfig->Header.GuidHob.Name));
  353. DEBUG ((DEBUG_INFO, "PmConfig->Header.GuidHob.Header.HobLength = 0x%x\n", PmConfig->Header.GuidHob.Header.HobLength));
  354. /********************************
  355. MiscPm Configuration
  356. ********************************/
  357. PmConfig->MeWakeSts = TRUE;
  358. PmConfig->WolOvrWkSts = TRUE;
  359. PmConfig->WakeConfig.WolEnableOverride = TRUE;
  360. PmConfig->WakeConfig.LanWakeFromDeepSx = TRUE;
  361. PmConfig->PchSlpS3MinAssert = PchSlpS350ms;
  362. PmConfig->PchSlpS4MinAssert = PchSlpS41s;
  363. PmConfig->PchSlpSusMinAssert = PchSlpSus4s;
  364. PmConfig->PchSlpAMinAssert = PchSlpA2s;
  365. PmConfig->SlpLanLowDc = TRUE;
  366. PmConfig->PciePllSsc = 0xFF;
  367. PmConfig->LpcClockRun = TRUE;
  368. PmConfig->SlpS0Enable = TRUE;
  369. PmConfig->CpuC10GatePinEnable = TRUE;
  370. if (IsWhlCpu () && (GetCpuStepping () == EnumCflV0)) {
  371. PmConfig->SlpS0WithGbeSupport = FALSE;
  372. } else {
  373. PmConfig->SlpS0WithGbeSupport = TRUE;
  374. }
  375. if (IsPchLp ()) {
  376. PmConfig->ModPhySusPgEnable = TRUE;
  377. }
  378. }
  379. /**
  380. Load Config block default
  381. @param[in] ConfigBlockPointer Pointer to config block
  382. **/
  383. VOID
  384. LoadScsConfigDefault (
  385. IN VOID *ConfigBlockPointer
  386. )
  387. {
  388. PCH_SCS_CONFIG *ScsConfig;
  389. ScsConfig = ConfigBlockPointer;
  390. DEBUG ((DEBUG_INFO, "ScsConfig->Header.GuidHob.Name = %g\n", &ScsConfig->Header.GuidHob.Name));
  391. DEBUG ((DEBUG_INFO, "ScsConfig->Header.GuidHob.Header.HobLength = 0x%x\n", ScsConfig->Header.GuidHob.Header.HobLength));
  392. /********************************
  393. SCS Configuration
  394. ********************************/
  395. ScsConfig->ScsEmmcEnabled = IsPchLp () ? TRUE : FALSE; // eMMC present on PCH-LP only
  396. ScsConfig->ScsEmmcHs400DriverStrength = DriverStrength40Ohm;
  397. //Enable Sd Card controller for Non-Desktop sku platforms
  398. if (GetCpuSku () != EnumCpuTrad) {
  399. ScsConfig->ScsSdcardEnabled = TRUE;
  400. }
  401. ScsConfig->SdCardPowerEnableActiveHigh = TRUE;
  402. ScsConfig->ScsUfsEnabled = TRUE;
  403. }
  404. /**
  405. Load Config block default
  406. @param[in] ConfigBlockPointer Pointer to config block
  407. **/
  408. VOID
  409. LoadSerialIoConfigDefault (
  410. IN VOID *ConfigBlockPointer
  411. )
  412. {
  413. UINTN Index;
  414. PCH_SERIAL_IO_CONFIG *SerialIoConfig;
  415. SerialIoConfig = ConfigBlockPointer;
  416. DEBUG ((DEBUG_INFO, "SerialIoConfig->Header.GuidHob.Name = %g\n", &SerialIoConfig->Header.GuidHob.Name));
  417. DEBUG ((DEBUG_INFO, "SerialIoConfig->Header.GuidHob.Header.HobLength = 0x%x\n", SerialIoConfig->Header.GuidHob.Header.HobLength));
  418. /********************************
  419. SerialIo Configuration
  420. ********************************/
  421. for (Index = 0; Index < GetPchMaxSerialIoControllersNum (); Index++) {
  422. SerialIoConfig->DevMode[Index] = PchSerialIoPci;
  423. }
  424. SerialIoConfig->DebugUartNumber = PcdGet8 (PcdSerialIoUartNumber);
  425. }
  426. /**
  427. Load Config block default
  428. @param[in] ConfigBlockPointer Pointer to config block
  429. **/
  430. VOID
  431. LoadSerialIrqConfigDefault (
  432. IN VOID *ConfigBlockPointer
  433. )
  434. {
  435. PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;
  436. SerialIrqConfig = ConfigBlockPointer;
  437. DEBUG ((DEBUG_INFO, "SerialIrqConfig->Header.GuidHob.Name = %g\n", &SerialIrqConfig->Header.GuidHob.Name));
  438. DEBUG ((DEBUG_INFO, "SerialIrqConfig->Header.GuidHob.Header.HobLength = 0x%x\n", SerialIrqConfig->Header.GuidHob.Header.HobLength));
  439. /********************************
  440. Serial IRQ Configuration
  441. ********************************/
  442. SerialIrqConfig->SirqEnable = TRUE;
  443. SerialIrqConfig->SirqMode = PchQuietMode;
  444. SerialIrqConfig->StartFramePulse = PchSfpw4Clk;
  445. }
  446. /**
  447. Load Config block default
  448. @param[in] ConfigBlockPointer Pointer to config block
  449. **/
  450. VOID
  451. LoadThermalConfigDefault (
  452. IN VOID *ConfigBlockPointer
  453. )
  454. {
  455. PCH_THERMAL_CONFIG *ThermalConfig;
  456. ThermalConfig = ConfigBlockPointer;
  457. DEBUG ((DEBUG_INFO, "ThermalConfig->Header.GuidHob.Name = %g\n", &ThermalConfig->Header.GuidHob.Name));
  458. DEBUG ((DEBUG_INFO, "ThermalConfig->Header.GuidHob.Header.HobLength = 0x%x\n", ThermalConfig->Header.GuidHob.Header.HobLength));
  459. /********************************
  460. Thermal configuration.
  461. ********************************/
  462. ThermalConfig->TsmicLock = TRUE;
  463. ThermalConfig->PchHotLevel = 0x154;
  464. ThermalConfig->TTLevels.SuggestedSetting = TRUE;
  465. ThermalConfig->TTLevels.PchCrossThrottling = TRUE;
  466. ThermalConfig->DmiHaAWC.SuggestedSetting = TRUE;
  467. ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioC].PmsyncEnable = TRUE;
  468. ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioC].C0TransmitEnable = TRUE;
  469. ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioD].PmsyncEnable = TRUE;
  470. ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioD].C0TransmitEnable = TRUE;
  471. }
  472. /**
  473. Load Config block default
  474. @param[in] ConfigBlockPointer Pointer to config block
  475. **/
  476. VOID
  477. LoadUsbConfigDefault (
  478. IN VOID *ConfigBlockPointer
  479. )
  480. {
  481. UINTN PortIndex;
  482. USB_CONFIG *UsbConfig;
  483. UsbConfig = ConfigBlockPointer;
  484. DEBUG ((DEBUG_INFO, "UsbConfig->Header.GuidHob.Name = %g\n", &UsbConfig->Header.GuidHob.Name));
  485. DEBUG ((DEBUG_INFO, "UsbConfig->Header.GuidHob.Header.HobLength = 0x%x\n", UsbConfig->Header.GuidHob.Header.HobLength));
  486. /********************************
  487. USB related configuration
  488. ********************************/
  489. for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex++) {
  490. UsbConfig->PortUsb20[PortIndex].Enable = TRUE;
  491. }
  492. for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {
  493. UsbConfig->PortUsb30[PortIndex].Enable = TRUE;
  494. }
  495. //
  496. // BIOS should program PDO in PEI phase by default
  497. //
  498. UsbConfig->PdoProgramming = TRUE;
  499. //
  500. // Default values of USB2 AFE settings.
  501. //
  502. UsbConfig->Usb2PhySusPgEnable = TRUE;
  503. for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex++) {
  504. UsbConfig->PortUsb20[PortIndex].Afe.Petxiset = 3;
  505. UsbConfig->PortUsb20[PortIndex].Afe.Txiset = 2;
  506. UsbConfig->PortUsb20[PortIndex].Afe.Predeemp = 1;
  507. UsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit = 1;
  508. }
  509. for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {
  510. UsbConfig->PortUsb30HsioRx[PortIndex].HsioOlfpsCfgPullUpDwnRes = 3;
  511. }
  512. UsbConfig->XhciOcLock = TRUE;
  513. //
  514. // xDCI configuration
  515. //
  516. UsbConfig->XdciConfig.Enable = FALSE;
  517. }
  518. /**
  519. Load Config block default
  520. @param[in] ConfigBlockPointer Pointer to config block
  521. **/
  522. VOID
  523. LoadEspiConfigDefault (
  524. IN VOID *ConfigBlockPointer
  525. )
  526. {
  527. PCH_ESPI_CONFIG *EspiConfig;
  528. EspiConfig = ConfigBlockPointer;
  529. DEBUG ((DEBUG_INFO, "EspiConfig->Header.GuidHob.Name = %g\n", &EspiConfig->Header.GuidHob.Name));
  530. DEBUG ((DEBUG_INFO, "EspiConfig->Header.GuidHob.Header.HobLength = 0x%x\n", EspiConfig->Header.GuidHob.Header.HobLength));
  531. /********************************
  532. Espi configuration.
  533. ********************************/
  534. EspiConfig->BmeMasterSlaveEnabled = TRUE;
  535. }
  536. /**
  537. Load Config block default
  538. @param[in] ConfigBlockPointer Pointer to config block
  539. **/
  540. VOID
  541. LoadCnviConfigDefault (
  542. IN VOID *ConfigBlockPointer
  543. )
  544. {
  545. PCH_CNVI_CONFIG *CnviConfig;
  546. CnviConfig = ConfigBlockPointer;
  547. DEBUG ((DEBUG_INFO, "CnviConfig->Header.GuidHob.Name = %g\n", &CnviConfig->Header.GuidHob.Name));
  548. DEBUG ((DEBUG_INFO, "CnviConfig->Header.GuidHob.Header.HobLength = 0x%x\n", CnviConfig->Header.GuidHob.Header.HobLength));
  549. /********************************
  550. Cnvi configuration.
  551. ********************************/
  552. CnviConfig->Mode = CnviModeAuto; // Automatic detection
  553. }
  554. /**
  555. Load Config block default
  556. @param[in] ConfigBlockPointer Pointer to config block
  557. **/
  558. VOID
  559. LoadHsioConfigDefault (
  560. IN VOID *ConfigBlockPointer
  561. )
  562. {
  563. PCH_HSIO_CONFIG *HsioConfig;
  564. HsioConfig = ConfigBlockPointer;
  565. DEBUG ((DEBUG_INFO, "HsioConfig->Header.GuidHob.Name = %g\n", &HsioConfig->Header.GuidHob.Name));
  566. DEBUG ((DEBUG_INFO, "HsioConfig->Header.GuidHob.Header.HobLength = 0x%x\n", HsioConfig->Header.GuidHob.Header.HobLength));
  567. }
  568. GLOBAL_REMOVE_IF_UNREFERENCED COMPONENT_BLOCK_ENTRY mPchIpBlocks [] = {
  569. {&gPchGeneralConfigGuid, sizeof (PCH_GENERAL_CONFIG), PCH_GENERAL_CONFIG_REVISION, LoadPchGeneralConfigDefault},
  570. {&gPcieRpConfigGuid, sizeof (PCH_PCIE_CONFIG), PCIE_RP_CONFIG_REVISION, LoadPcieRpConfigDefault},
  571. {&gSataConfigGuid, sizeof (PCH_SATA_CONFIG), SATA_CONFIG_REVISION, LoadSataConfigDefault},
  572. {&gIoApicConfigGuid, sizeof (PCH_IOAPIC_CONFIG), IOAPIC_CONFIG_REVISION, LoadIoApicConfigDefault},
  573. {&gDmiConfigGuid, sizeof (PCH_DMI_CONFIG), DMI_CONFIG_REVISION, LoadDmiConfigDefault},
  574. {&gFlashProtectionConfigGuid, sizeof (PCH_FLASH_PROTECTION_CONFIG), FLASH_PROTECTION_CONFIG_REVISION, LoadFlashProtectionConfigDefault},
  575. {&gHdAudioConfigGuid, sizeof (PCH_HDAUDIO_CONFIG), HDAUDIO_CONFIG_REVISION, LoadHdAudioConfigDefault},
  576. {&gInterruptConfigGuid, sizeof (PCH_INTERRUPT_CONFIG), INTERRUPT_CONFIG_REVISION, LoadInterruptConfigDefault},
  577. {&gIshConfigGuid, sizeof (PCH_ISH_CONFIG), ISH_CONFIG_REVISION, LoadIshConfigDefault},
  578. {&gLanConfigGuid, sizeof (PCH_LAN_CONFIG), LAN_CONFIG_REVISION, LoadLanConfigDefault},
  579. {&gLockDownConfigGuid, sizeof (PCH_LOCK_DOWN_CONFIG), LOCK_DOWN_CONFIG_REVISION, LoadLockDownConfigDefault},
  580. {&gP2sbConfigGuid, sizeof (PCH_P2SB_CONFIG), P2SB_CONFIG_REVISION, LoadP2sbConfigDefault},
  581. {&gPmConfigGuid, sizeof (PCH_PM_CONFIG), PM_CONFIG_REVISION, LoadPmConfigDefault},
  582. {&gScsConfigGuid, sizeof (PCH_SCS_CONFIG), SCS_CONFIG_REVISION, LoadScsConfigDefault},
  583. {&gSerialIoConfigGuid, sizeof (PCH_SERIAL_IO_CONFIG), SERIAL_IO_CONFIG_REVISION, LoadSerialIoConfigDefault},
  584. {&gSerialIrqConfigGuid, sizeof (PCH_LPC_SIRQ_CONFIG), SERIAL_IRQ_CONFIG_REVISION, LoadSerialIrqConfigDefault},
  585. {&gThermalConfigGuid, sizeof (PCH_THERMAL_CONFIG), THERMAL_CONFIG_REVISION, LoadThermalConfigDefault},
  586. {&gUsbConfigGuid, sizeof (USB_CONFIG), USB_CONFIG_REVISION, LoadUsbConfigDefault},
  587. {&gEspiConfigGuid, sizeof (PCH_ESPI_CONFIG), ESPI_CONFIG_REVISION, LoadEspiConfigDefault},
  588. {&gCnviConfigGuid, sizeof (PCH_CNVI_CONFIG), CNVI_CONFIG_REVISION, LoadCnviConfigDefault},
  589. {&gHsioConfigGuid, sizeof (PCH_HSIO_CONFIG), HSIO_CONFIG_REVISION, LoadHsioConfigDefault},
  590. };
  591. /**
  592. Get PCH config block table total size.
  593. @retval Size of PCH config block table
  594. **/
  595. UINT16
  596. EFIAPI
  597. PchGetConfigBlockTotalSize (
  598. VOID
  599. )
  600. {
  601. return GetComponentConfigBlockTotalSize (&mPchIpBlocks[0], sizeof (mPchIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));
  602. }
  603. /**
  604. PchAddConfigBlocks add all PCH config blocks.
  605. @param[in] ConfigBlockTableAddress The pointer to add PCH config blocks
  606. @retval EFI_SUCCESS The policy default is initialized.
  607. @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
  608. **/
  609. EFI_STATUS
  610. EFIAPI
  611. PchAddConfigBlocks (
  612. IN VOID *ConfigBlockTableAddress
  613. )
  614. {
  615. DEBUG ((DEBUG_INFO, "PCH AddConfigBlocks\n"));
  616. return AddComponentConfigBlocks (ConfigBlockTableAddress, &mPchIpBlocks[0], sizeof (mPchIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));
  617. }