PchPreMemPrintPolicy.c 15 KB

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  1. /** @file
  2. Print whole PCH_PREMEM_POLICY_PPI
  3. Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "PeiPchPolicyLibrary.h"
  7. #include <Library/ConfigBlockLib.h>
  8. /**
  9. Print PCH_GENERAL_PREMEM_CONFIG and serial out.
  10. @param[in] PchGeneralPreMemConfig Pointer to a PCH_GENERAL_PREMEM_CONFIG that provides the platform setting
  11. **/
  12. VOID
  13. PchPrintGeneralPreMemConfig (
  14. IN CONST PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig
  15. )
  16. {
  17. DEBUG ((DEBUG_INFO, "------------------ PCH General PreMem Config ------------------\n"));
  18. DEBUG ((DEBUG_INFO, " Port80Route= %x\n", PchGeneralPreMemConfig->Port80Route));
  19. }
  20. /**
  21. Print PCH_DCI_PREMEM_CONFIG and serial out.
  22. @param[in] DciPreMemConfig Pointer to a PCH_DCI_PREMEM_CONFIG that provides the platform setting
  23. **/
  24. VOID
  25. PchPrintDciPreMemConfig (
  26. IN CONST PCH_DCI_PREMEM_CONFIG *DciPreMemConfig
  27. )
  28. {
  29. DEBUG ((DEBUG_INFO, "------------------ PCH DCI PreMem Config ------------------\n"));
  30. DEBUG ((DEBUG_INFO, "PlatformDebugConsent = %x\n", DciPreMemConfig->PlatformDebugConsent));
  31. DEBUG ((DEBUG_INFO, "DciUsb3TypecUfpDbg = %x\n", DciPreMemConfig->DciUsb3TypecUfpDbg));
  32. }
  33. /**
  34. Print PCH_WDT_PREMEM_CONFIG and serial out.
  35. @param[in] WdtPreMemConfig Pointer to a PCH_WDT_PREMEM_CONFIG that provides the platform setting
  36. **/
  37. VOID
  38. PchPrintWdtPreMemConfig (
  39. IN CONST PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig
  40. )
  41. {
  42. DEBUG ((DEBUG_INFO, "------------------ PCH WDT PreMem Config ------------------\n"));
  43. DEBUG ((DEBUG_INFO, "DisableAndLock= %x\n", WdtPreMemConfig->DisableAndLock));
  44. }
  45. /**
  46. Print PCH_TRACE_HUB_CONFIG and serial out.
  47. @param[in] TraceHubConfig Pointer to a PCH_TRACE_HUB_CONFIG that provides the platform setting
  48. **/
  49. VOID
  50. PchPrintTraceHubPreMemConfig (
  51. IN CONST PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig
  52. )
  53. {
  54. DEBUG ((DEBUG_INFO, "------------------ PCH TraceHub PreMem Config ------------------\n"));
  55. DEBUG ((DEBUG_INFO, "EnableMode= %x\n", PchTraceHubPreMemConfig->EnableMode));
  56. DEBUG ((DEBUG_INFO, "MemReg0Size= %x\n", PchTraceHubPreMemConfig->MemReg0Size));
  57. DEBUG ((DEBUG_INFO, "MemReg1Size= %x\n", PchTraceHubPreMemConfig->MemReg1Size));
  58. }
  59. /**
  60. Print PCH_SMBUS_CONFIG and serial out.
  61. @param[in] SmbusConfig Pointer to a PCH_SMBUS_CONFIG that provides the platform setting
  62. **/
  63. VOID
  64. PchPrintSmbusPreMemConfig (
  65. IN CONST PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig
  66. )
  67. {
  68. UINT32 Index;
  69. DEBUG ((DEBUG_INFO, "------------------ PCH SMBUS PreMem Config ------------------\n"));
  70. DEBUG ((DEBUG_INFO, " Enable= %x\n", SmbusPreMemConfig->Enable));
  71. DEBUG ((DEBUG_INFO, " ArpEnable= %x\n", SmbusPreMemConfig->ArpEnable));
  72. DEBUG ((DEBUG_INFO, " DynamicPowerGating= %x\n", SmbusPreMemConfig->DynamicPowerGating));
  73. DEBUG ((DEBUG_INFO, " SpdWriteDisable= %x\n", SmbusPreMemConfig->SpdWriteDisable));
  74. DEBUG ((DEBUG_INFO, " SmbAlertEnable= %x\n", SmbusPreMemConfig->SmbAlertEnable));
  75. DEBUG ((DEBUG_INFO, " SmbusIoBase= %x\n", SmbusPreMemConfig->SmbusIoBase));
  76. DEBUG ((DEBUG_INFO, " NumRsvdSmbusAddresses= %x\n", SmbusPreMemConfig->NumRsvdSmbusAddresses));
  77. DEBUG ((DEBUG_INFO, " RsvdSmbusAddressTable= {"));
  78. for (Index = 0; Index < SmbusPreMemConfig->NumRsvdSmbusAddresses; ++Index) {
  79. DEBUG ((DEBUG_INFO, " %02xh", SmbusPreMemConfig->RsvdSmbusAddressTable[Index]));
  80. }
  81. DEBUG ((DEBUG_INFO, " }\n"));
  82. }
  83. /**
  84. Print PCH_LPC_PREMEM_CONFIG and serial out.
  85. @param[in] LpcPreMemConfig Pointer to a PCH_LPC_PREMEM_CONFIG that provides the platform setting
  86. **/
  87. VOID
  88. PchPrintLpcPreMemConfig (
  89. IN CONST PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig
  90. )
  91. {
  92. DEBUG ((DEBUG_INFO, "------------------ PCH LPC PreMem Config ------------------\n"));
  93. DEBUG ((DEBUG_INFO, "EnhancePort8xhDecoding= %x\n", LpcPreMemConfig->EnhancePort8xhDecoding));
  94. }
  95. /**
  96. Print PCH_HSIO_PCIE_PREMEM_CONFIG and serial out.
  97. @param[in] HsioPciePreMemConfig Pointer to a PCH_HSIO_PCIE_PREMEM_CONFIG that provides the platform setting
  98. **/
  99. VOID
  100. PchPrintHsioPciePreMemConfig (
  101. IN CONST PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig
  102. )
  103. {
  104. UINT32 Index;
  105. DEBUG ((DEBUG_INFO, "------------------ HSIO PCIE PreMem Config ------------------\n"));
  106. for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
  107. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioRxSetCtleEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable));
  108. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioRxSetCtle= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle));
  109. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DownscaleAmpEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEnable));
  110. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DownscaleAmp= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp));
  111. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DownscaleAmpEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEnable));
  112. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DownscaleAmp= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp));
  113. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen3DownscaleAmpEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEnable));
  114. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen3DownscaleAmp= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp));
  115. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DeEmphEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable));
  116. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DeEmph= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph));
  117. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph3p5Enable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable));
  118. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph3p5= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5));
  119. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph6p0Enable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable));
  120. DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph6p0= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0));
  121. }
  122. }
  123. /**
  124. Print PCH_HSIO_SATA_PREMEM_CONFIG and serial out.
  125. @param[in] SataCtrlIndex SATA controller index
  126. @param[in] HsioSataPreMemConfig Pointer to a PCH_HSIO_SATA_PREMEM_CONFIG that provides the platform setting
  127. **/
  128. VOID
  129. PchPrintHsioSataPreMemConfig (
  130. IN UINT8 SataCtrlIndex,
  131. IN CONST PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig
  132. )
  133. {
  134. UINT32 Index;
  135. DEBUG ((DEBUG_INFO, "---------------- HSIO SATA PreMem Config for controller %d ----------------\n", SataCtrlIndex));
  136. for (Index = 0; Index < GetPchMaxSataPortNum (SataCtrlIndex); Index++) {
  137. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMagEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEnable));
  138. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMag= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag));
  139. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMagEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEnable));
  140. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMag= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag));
  141. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMagEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable));
  142. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMag= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag));
  143. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmpEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable));
  144. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmp= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp));
  145. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmpEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable));
  146. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmp= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp));
  147. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmpEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmpEnable));
  148. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmp= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp));
  149. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmphEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable));
  150. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmph= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph));
  151. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmphEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable));
  152. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmph= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph));
  153. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmphEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable));
  154. DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmph= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph));
  155. }
  156. }
  157. /**
  158. Print PCH_PCIE_RP_PREMEM_CONFIG and serial out.
  159. @param[in] PcieRpPreMemConfig Pointer to a PCH_PCIE_RP_PREMEM_CONFIG that provides the platform setting
  160. **/
  161. VOID
  162. PchPrintPcieRpPreMemConfig (
  163. IN CONST PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig
  164. )
  165. {
  166. UINT32 Index;
  167. DEBUG ((DEBUG_INFO, "------------------ PCH PCIe RP PreMem Config ------------------\n"));
  168. for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
  169. DEBUG ((DEBUG_INFO, " Port[%d] RpEnabled= %x\n", Index, (PcieRpPreMemConfig->RpEnabledMask & (UINT32) (1 << Index)) != 0 ));
  170. }
  171. DEBUG ((DEBUG_INFO, " PcieImrEnabled= %x\n", PcieRpPreMemConfig->PcieImrEnabled));
  172. DEBUG ((DEBUG_INFO, " PcieImrSize= %d MB\n", PcieRpPreMemConfig->PcieImrSize));
  173. DEBUG ((DEBUG_INFO, " ImrRpSelection= %d\n", PcieRpPreMemConfig->ImrRpSelection));
  174. }
  175. /**
  176. Print PCH_HDAUDIO_PREMEM_CONFIG and serial out.
  177. @param[in] LpcPreMemConfig Pointer to a PCH_HDAUDIO_PREMEM_CONFIG that provides the platform setting
  178. **/
  179. VOID
  180. PchPrintHdAudioPreMemConfig (
  181. IN CONST PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig
  182. )
  183. {
  184. DEBUG ((DEBUG_INFO, "------------------ HD Audio PreMem Config ------------------\n"));
  185. DEBUG ((DEBUG_INFO, " Enable= %x\n", HdaPreMemConfig->Enable));
  186. }
  187. /**
  188. Print PCH_ISH_PREMEM_CONFIG and serial out.
  189. @param[in] IshPreMemConfig Pointer to a PCH_ISH_PREMEM_CONFIG that provides the platform setting
  190. **/
  191. VOID
  192. PchPrintIshPreMemConfig (
  193. IN CONST PCH_ISH_PREMEM_CONFIG *IshPreMemConfig
  194. )
  195. {
  196. DEBUG ((DEBUG_INFO, "------------------ ISH PreMem Config ------------------\n"));
  197. DEBUG ((DEBUG_INFO, " Enable= %x\n", IshPreMemConfig->Enable));
  198. }
  199. /**
  200. Print whole PCH_POLICY_PPI and serial out.
  201. @param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance
  202. **/
  203. VOID
  204. EFIAPI
  205. PchPreMemPrintPolicyPpi (
  206. IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
  207. )
  208. {
  209. DEBUG_CODE_BEGIN ();
  210. EFI_STATUS Status;
  211. PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig;
  212. PCH_DCI_PREMEM_CONFIG *DciPreMemConfig;
  213. PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig;
  214. PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig;
  215. PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig;
  216. PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig;
  217. PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig;
  218. PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig;
  219. PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;
  220. PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig;
  221. PCH_ISH_PREMEM_CONFIG *IshPreMemConfig;
  222. UINT8 SataCtrlIndex;
  223. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig);
  224. ASSERT_EFI_ERROR (Status);
  225. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gDciPreMemConfigGuid, (VOID *) &DciPreMemConfig);
  226. ASSERT_EFI_ERROR (Status);
  227. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gWatchDogPreMemConfigGuid, (VOID *) &WdtPreMemConfig);
  228. ASSERT_EFI_ERROR (Status);
  229. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchTraceHubPreMemConfigGuid, (VOID *) &PchTraceHubPreMemConfig);
  230. ASSERT_EFI_ERROR (Status);
  231. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSmbusPreMemConfigGuid, (VOID *) &SmbusPreMemConfig);
  232. ASSERT_EFI_ERROR (Status);
  233. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gLpcPreMemConfigGuid, (VOID *) &LpcPreMemConfig);
  234. ASSERT_EFI_ERROR (Status);
  235. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig);
  236. ASSERT_EFI_ERROR (Status);
  237. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
  238. ASSERT_EFI_ERROR (Status);
  239. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHdAudioPreMemConfigGuid, (VOID *) &HdaPreMemConfig);
  240. ASSERT_EFI_ERROR (Status);
  241. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gIshPreMemConfigGuid, (VOID *) &IshPreMemConfig);
  242. ASSERT_EFI_ERROR (Status);
  243. DEBUG ((DEBUG_INFO, "------------------------ PCH Print PreMemPolicy Start ------------------------\n"));
  244. DEBUG ((DEBUG_INFO, " Revision= %x\n", SiPreMemPolicyPpi->TableHeader.Header.Revision));
  245. PchPrintGeneralPreMemConfig (PchGeneralPreMemConfig);
  246. PchPrintDciPreMemConfig (DciPreMemConfig);
  247. PchPrintWdtPreMemConfig (WdtPreMemConfig);
  248. PchPrintTraceHubPreMemConfig (PchTraceHubPreMemConfig);
  249. PchPrintSmbusPreMemConfig (SmbusPreMemConfig);
  250. PchPrintLpcPreMemConfig (LpcPreMemConfig);
  251. PchPrintHsioPciePreMemConfig (HsioPciePreMemConfig);
  252. for (SataCtrlIndex = 0; SataCtrlIndex < GetPchMaxSataControllerNum (); SataCtrlIndex++) {
  253. HsioSataPreMemConfig = GetPchHsioSataPreMemConfig (SiPreMemPolicyPpi, SataCtrlIndex);
  254. PchPrintHsioSataPreMemConfig (SataCtrlIndex, HsioSataPreMemConfig);
  255. }
  256. PchPrintPcieRpPreMemConfig (PcieRpPreMemConfig);
  257. PchPrintHdAudioPreMemConfig (HdaPreMemConfig);
  258. PchPrintIshPreMemConfig (IshPreMemConfig);
  259. DEBUG ((DEBUG_INFO, "------------------------ PCH Print PreMemPolicy End --------------------------\n"));
  260. DEBUG_CODE_END ();
  261. }