PchInfoHob.h 2.3 KB

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  1. /** @file
  2. This file contains definitions of PCH Info HOB.
  3. Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _PCH_INFO_HOB_H_
  7. #define _PCH_INFO_HOB_H_
  8. extern EFI_GUID gPchInfoHobGuid;
  9. #define PCH_INFO_HOB_REVISION 2
  10. #pragma pack (push,1)
  11. /**
  12. This structure is used to provide the information of PCH controller.
  13. <b>Revision 1</b>:
  14. - Initial version.
  15. <b>Revision 2</b>:
  16. - Add CridSupport, CridOrgRid, and CridNewRid.
  17. <b>Revision 3</b>:
  18. - Added LaneReversal Field
  19. **/
  20. typedef struct {
  21. /**
  22. This member specifies the revision of the PCH Info HOB. This field is used
  23. to indicate backwards compatible changes to the protocol. Platform code that
  24. consumes this protocol must read the correct revision value to correctly interpret
  25. the content of the protocol fields.
  26. **/
  27. UINT8 Revision;
  28. UINT8 PcieControllerCfg[6];
  29. /**
  30. GbE over PCIe port number when GbE is enabled
  31. >0 - Root port number (1-based)
  32. 0 - GbE over PCIe disabled
  33. This information needs to be passed through HOB as FIA registers
  34. are not accessible with POSTBOOT_SAI
  35. **/
  36. UINT8 GbePciePortNumber;
  37. UINT32 PciePortFuses;
  38. /**
  39. Bit map for PCIe Root Port Lane setting. If bit is set it means that
  40. corresponding Root Port has its lane enabled.
  41. BIT0 - RP0, BIT1 - RP1, ...
  42. This information needs to be passed through HOB as FIA registers
  43. are not accessible with POSTBOOT_SAI
  44. **/
  45. UINT32 PciePortLaneEnabled;
  46. /**
  47. Publish Hpet BDF and IoApic BDF information for VTD.
  48. **/
  49. UINT32 HpetBusNum : 8;
  50. UINT32 HpetDevNum : 5;
  51. UINT32 HpetFuncNum : 3;
  52. UINT32 IoApicBusNum : 8;
  53. UINT32 IoApicDevNum : 5;
  54. UINT32 IoApicFuncNum : 3;
  55. /**
  56. Publish the CRID information.
  57. **/
  58. UINT32 CridOrgRid : 8;
  59. UINT32 CridNewRid : 8;
  60. UINT32 CridSupport : 1;
  61. UINT32 Rsvdbits : 15;
  62. /**
  63. This member specifies if lane reversal is enabled on the specific
  64. Pcie Root port controller.
  65. **/
  66. UINT8 PcieControllerLaneReversal[6];
  67. } PCH_INFO_HOB;
  68. #pragma pack (pop)
  69. #endif // _PCH_INFO_HOB_H_