PeiSiPolicyUpdate.c 17 KB

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  1. /** @file
  2. This file is SampleCode of the library for Intel Silicon PEI
  3. Platform Policy initialization.
  4. Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include "PeiSiPolicyUpdate.h"
  8. #include <MeChipset.h>
  9. #include <Library/PchInfoLib.h>
  10. #include <Library/PeiServicesLib.h>
  11. #include <Library/SiPolicyLib.h>
  12. #include <Library/MemoryAllocationLib.h>
  13. #include <Library/ConfigBlockLib.h>
  14. STATIC SVID_SID_INIT_ENTRY mCdfSsidTablePtr[] = {
  15. //
  16. // SA Device(s)
  17. //
  18. {{{PCI_SVID_OFFSET, SA_MC_FUN, SA_MC_DEV, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  19. {{{R_SA_PEG_SS_OFFSET, SA_PEG0_FUN_NUM, SA_PEG0_DEV_NUM, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  20. {{{R_SA_PEG_SS_OFFSET, SA_PEG1_FUN_NUM, SA_PEG1_DEV_NUM, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  21. {{{R_SA_PEG_SS_OFFSET, SA_PEG2_FUN_NUM, SA_PEG2_DEV_NUM, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  22. {{{PCI_SVID_OFFSET, SA_IGD_FUN_0, SA_IGD_DEV, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  23. {{{PCI_SVID_OFFSET, SA_IPU_FUN_NUM, SA_IPU_DEV_NUM, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  24. {{{PCI_SVID_OFFSET, SA_GNA_FUN_NUM, SA_GNA_DEV_NUM, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  25. //
  26. // PCH Device(s)
  27. //
  28. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LPC, PCI_DEVICE_NUMBER_PCH_LPC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  29. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_P2SB, PCI_DEVICE_NUMBER_PCH_P2SB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  30. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_PMC, PCI_DEVICE_NUMBER_PCH_PMC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  31. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_HDA, PCI_DEVICE_NUMBER_PCH_HDA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  32. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_1, PCI_DEVICE_NUMBER_CDF_PCH_SATA_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  33. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_2, PCI_DEVICE_NUMBER_CDF_PCH_SATA_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  34. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_3, PCI_DEVICE_NUMBER_CDF_PCH_SATA_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  35. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SMBUS, PCI_DEVICE_NUMBER_PCH_SMBUS, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  36. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SPI, PCI_DEVICE_NUMBER_PCH_SPI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  37. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_TRACE_HUB, PCI_DEVICE_NUMBER_PCH_TRACE_HUB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  38. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XHCI, PCI_DEVICE_NUMBER_PCH_XHCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  39. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XDCI, PCI_DEVICE_NUMBER_PCH_XDCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  40. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_THERMAL, PCI_DEVICE_NUMBER_PCH_THERMAL, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  41. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  42. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  43. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  44. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  45. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  46. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  47. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  48. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  49. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  50. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  51. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  52. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  53. };
  54. STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[] = {
  55. //
  56. // SA Device(s)
  57. //
  58. {{{PCI_SVID_OFFSET, SA_MC_FUN, SA_MC_DEV, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  59. {{{R_SA_PEG_SS_OFFSET, SA_PEG0_FUN_NUM, SA_PEG0_DEV_NUM, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  60. {{{R_SA_PEG_SS_OFFSET, SA_PEG1_FUN_NUM, SA_PEG1_DEV_NUM, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  61. {{{R_SA_PEG_SS_OFFSET, SA_PEG2_FUN_NUM, SA_PEG2_DEV_NUM, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  62. {{{PCI_SVID_OFFSET, SA_IGD_FUN_0, SA_IGD_DEV, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  63. {{{PCI_SVID_OFFSET, SA_IPU_FUN_NUM, SA_IPU_DEV_NUM, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  64. {{{PCI_SVID_OFFSET, SA_GNA_FUN_NUM, SA_GNA_DEV_NUM, SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0},
  65. //
  66. // PCH Device(s)
  67. //
  68. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LPC, PCI_DEVICE_NUMBER_PCH_LPC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  69. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_P2SB, PCI_DEVICE_NUMBER_PCH_P2SB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  70. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_PMC, PCI_DEVICE_NUMBER_PCH_PMC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  71. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_HDA, PCI_DEVICE_NUMBER_PCH_HDA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  72. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SATA, PCI_DEVICE_NUMBER_PCH_SATA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  73. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SMBUS, PCI_DEVICE_NUMBER_PCH_SMBUS, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  74. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SPI, PCI_DEVICE_NUMBER_PCH_SPI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  75. //
  76. // Skip PCH LAN controller
  77. // PCH LAN SVID/SID may be loaded automatically from the NVM Word 0Ch/0Bh upon power up or reset
  78. // depending on the "Load Subsystem ID" bit field in NVM word 0Ah
  79. //
  80. //{{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LAN, PCI_DEVICE_NUMBER_PCH_LAN, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  81. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_TRACE_HUB, PCI_DEVICE_NUMBER_PCH_TRACE_HUB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  82. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  83. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  84. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  85. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  86. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_CNL_SCS_SDCARD, PCI_DEVICE_NUMBER_PCH_CNL_SCS_SDCARD, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  87. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XHCI, PCI_DEVICE_NUMBER_PCH_XHCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  88. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XDCI, PCI_DEVICE_NUMBER_PCH_XDCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  89. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_THERMAL, PCI_DEVICE_NUMBER_PCH_THERMAL, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  90. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_ISH, PCI_DEVICE_NUMBER_PCH_ISH, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  91. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  92. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  93. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  94. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  95. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  96. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  97. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  98. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  99. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  100. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  101. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  102. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  103. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  104. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  105. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  106. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  107. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  108. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  109. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  110. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  111. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_21, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  112. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_22, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  113. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_23, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  114. {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_24, PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  115. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  116. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  117. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  118. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  119. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  120. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  121. {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4, PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  122. //
  123. // ME Device(s)
  124. //
  125. {{{PCI_SVID_OFFSET, HECI_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  126. {{{PCI_SVID_OFFSET, HECI2_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  127. {{{PCI_SVID_OFFSET, IDER_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  128. {{{PCI_SVID_OFFSET, SOL_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  129. {{{PCI_SVID_OFFSET, HECI3_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0},
  130. {{{PCI_SVID_OFFSET, HECI4_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}
  131. };
  132. /**
  133. This function performs Silicon PEI Policy initialization.
  134. @param[in] SiPolicy The Silicon Policy PPI instance
  135. @retval EFI_SUCCESS The function completed successfully
  136. **/
  137. EFI_STATUS
  138. EFIAPI
  139. UpdatePeiSiPolicy (
  140. IN OUT SI_POLICY_PPI *SiPolicy
  141. )
  142. {
  143. EFI_STATUS Status;
  144. SI_CONFIG *SiConfig;
  145. Status = GetConfigBlock ((VOID *) SiPolicy, &gSiConfigGuid, (VOID *) &SiConfig);
  146. ASSERT_EFI_ERROR (Status);
  147. SiConfig->CsmFlag = 0;
  148. if (IsCdfPch ()) {
  149. SiConfig->SsidTablePtr = (UINT32*)(UINTN) mCdfSsidTablePtr;
  150. SiConfig->NumberOfSsidTableEntry = (sizeof (mCdfSsidTablePtr) / sizeof (SVID_SID_INIT_ENTRY));
  151. } else {
  152. SiConfig->SsidTablePtr = (UINT32*)(UINTN) mSsidTablePtr;
  153. SiConfig->NumberOfSsidTableEntry = (sizeof (mSsidTablePtr) / sizeof (SVID_SID_INIT_ENTRY));
  154. }
  155. return EFI_SUCCESS;
  156. }