PeiSaPolicyUpdatePreMem.c 8.8 KB

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  1. /** @file
  2. Platform Stage System Agent initialization.
  3. Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "PeiSaPolicyUpdate.h"
  7. #include <CpuRegs.h>
  8. #include <Register/Cpuid.h>
  9. #include <Library/CpuPlatformLib.h>
  10. #include <Guid/MemoryTypeInformation.h>
  11. #include <Guid/MemoryOverwriteControl.h>
  12. #include <Library/HobLib.h>
  13. #include <Platform.h>
  14. #include <PlatformBoardConfig.h>
  15. #include <Library/SiPolicyLib.h>
  16. #include <Library/BaseMemoryLib.h>
  17. #include <Library/MemoryAllocationLib.h>
  18. #include <Library/PeiSaPolicyLib.h>
  19. #include <Library/GpioLib.h>
  20. #include <Library/ConfigBlockLib.h>
  21. ///
  22. /// Memory Reserved should be between 125% to 150% of the Current required memory
  23. /// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
  24. ///
  25. GLOBAL_REMOVE_IF_UNREFERENCED STATIC EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  26. { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) }, // ASL
  27. { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) }, // ACPI NVS (including S3 related)
  28. { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) }, // BIOS Reserved (including S3 related)
  29. { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize) }, // Runtime Service Data
  30. { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize) }, // Runtime Service Code
  31. { EfiMaxMemoryType, 0 }
  32. };
  33. /**
  34. UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization
  35. @param[in out] SiPreMemPolicyPpi - SI_PREMEM_POLICY PPI
  36. @retval EFI_SUCCESS The policy is installed and initialized.
  37. **/
  38. EFI_STATUS
  39. UpdatePeiSaPolicyPreMem (
  40. IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
  41. )
  42. {
  43. EFI_STATUS Status;
  44. SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig = NULL;
  45. MEMORY_CONFIG_NO_CRC *MemConfigNoCrc = NULL;
  46. SA_MEMORY_RCOMP *RcompData;
  47. WDT_PPI *gWdtPei;
  48. UINT8 Index;
  49. UINTN DataSize;
  50. EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
  51. EFI_BOOT_MODE BootMode;
  52. UINT32 TraceHubTotalMemSize;
  53. GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig = NULL;
  54. MEMORY_CONFIGURATION *MemConfig = NULL;
  55. PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig = NULL;
  56. SWITCHABLE_GRAPHICS_CONFIG *SgGpioData = NULL;
  57. IPU_PREMEM_CONFIG *IpuPreMemPolicy = NULL;
  58. OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig = NULL;
  59. VTD_CONFIG *Vtd = NULL;
  60. UINT32 ProcessorTraceTotalMemSize;
  61. TraceHubTotalMemSize = 0;
  62. ProcessorTraceTotalMemSize = 0;
  63. DEBUG((DEBUG_INFO, "Entering Get Config Block function call from UpdatePeiSaPolicyPreMem\n"));
  64. Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
  65. ASSERT_EFI_ERROR(Status);
  66. Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gGraphicsPeiPreMemConfigGuid, (VOID *) &GtPreMemConfig);
  67. ASSERT_EFI_ERROR(Status);
  68. Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
  69. ASSERT_EFI_ERROR(Status);
  70. Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaPciePeiPreMemConfigGuid, (VOID *) &PciePeiPreMemConfig);
  71. ASSERT_EFI_ERROR(Status);
  72. Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSwitchableGraphicsConfigGuid, (VOID *) &SgGpioData);
  73. ASSERT_EFI_ERROR(Status);
  74. Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gIpuPreMemConfigGuid, (VOID *) &IpuPreMemPolicy);
  75. ASSERT_EFI_ERROR (Status);
  76. Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
  77. ASSERT_EFI_ERROR(Status);
  78. Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaOverclockingPreMemConfigGuid, (VOID *) &OcPreMemConfig);
  79. ASSERT_EFI_ERROR(Status);
  80. Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid, (VOID *)&Vtd);
  81. ASSERT_EFI_ERROR(Status);
  82. RcompData = MemConfigNoCrc->RcompData;
  83. //
  84. // Locate WDT_PPI (ICC WDT PPI)
  85. //
  86. gWdtPei = NULL;
  87. Status = PeiServicesLocatePpi(
  88. &gWdtPpiGuid,
  89. 0,
  90. NULL,
  91. (VOID **) &gWdtPei
  92. );
  93. Status = PeiServicesGetBootMode(&BootMode);
  94. ASSERT_EFI_ERROR(Status);
  95. MiscPeiPreMemConfig->S3DataPtr = NULL;
  96. MiscPeiPreMemConfig->UserBd = 0; // It's a CRB mobile board by default (btCRBMB)
  97. PcdSetBoolS (PcdMobileDramPresent, (BOOLEAN) (MemConfig->MobilePlatform));
  98. MiscPeiPreMemConfig->SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0);
  99. MiscPeiPreMemConfig->SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1);
  100. MiscPeiPreMemConfig->SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2);
  101. MiscPeiPreMemConfig->SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3);
  102. MemConfig->CaVrefConfig = PcdGet8 (PcdMrcCaVrefConfig);
  103. MemConfig->DualDimmPerChannelBoardType = PcdGetBool (PcdDualDimmPerChannelBoardType);
  104. if (PcdGet32 (PcdMrcRcompResistor)) {
  105. CopyMem((VOID *)RcompData->RcompResistor, (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor), sizeof (RcompData->RcompResistor));
  106. }
  107. if (PcdGet32 (PcdMrcRcompTarget)) {
  108. CopyMem((VOID *)RcompData->RcompTarget, (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget), sizeof (RcompData->RcompTarget));
  109. }
  110. if (PcdGet32 (PcdMrcDqByteMap)) {
  111. CopyMem((VOID *)MemConfigNoCrc->DqByteMap, (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap), sizeof (UINT8)* SA_MC_MAX_CHANNELS * SA_MRC_ITERATION_MAX * 2);
  112. }
  113. if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) {
  114. CopyMem((VOID *)MemConfigNoCrc->DqsMap, (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram), sizeof (UINT8)* SA_MC_MAX_CHANNELS * SA_MC_MAX_BYTES_NO_ECC);
  115. }
  116. if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) {
  117. MemConfig->DqPinsInterleaved = PcdGetBool (PcdMrcDqPinsInterleaved);
  118. }
  119. if (PcdGet32 (PcdMrcSpdData)) {
  120. CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
  121. CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
  122. }
  123. MiscPeiPreMemConfig->MchBar = (UINTN) PcdGet64 (PcdMchBaseAddress);
  124. MiscPeiPreMemConfig->DmiBar = (UINTN) PcdGet64 (PcdDmiBaseAddress);
  125. MiscPeiPreMemConfig->EpBar = (UINTN) PcdGet64 (PcdEpBaseAddress);
  126. MiscPeiPreMemConfig->EdramBar = (UINTN) PcdGet64 (PcdEdramBaseAddress);
  127. MiscPeiPreMemConfig->SmbusBar = PcdGet16(PcdSmbusBaseAddress);
  128. MiscPeiPreMemConfig->TsegSize = PcdGet32(PcdTsegSize);
  129. MiscPeiPreMemConfig->UserBd = PcdGet8 (PcdSaMiscUserBd);
  130. MiscPeiPreMemConfig->MmioSizeAdjustment = PcdGet16 (PcdSaMiscMmioSizeAdjustment);
  131. if (PcdGetBool (PcdPegGpioResetControl)) {
  132. PciePeiPreMemConfig->PegGpioData.GpioSupport = PcdGetBool (PcdPegGpioResetSupoort);
  133. } else {
  134. }
  135. PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.GpioPad = PcdGet32 (PcdPeg0ResetGpioPad);
  136. PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.Active = PcdGetBool (PcdPeg0ResetGpioActive);
  137. PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.GpioPad = PcdGet32 (PcdPeg3ResetGpioPad);
  138. PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.Active = PcdGetBool (PcdPeg3ResetGpioActive);
  139. MemConfig->CkeRankMapping = 0xAA;
  140. ///
  141. /// Initialize the VTD Configuration
  142. ///
  143. Vtd->VtdDisable = 0;
  144. MemConfig->RMT = 1;
  145. MemConfig->UserPowerWeightsEn = 0;
  146. MemConfig->RaplLim2WindY = 0x0A;
  147. MemConfig->ExitOnFailure = 1;
  148. MemConfigNoCrc->PlatformMemorySize = PEI_MIN_MEMORY_SIZE + TraceHubTotalMemSize + ProcessorTraceTotalMemSize;
  149. DataSize = sizeof (mDefaultMemoryTypeInformation);
  150. CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize);
  151. if (BootMode != BOOT_IN_RECOVERY_MODE) {
  152. for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) {
  153. MemConfigNoCrc->PlatformMemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
  154. }
  155. OcPreMemConfig->GtMaxOcRatio = 0;
  156. OcPreMemConfig->GtVoltageMode = 0;
  157. OcPreMemConfig->GtVoltageOverride = 0;
  158. OcPreMemConfig->GtExtraTurboVoltage = 0;
  159. OcPreMemConfig->GtVoltageOffset = 0;
  160. OcPreMemConfig->SaVoltageOffset = 0;
  161. OcPreMemConfig->GtusMaxOcRatio = 0;
  162. OcPreMemConfig->GtusVoltageMode = 0;
  163. OcPreMemConfig->GtusVoltageOverride = 0;
  164. OcPreMemConfig->GtusExtraTurboVoltage = 0;
  165. OcPreMemConfig->GtusVoltageOffset = 0;
  166. ///
  167. /// Build the GUID'd HOB for DXE
  168. ///
  169. BuildGuidDataHob (
  170. &gEfiMemoryTypeInformationGuid,
  171. MemoryData,
  172. DataSize
  173. );
  174. }
  175. return EFI_SUCCESS;
  176. }