PeiPchPolicyUpdate.c 21 KB

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  1. /** @file
  2. This file is SampleCode of the library for Intel PCH PEI Policy initialization.
  3. Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "PeiPchPolicyUpdate.h"
  7. #include <Library/BaseMemoryLib.h>
  8. #include <Library/HdaVerbTableLib.h>
  9. #include <Library/MemoryAllocationLib.h>
  10. #include <Library/HobLib.h>
  11. #include <Library/PchGbeLib.h>
  12. #include <Library/PchInfoLib.h>
  13. #include <Library/SataLib.h>
  14. #include <Library/PchPcrLib.h>
  15. #include <Library/PchSerialIoLib.h>
  16. #include <Library/PchPcieRpLib.h>
  17. #include <Ppi/Spi.h>
  18. #include <GpioConfig.h>
  19. #include <Library/DebugLib.h>
  20. #include <Library/PchGbeLib.h>
  21. #include <PlatformBoardConfig.h>
  22. #include <Library/CnviLib.h>
  23. #include <Register/PchRegsLpcCnl.h>
  24. #include <PcieDeviceOverrideTable.h>
  25. #include <Library/ConfigBlockLib.h>
  26. VOID
  27. UpdatePcieClockInfo (
  28. PCH_PCIE_CONFIG *PcieRpConfig,
  29. UINTN Index,
  30. UINT64 Data
  31. )
  32. {
  33. PCD64_BLOB Pcd64;
  34. Pcd64.Blob = Data;
  35. DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupported));
  36. PcieRpConfig->PcieClock[Index].Usage = (UINT8)Pcd64.PcieClock.ClockUsage;
  37. if (Pcd64.PcieClock.ClkReqSupported) {
  38. PcieRpConfig->PcieClock[Index].ClkReq = (UINT8)Index;
  39. } else {
  40. PcieRpConfig->PcieClock[Index].ClkReq = 0xFF;
  41. }
  42. }
  43. /**
  44. This is helper function for getting I2C Pads Internal Termination settings from Pcd
  45. @param[in] Index I2C Controller Index
  46. **/
  47. UINT8
  48. GetSerialIoI2cPadsTerminationFromPcd (
  49. IN UINT8 Index
  50. )
  51. {
  52. switch (Index) {
  53. case 0:
  54. return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm);
  55. case 1:
  56. return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm);
  57. case 2:
  58. return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm);
  59. case 3:
  60. return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm);
  61. case 4:
  62. return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm);
  63. case 5:
  64. return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm);
  65. default:
  66. ASSERT (FALSE); // Invalid I2C Controller Index
  67. }
  68. return 0;
  69. }
  70. /**
  71. This is a helper function for updating USB Policy according to Blob data
  72. @param[in] UsbConfig Pointer to USB_CONFIG data buffer
  73. @param[in] PortIndex USB Port index
  74. @param[in] Data32 Blob containing USB2 Afe (PCD32_BLOB) data
  75. **/
  76. VOID
  77. UpdateUsb20AfePolicy (
  78. IN USB_CONFIG *UsbConfig,
  79. IN UINT8 PortIndex,
  80. UINT32 Data32
  81. )
  82. {
  83. PCD32_BLOB Pcd32;
  84. Pcd32.Blob = Data32;
  85. if (PortIndex < MAX_USB2_PORTS && Pcd32.Info.Petxiset != 0) {
  86. UsbConfig->PortUsb20[PortIndex].Afe.Petxiset = Pcd32.Info.Petxiset;
  87. UsbConfig->PortUsb20[PortIndex].Afe.Txiset = Pcd32.Info.Txiset;
  88. UsbConfig->PortUsb20[PortIndex].Afe.Predeemp = Pcd32.Info.Predeemp;
  89. UsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit = Pcd32.Info.Pehalfbit;
  90. }
  91. }
  92. /**
  93. This function updates USB Policy per port OC Pin number
  94. @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
  95. @param[in] PortIndex USB Port index
  96. @param[in] Pin OverCurrent pin number
  97. **/
  98. VOID
  99. UpdateUsb20OverCurrentPolicy (
  100. IN USB_CONFIG *UsbConfig,
  101. IN UINT8 PortIndex,
  102. UINT8 Pin
  103. )
  104. {
  105. if (PortIndex < MAX_USB2_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin == UsbOverCurrentPinSkip))) {
  106. UsbConfig->PortUsb20[PortIndex].OverCurrentPin = Pin;
  107. } else {
  108. if (PortIndex >= MAX_USB2_PORTS) {
  109. DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: USB2 port number %d is not a valid USB2 port number\n", PortIndex));
  110. } else {
  111. DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: Invalid OverCurrent pin specified USB2 port %d\n", PortIndex));
  112. }
  113. }
  114. }
  115. /**
  116. This function updates USB Policy per port OC Pin number
  117. @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
  118. @param[in] PortIndex USB Port index
  119. @param[in] Pin OverCurrent pin number
  120. **/
  121. VOID
  122. UpdateUsb30OverCurrentPolicy (
  123. IN USB_CONFIG *UsbConfig,
  124. IN UINT8 PortIndex,
  125. UINT8 Pin
  126. )
  127. {
  128. if (PortIndex < MAX_USB3_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin == UsbOverCurrentPinSkip))) {
  129. UsbConfig->PortUsb30[PortIndex].OverCurrentPin = Pin;
  130. } else {
  131. if (PortIndex >= MAX_USB2_PORTS) {
  132. DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: USB3 port number %d is not a valid USB3 port number\n", PortIndex));
  133. } else {
  134. DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: Invalid OverCurrent pin specified USB3 port %d\n", PortIndex));
  135. }
  136. }
  137. }
  138. /**
  139. This function performs PCH USB Platform Policy initialization
  140. @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
  141. @param[in] PchSetup Pointer to PCH_SETUP data buffer
  142. **/
  143. VOID
  144. UpdatePchUsbConfig (
  145. IN USB_CONFIG *UsbConfig
  146. )
  147. {
  148. UINTN PortIndex;
  149. UsbConfig->OverCurrentEnable = TRUE;
  150. for (PortIndex = 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortIndex++) {
  151. UsbConfig->PortUsb20[PortIndex].Enable = TRUE;
  152. }
  153. for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {
  154. UsbConfig->PortUsb30[PortIndex].Enable = TRUE;
  155. }
  156. UsbConfig->XdciConfig.Enable = FALSE;
  157. //
  158. // USB2 AFE settings.
  159. //
  160. UpdateUsb20AfePolicy (UsbConfig, 0, PcdGet32 (PcdUsb20Port0Afe));
  161. UpdateUsb20AfePolicy (UsbConfig, 1, PcdGet32 (PcdUsb20Port1Afe));
  162. UpdateUsb20AfePolicy (UsbConfig, 2, PcdGet32 (PcdUsb20Port2Afe));
  163. UpdateUsb20AfePolicy (UsbConfig, 3, PcdGet32 (PcdUsb20Port3Afe));
  164. UpdateUsb20AfePolicy (UsbConfig, 4, PcdGet32 (PcdUsb20Port4Afe));
  165. UpdateUsb20AfePolicy (UsbConfig, 5, PcdGet32 (PcdUsb20Port5Afe));
  166. UpdateUsb20AfePolicy (UsbConfig, 6, PcdGet32 (PcdUsb20Port6Afe));
  167. UpdateUsb20AfePolicy (UsbConfig, 7, PcdGet32 (PcdUsb20Port7Afe));
  168. UpdateUsb20AfePolicy (UsbConfig, 8, PcdGet32 (PcdUsb20Port8Afe));
  169. UpdateUsb20AfePolicy (UsbConfig, 9, PcdGet32 (PcdUsb20Port9Afe));
  170. UpdateUsb20AfePolicy (UsbConfig,10, PcdGet32 (PcdUsb20Port10Afe));
  171. UpdateUsb20AfePolicy (UsbConfig,11, PcdGet32 (PcdUsb20Port11Afe));
  172. UpdateUsb20AfePolicy (UsbConfig,12, PcdGet32 (PcdUsb20Port12Afe));
  173. UpdateUsb20AfePolicy (UsbConfig,13, PcdGet32 (PcdUsb20Port13Afe));
  174. UpdateUsb20AfePolicy (UsbConfig,14, PcdGet32 (PcdUsb20Port14Afe));
  175. UpdateUsb20AfePolicy (UsbConfig,15, PcdGet32 (PcdUsb20Port15Afe));
  176. //
  177. // Platform Board programming per the layout of each port.
  178. //
  179. UpdateUsb20OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb20OverCurrentPinPort0));
  180. UpdateUsb20OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb20OverCurrentPinPort1));
  181. UpdateUsb20OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb20OverCurrentPinPort2));
  182. UpdateUsb20OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb20OverCurrentPinPort3));
  183. UpdateUsb20OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb20OverCurrentPinPort4));
  184. UpdateUsb20OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb20OverCurrentPinPort5));
  185. UpdateUsb20OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb20OverCurrentPinPort6));
  186. UpdateUsb20OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb20OverCurrentPinPort7));
  187. UpdateUsb20OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb20OverCurrentPinPort8));
  188. UpdateUsb20OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb20OverCurrentPinPort9));
  189. UpdateUsb20OverCurrentPolicy (UsbConfig,10, PcdGet8 (PcdUsb20OverCurrentPinPort10));
  190. UpdateUsb20OverCurrentPolicy (UsbConfig,11, PcdGet8 (PcdUsb20OverCurrentPinPort11));
  191. UpdateUsb20OverCurrentPolicy (UsbConfig,12, PcdGet8 (PcdUsb20OverCurrentPinPort12));
  192. UpdateUsb20OverCurrentPolicy (UsbConfig,13, PcdGet8 (PcdUsb20OverCurrentPinPort13));
  193. UpdateUsb20OverCurrentPolicy (UsbConfig,14, PcdGet8 (PcdUsb20OverCurrentPinPort14));
  194. UpdateUsb20OverCurrentPolicy (UsbConfig,15, PcdGet8 (PcdUsb20OverCurrentPinPort15));
  195. UpdateUsb30OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb30OverCurrentPinPort0));
  196. UpdateUsb30OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb30OverCurrentPinPort1));
  197. UpdateUsb30OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb30OverCurrentPinPort2));
  198. UpdateUsb30OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb30OverCurrentPinPort3));
  199. UpdateUsb30OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb30OverCurrentPinPort4));
  200. UpdateUsb30OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb30OverCurrentPinPort5));
  201. UpdateUsb30OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb30OverCurrentPinPort6));
  202. UpdateUsb30OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb30OverCurrentPinPort7));
  203. UpdateUsb30OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb30OverCurrentPinPort8));
  204. UpdateUsb30OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb30OverCurrentPinPort9));
  205. }
  206. /**
  207. Return if input ImageGuid belongs to system FMP GUID list.
  208. @param[in] ImageGuid A pointer to GUID
  209. @retval TRUE ImageGuid is in the list of PcdSystemFmpCapsuleImageTypeIdGuid
  210. @retval FALSE ImageGuid is not in the list of PcdSystemFmpCapsuleImageTypeIdGuid
  211. **/
  212. BOOLEAN
  213. IsSystemFmpGuid (
  214. IN GUID *ImageGuid
  215. )
  216. {
  217. GUID *Guid;
  218. UINTN Count;
  219. UINTN Index;
  220. Guid = PcdGetPtr (PcdSystemFmpCapsuleImageTypeIdGuid);
  221. Count = PcdGetSize (PcdSystemFmpCapsuleImageTypeIdGuid) / sizeof (GUID);
  222. for (Index = 0; Index < Count; Index++, Guid++) {
  223. if (CompareGuid (ImageGuid, Guid)) {
  224. return TRUE;
  225. }
  226. }
  227. return FALSE;
  228. }
  229. /**
  230. This function performs PCH PEI Policy initialization.
  231. @param[in, out] SiPolicy The SI Policy PPI instance
  232. @retval EFI_SUCCESS The PPI is installed and initialized.
  233. @retval EFI ERRORS The PPI is not successfully installed.
  234. @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
  235. **/
  236. EFI_STATUS
  237. EFIAPI
  238. UpdatePeiPchPolicy (
  239. IN OUT SI_POLICY_PPI *SiPolicy
  240. )
  241. {
  242. EFI_STATUS Status;
  243. UINT8 Index;
  244. DMI_HW_WIDTH_CONTROL *DmiHaAWC;
  245. PCH_GENERAL_CONFIG *PchGeneralConfig;
  246. PCH_PCIE_CONFIG *PcieRpConfig;
  247. PCH_SATA_CONFIG *SataConfig;
  248. PCH_IOAPIC_CONFIG *IoApicConfig;
  249. PCH_DMI_CONFIG *DmiConfig;
  250. PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig;
  251. PCH_HDAUDIO_CONFIG *HdAudioConfig;
  252. PCH_INTERRUPT_CONFIG *InterruptConfig;
  253. PCH_ISH_CONFIG *IshConfig;
  254. PCH_LAN_CONFIG *LanConfig;
  255. PCH_LOCK_DOWN_CONFIG *LockDownConfig;
  256. PCH_PM_CONFIG *PmConfig;
  257. PCH_SCS_CONFIG *ScsConfig;
  258. PCH_SERIAL_IO_CONFIG *SerialIoConfig;
  259. PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;
  260. PCH_THERMAL_CONFIG *ThermalConfig;
  261. USB_CONFIG *UsbConfig;
  262. PCH_ESPI_CONFIG *EspiConfig;
  263. PCH_CNVI_CONFIG *CnviConfig;
  264. SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
  265. Status = GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
  266. ASSERT_EFI_ERROR (Status);
  267. Status = GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID *) &PcieRpConfig);
  268. ASSERT_EFI_ERROR (Status);
  269. Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig);
  270. ASSERT_EFI_ERROR (Status);
  271. Status = GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID *) &IoApicConfig);
  272. ASSERT_EFI_ERROR (Status);
  273. Status = GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) &DmiConfig);
  274. ASSERT_EFI_ERROR (Status);
  275. Status = GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig);
  276. ASSERT_EFI_ERROR (Status);
  277. Status = GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig);
  278. ASSERT_EFI_ERROR (Status);
  279. Status = GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VOID *) &InterruptConfig);
  280. ASSERT_EFI_ERROR (Status);
  281. Status = GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) &IshConfig);
  282. ASSERT_EFI_ERROR (Status);
  283. Status = GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) &LanConfig);
  284. ASSERT_EFI_ERROR (Status);
  285. Status = GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
  286. ASSERT_EFI_ERROR (Status);
  287. Status = GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &PmConfig);
  288. ASSERT_EFI_ERROR (Status);
  289. Status = GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) &ScsConfig);
  290. ASSERT_EFI_ERROR (Status);
  291. Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
  292. ASSERT_EFI_ERROR (Status);
  293. Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VOID *) &SerialIrqConfig);
  294. ASSERT_EFI_ERROR (Status);
  295. Status = GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID *) &ThermalConfig);
  296. ASSERT_EFI_ERROR (Status);
  297. Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig);
  298. ASSERT_EFI_ERROR (Status);
  299. Status = GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID *) &EspiConfig);
  300. ASSERT_EFI_ERROR (Status);
  301. Status = GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *) &CnviConfig);
  302. ASSERT_EFI_ERROR (Status);
  303. Status = PeiServicesLocatePpi (
  304. &gSiPreMemPolicyPpiGuid,
  305. 0,
  306. NULL,
  307. (VOID **) &SiPreMemPolicyPpi
  308. );
  309. ASSERT_EFI_ERROR (Status);
  310. DmiConfig->PwrOptEnable = TRUE;
  311. PmConfig->PchSlpS3MinAssert = 0;
  312. PmConfig->PchSlpS4MinAssert = 0;
  313. PmConfig->PchSlpSusMinAssert = 0;
  314. PmConfig->PchSlpAMinAssert = 0;
  315. SataConfig->ThermalThrottling.P1T3M = 3;
  316. SataConfig->ThermalThrottling.P1T2M = 2;
  317. SataConfig->ThermalThrottling.P1T1M = 1;
  318. SataConfig->ThermalThrottling.P0T3M = 3;
  319. SataConfig->ThermalThrottling.P0T2M = 2;
  320. SataConfig->ThermalThrottling.P0T1M = 1;
  321. UpdatePcieClockInfo (PcieRpConfig, 0, PcdGet64 (PcdPcieClock0));
  322. UpdatePcieClockInfo (PcieRpConfig, 1, PcdGet64 (PcdPcieClock1));
  323. UpdatePcieClockInfo (PcieRpConfig, 2, PcdGet64 (PcdPcieClock2));
  324. UpdatePcieClockInfo (PcieRpConfig, 3, PcdGet64 (PcdPcieClock3));
  325. UpdatePcieClockInfo (PcieRpConfig, 4, PcdGet64 (PcdPcieClock4));
  326. UpdatePcieClockInfo (PcieRpConfig, 5, PcdGet64 (PcdPcieClock5));
  327. UpdatePcieClockInfo (PcieRpConfig, 6, PcdGet64 (PcdPcieClock6));
  328. UpdatePcieClockInfo (PcieRpConfig, 7, PcdGet64 (PcdPcieClock7));
  329. UpdatePcieClockInfo (PcieRpConfig, 8, PcdGet64 (PcdPcieClock8));
  330. UpdatePcieClockInfo (PcieRpConfig, 9, PcdGet64 (PcdPcieClock9));
  331. UpdatePcieClockInfo (PcieRpConfig, 10, PcdGet64 (PcdPcieClock10));
  332. UpdatePcieClockInfo (PcieRpConfig, 11, PcdGet64 (PcdPcieClock11));
  333. UpdatePcieClockInfo (PcieRpConfig, 12, PcdGet64 (PcdPcieClock12));
  334. UpdatePcieClockInfo (PcieRpConfig, 13, PcdGet64 (PcdPcieClock13));
  335. UpdatePcieClockInfo (PcieRpConfig, 14, PcdGet64 (PcdPcieClock14));
  336. UpdatePcieClockInfo (PcieRpConfig, 15, PcdGet64 (PcdPcieClock15));
  337. PcieRpConfig->PcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable;
  338. PcieRpConfig->RootPort[0].ClkReqDetect = TRUE;
  339. PcieRpConfig->RootPort[1].ClkReqDetect = TRUE;
  340. PcieRpConfig->RootPort[2].ClkReqDetect = TRUE;
  341. PcieRpConfig->RootPort[3].ClkReqDetect = TRUE;
  342. PcieRpConfig->RootPort[4].ClkReqDetect = TRUE;
  343. PcieRpConfig->RootPort[5].ClkReqDetect = TRUE;
  344. PcieRpConfig->RootPort[6].ClkReqDetect = TRUE;
  345. PcieRpConfig->RootPort[7].ClkReqDetect = TRUE;
  346. PcieRpConfig->RootPort[8].ClkReqDetect = TRUE;
  347. PcieRpConfig->RootPort[9].ClkReqDetect = TRUE;
  348. PcieRpConfig->RootPort[10].ClkReqDetect = TRUE;
  349. PcieRpConfig->RootPort[11].ClkReqDetect = TRUE;
  350. PcieRpConfig->RootPort[12].ClkReqDetect = TRUE;
  351. PcieRpConfig->RootPort[13].ClkReqDetect = TRUE;
  352. PcieRpConfig->RootPort[14].ClkReqDetect = TRUE;
  353. PcieRpConfig->RootPort[15].ClkReqDetect = TRUE;
  354. PcieRpConfig->RootPort[0].AdvancedErrorReporting = TRUE;
  355. PcieRpConfig->RootPort[1].AdvancedErrorReporting = TRUE;
  356. PcieRpConfig->RootPort[2].AdvancedErrorReporting = TRUE;
  357. PcieRpConfig->RootPort[3].AdvancedErrorReporting = TRUE;
  358. PcieRpConfig->RootPort[4].AdvancedErrorReporting = TRUE;
  359. PcieRpConfig->RootPort[5].AdvancedErrorReporting = TRUE;
  360. PcieRpConfig->RootPort[6].AdvancedErrorReporting = TRUE;
  361. PcieRpConfig->RootPort[7].AdvancedErrorReporting = TRUE;
  362. PcieRpConfig->RootPort[8].AdvancedErrorReporting = TRUE;
  363. PcieRpConfig->RootPort[9].AdvancedErrorReporting = TRUE;
  364. PcieRpConfig->RootPort[10].AdvancedErrorReporting = TRUE;
  365. PcieRpConfig->RootPort[11].AdvancedErrorReporting = TRUE;
  366. PcieRpConfig->RootPort[12].AdvancedErrorReporting = TRUE;
  367. PcieRpConfig->RootPort[13].AdvancedErrorReporting = TRUE;
  368. PcieRpConfig->RootPort[14].AdvancedErrorReporting = TRUE;
  369. PcieRpConfig->RootPort[15].AdvancedErrorReporting = TRUE;
  370. //
  371. // Install HDA Link/iDisplay Codec Verb Table
  372. //
  373. AddPlatformVerbTables (
  374. PchHdaCodecPlatformOnboard,
  375. &(HdAudioConfig->VerbTableEntryNum),
  376. &(HdAudioConfig->VerbTablePtr)
  377. );
  378. LockDownConfig->BiosLock = FALSE;
  379. LockDownConfig->BiosInterface = FALSE;
  380. //
  381. // IOAPIC Config
  382. //
  383. // IoApicConfig->IoApicEntry24_119 = PchSetup.PchIoApic24119Entries;
  384. //
  385. // To support SLP_S0, it's required to disable 8254 timer.
  386. // Note that CSM may require this option to be disabled for correct operation.
  387. // Once 8254 timer disabled, some legacy OPROM and legacy OS will fail while using 8254 timer.
  388. // For some OS environment that it needs to set 8254CGE in late state it should
  389. // set this policy to FALSE and use PmcSet8254ClockGateState (TRUE) in SMM later.
  390. // This is also required during S3 resume.
  391. //
  392. // The Enable8254ClockGatingOnS3 is only applicable when Enable8254ClockGating is disabled.
  393. // If Enable8254ClockGating is enabled, RC will do 8254 CGE programming on S3 as well.
  394. // else, RC will do the programming on S3 when Enable8254ClockGatingOnS3 is enabled.
  395. // This avoids the SMI requirement for the programming.
  396. //
  397. // If S0ix is not enabled, then disable 8254CGE for leagcy boot case.
  398. //
  399. IoApicConfig->Enable8254ClockGating = FALSE;
  400. IoApicConfig->Enable8254ClockGatingOnS3 = FALSE;
  401. //
  402. // SerialIo Config
  403. //
  404. SerialIoConfig->DevMode[0] = 1;
  405. SerialIoConfig->DevMode[1] = 1;
  406. SerialIoConfig->DevMode[2] = 0;
  407. SerialIoConfig->DevMode[3] = 0;
  408. SerialIoConfig->DevMode[4] = 1;
  409. SerialIoConfig->DevMode[5] = 0;
  410. SerialIoConfig->DevMode[6] = 0;
  411. SerialIoConfig->DevMode[7] = 0;
  412. SerialIoConfig->DevMode[8] = 0;
  413. SerialIoConfig->DevMode[9] = 0;
  414. SerialIoConfig->DevMode[10] = 0;
  415. SerialIoConfig->DevMode[11] = 3;
  416. SerialIoConfig->Uart0PinMuxing = 1;
  417. SerialIoConfig->SpiCsPolarity[0] = 1;
  418. SerialIoConfig->SpiCsPolarity[1] = 0;
  419. SerialIoConfig->SpiCsPolarity[2] = 0;
  420. SerialIoConfig->UartHwFlowCtrl[0] = 1;
  421. SerialIoConfig->UartHwFlowCtrl[1] = 1;
  422. SerialIoConfig->UartHwFlowCtrl[2] = 1;
  423. //
  424. // I2C4 and I2C5 don't exist in SPT-H chipset
  425. //
  426. if (IsPchH ()) {
  427. SerialIoConfig->DevMode[PchSerialIoIndexI2C4] = PchSerialIoDisabled;
  428. SerialIoConfig->DevMode[PchSerialIoIndexI2C5] = PchSerialIoDisabled;
  429. }
  430. for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++) {
  431. SerialIoConfig->I2cPadsTermination[Index] = GetSerialIoI2cPadsTerminationFromPcd (Index);
  432. }
  433. PmConfig->SlpS0Override = 2; //PchSetup.SlpS0Override;
  434. PmConfig->SlpS0DisQForDebug = 3; //PchSetup.SlpS0DisQForDebug;
  435. PmConfig->SlpS0Vm075VSupport = 1; // PcdGetBool(PcdSlpS0Vm075VSupport);
  436. PmConfig->CpuC10GatePinEnable = 1;
  437. //
  438. // Thermal Config
  439. //
  440. ThermalConfig->TsmicLock = TRUE;
  441. ThermalConfig->PchHotEnable = PcdGetBool (PcdPchThermalHotEnable);
  442. DmiHaAWC = &ThermalConfig->DmiHaAWC;
  443. DmiHaAWC->TS3TW = 0;
  444. DmiHaAWC->TS2TW = 1;
  445. DmiHaAWC->TS1TW = 2;
  446. DmiHaAWC->TS0TW = 3;
  447. //
  448. // Update Pch Usb Config
  449. //
  450. UpdatePchUsbConfig (
  451. UsbConfig
  452. );
  453. ScsConfig->ScsUfsEnabled = 0;
  454. ScsConfig->ScsEmmcHs400Enabled = 1;
  455. ScsConfig->ScsEmmcHs400TuningRequired = TRUE;
  456. IshConfig->I2c0GpioAssign = 1;
  457. IshConfig->I2c1GpioAssign = 1;
  458. IshConfig->Gp0GpioAssign = 1;
  459. IshConfig->Gp1GpioAssign = 1;
  460. IshConfig->Gp2GpioAssign = 1;
  461. IshConfig->Gp3GpioAssign = 1;
  462. IshConfig->Gp4GpioAssign = 1;
  463. IshConfig->Gp5GpioAssign = 1;
  464. IshConfig->Gp6GpioAssign = 1;
  465. return Status;
  466. }