PeiSaPolicyInit.c 3.2 KB

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  1. /** @file
  2. This file is SampleCode for Intel SA PEI Policy initialization.
  3. Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "PeiSaPolicyInit.h"
  7. #include <Library/ConfigBlockLib.h>
  8. /**
  9. PcieCardResetWorkAround performs PCIe Card reset on root port
  10. @param[in out] SiPreMemPolicyPpi SI_PREMEM_POLICY_PPI
  11. @retval EFI_SUCCESS The policy is installed and initialized.
  12. **/
  13. EFI_STATUS
  14. PcieCardResetWorkAround (
  15. IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
  16. )
  17. {
  18. EFI_STATUS Status;
  19. SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
  20. SWITCHABLE_GRAPHICS_CONFIG *SgGpioData;
  21. Status = GetConfigBlock((VOID *)SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *)&MiscPeiPreMemConfig);
  22. ASSERT_EFI_ERROR(Status);
  23. Status = GetConfigBlock((VOID *)SiPreMemPolicyPpi, &gSwitchableGraphicsConfigGuid, (VOID *)&SgGpioData);
  24. ASSERT_EFI_ERROR(Status);
  25. if (SgGpioData->SaRtd3Pcie0Gpio.GpioSupport != NotSupported) {
  26. ///
  27. /// dGPU is present.
  28. /// If PCIe Mode or SG Muxless
  29. /// Power on MXM
  30. /// Configure GPIOs to drive MXM in PCIe mode or SG Muxless
  31. /// else
  32. /// Do Nothing
  33. ///
  34. if ((MiscPeiPreMemConfig->SgMode == SgModeMuxless) ||
  35. (MiscPeiPreMemConfig->SgMode == SgModeDgpu)) {
  36. DEBUG((DEBUG_INFO, "Configure GPIOs for driving the dGPU.\n"));
  37. ///
  38. /// Drive DGPU HOLD RST Enable to make sure we hold reset
  39. ///
  40. PcieGpioWrite (
  41. SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo,
  42. SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active,
  43. GP_ENABLE
  44. );
  45. ///
  46. /// wait 100ms
  47. ///
  48. MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * STALL_ONE_MILLI_SECOND);
  49. ///
  50. /// Drive DGPU PWR EN to Power On MXM
  51. ///
  52. PcieGpioWrite (
  53. SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.GpioNo,
  54. SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.Active,
  55. GP_ENABLE
  56. );
  57. ///
  58. /// wait 300ms
  59. ///
  60. MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterPwrEn) * STALL_ONE_MILLI_SECOND);
  61. ///
  62. /// Drive DGPU HOLD RST Disabled to remove reset
  63. ///
  64. PcieGpioWrite (
  65. SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo,
  66. SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active,
  67. GP_DISABLE
  68. );
  69. ///
  70. /// wait 100ms
  71. ///
  72. MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * STALL_ONE_MILLI_SECOND);
  73. }
  74. }
  75. return EFI_SUCCESS;
  76. }
  77. /**
  78. PCIe GPIO Write
  79. @param[in] Gpio - GPIO Number
  80. @param[in] Active - GPIO Active Information; High/Low
  81. @param[in] Level - Write GPIO value (0/1)
  82. **/
  83. VOID
  84. PcieGpioWrite (
  85. IN UINT32 Gpio,
  86. IN BOOLEAN Active,
  87. IN BOOLEAN Level
  88. )
  89. {
  90. EFI_STATUS Status;
  91. if (Active == 0) {
  92. Level = (~Level) & 0x1;
  93. }
  94. Status = GpioSetOutputValue(Gpio, (UINT32)Level);
  95. if (Status != EFI_SUCCESS) {
  96. return;
  97. }
  98. }