PeiFspSaPolicyInitLib.c 44 KB

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  1. /** @file
  2. Implementation of Fsp SA Policy Initialization.
  3. Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <PeiFspPolicyInitLib.h>
  7. #include <Ppi/SiPolicy.h>
  8. #include <ConfigBlock/MemoryConfig.h>
  9. #include <Library/IoLib.h>
  10. #include <Library/BaseMemoryLib.h>
  11. #include <Library/SmbusLib.h>
  12. #include <Library/ConfigBlockLib.h>
  13. #include <Library/PcdLib.h>
  14. #include <IndustryStandard/Pci.h>
  15. #include <PchAccess.h>
  16. #include <Ppi/FirmwareVolume.h>
  17. #include <Pi/PiFirmwareFile.h>
  18. #include <Pi/PiPeiCis.h>
  19. #include <Core/Pei/PeiMain.h>
  20. #include <Library/ConfigBlockLib.h>
  21. #define MAX_SPD_PAGE_COUNT (2)
  22. #define MAX_SPD_PAGE_SIZE (256)
  23. #define MAX_SPD_SIZE (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_COUNT)
  24. #define SPD_PAGE_ADDRESS_0 (0x6C)
  25. #define SPD_PAGE_ADDRESS_1 (0x6E)
  26. #define SPD_DDR3_SDRAM_TYPE_OFFSET (0x02)
  27. #define SPD_DDR3_SDRAM_TYPE_NUMBER (0x0B)
  28. #define SPD_DDR4_SDRAM_TYPE_NUMBER (0x0C)
  29. #define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0xF1)
  30. #define SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER (0x0F)
  31. #define XMP_ID_STRING (0x4A0C)
  32. #define SPD3_MANUF_START (117)
  33. #define SPD3_MANUF_END (127)
  34. #define SPD4_MANUF_START (320)
  35. #define SPD4_MANUF_END (328)
  36. #define SPDLP_MANUF_START (320)
  37. #define SPDLP_MANUF_END (328)
  38. GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr3Table[] = {
  39. { 0, 1, (1 << SpdCold),},
  40. { 2, 2, (1 << SpdCold) | (1 << SpdFast),},
  41. { 3, 41, (1 << SpdCold),},
  42. { 60, 63, (1 << SpdCold),},
  43. { SPD3_MANUF_START, SPD3_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
  44. { 128, 145, (1 << SpdCold),},
  45. { 39, 59, (1 << SpdCold),},
  46. { 64, 125, (1 << SpdCold),},
  47. { 176, 179, (1 << SpdCold),},
  48. { 180, 184, (1 << SpdCold),},
  49. { 185, 215, (1 << SpdCold),},
  50. { 220, 250, (1 << SpdCold),},
  51. };
  52. GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr4Table[] = {
  53. { 0, 1, (1 << SpdCold),},
  54. { 2, 2, (1 << SpdCold) | (1 << SpdFast),},
  55. { 3, 40, (1 << SpdCold),},
  56. { 117, 131, (1 << SpdCold),},
  57. { SPD4_MANUF_START, SPD4_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
  58. { 329, 348, (1 << SpdCold),},
  59. { 32, 119, (1 << SpdCold),},
  60. { 126, 255, (1 << SpdCold),},
  61. { 349, 383, (1 << SpdCold),},
  62. { 384, 387, (1 << SpdCold),},
  63. { 388, 389, (1 << SpdCold),},
  64. { 393, 431, (1 << SpdCold),},
  65. { 440, 478, (1 << SpdCold),},
  66. };
  67. GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdLpddrTable[] = {
  68. { 0, 1, (1 << SpdCold),},
  69. { 2, 2, (1 << SpdCold) | (1 << SpdFast),},
  70. { 3, 32, (1 << SpdCold),},
  71. { 120, 130, (1 << SpdCold),},
  72. { SPDLP_MANUF_START, SPDLP_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
  73. { 329, 348, (1 << SpdCold),},
  74. { 31, 121, (1 << SpdCold),},
  75. { 126, 255, (1 << SpdCold),},
  76. { 349, 383, (1 << SpdCold),},
  77. { 384, 387, (1 << SpdCold),},
  78. { 388, 389, (1 << SpdCold),},
  79. { 393, 431, (1 << SpdCold),},
  80. { 440, 478, (1 << SpdCold),},
  81. };
  82. /**
  83. Update Spd Data
  84. @param[in][out] FspmUpd Pointer to FSP UPD Data.
  85. @param[in] MemConfigNoCrc Pointer to Mem Config No Crc.
  86. @param[in] MiscPeiPreMemConfig Pointer to Misc Config.
  87. @retval EFI_SUCCESS The function completes successfully
  88. @retval Other The function fail
  89. **/
  90. VOID
  91. EFIAPI
  92. InternalUpdateSpdInfo (
  93. IN OUT FSPM_UPD *FspmUpd,
  94. IN MEMORY_CONFIG_NO_CRC *MemConfigNoCrc,
  95. IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig
  96. )
  97. {
  98. DEBUG ((DEBUG_INFO, "Updating UPD:Memory Spd Pointers...\n"));
  99. if ((FspmUpd == NULL) || (MemConfigNoCrc == NULL) || (MiscPeiPreMemConfig == NULL)) {
  100. DEBUG ((DEBUG_ERROR, "EFI_INVALID_PARAMETER.\n"));
  101. DEBUG ((DEBUG_ERROR, "Fail to access SPD from SiPolicyPpi\n"));
  102. return;
  103. }
  104. //
  105. // Update MemorySpdPtrXX if SpdAddressTable is zero
  106. //
  107. if (MiscPeiPreMemConfig->SpdAddressTable[0] == 0x0) {
  108. FspmUpd->FspmConfig.MemorySpdPtr00 = (UINT32)MemConfigNoCrc->SpdData->SpdData;
  109. } else {
  110. FspmUpd->FspmConfig.SpdAddressTable[0] = MiscPeiPreMemConfig->SpdAddressTable[0];
  111. }
  112. if (MiscPeiPreMemConfig->SpdAddressTable[1] == 0x0) {
  113. FspmUpd->FspmConfig.MemorySpdPtr01 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (1 * SA_MC_MAX_SPD_SIZE);
  114. } else {
  115. FspmUpd->FspmConfig.SpdAddressTable[1] = MiscPeiPreMemConfig->SpdAddressTable[1];
  116. }
  117. if (MiscPeiPreMemConfig->SpdAddressTable[2] == 0x0) {
  118. FspmUpd->FspmConfig.MemorySpdPtr10 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (2 * SA_MC_MAX_SPD_SIZE);
  119. } else {
  120. FspmUpd->FspmConfig.SpdAddressTable[2] = MiscPeiPreMemConfig->SpdAddressTable[2];
  121. }
  122. if (MiscPeiPreMemConfig->SpdAddressTable[3] == 0x0) {
  123. FspmUpd->FspmConfig.MemorySpdPtr11 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (3 * SA_MC_MAX_SPD_SIZE);
  124. } else {
  125. FspmUpd->FspmConfig.SpdAddressTable[3] = MiscPeiPreMemConfig->SpdAddressTable[3];
  126. }
  127. DEBUG ((DEBUG_INFO, "UPD:MemorySpdPtr Updated\n"));
  128. }
  129. /**
  130. PeiGetSectionFromFv finds the file in FV and gets file Address and Size
  131. @param[in] NameGuid - File GUID
  132. @param[out] Address - Pointer to the File Address
  133. @param[out] Size - Pointer to File Size
  134. @retval EFI_SUCCESS Successfull in reading the section from FV
  135. **/
  136. EFI_STATUS
  137. EFIAPI
  138. PeiGetSectionFromFv (
  139. IN CONST EFI_GUID NameGuid,
  140. OUT VOID **Address,
  141. OUT UINT32 *Size
  142. )
  143. {
  144. EFI_STATUS Status;
  145. EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi;
  146. EFI_FV_FILE_INFO FvFileInfo;
  147. PEI_CORE_INSTANCE *PrivateData;
  148. UINTN CurrentFv;
  149. PEI_CORE_FV_HANDLE *CoreFvHandle;
  150. EFI_PEI_FILE_HANDLE VbtFileHandle;
  151. EFI_GUID *VbtGuid;
  152. EFI_COMMON_SECTION_HEADER *Section;
  153. CONST EFI_PEI_SERVICES **PeiServices;
  154. PeiServices = GetPeiServicesTablePointer ();
  155. PrivateData = PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
  156. Status = PeiServicesLocatePpi (
  157. &gEfiFirmwareFileSystem2Guid,
  158. 0,
  159. NULL,
  160. (VOID **) &FvPpi
  161. );
  162. ASSERT_EFI_ERROR (Status);
  163. CurrentFv = PrivateData->CurrentPeimFvCount;
  164. CoreFvHandle = &(PrivateData->Fv[CurrentFv]);
  165. Status = FvPpi->FindFileByName (FvPpi, &NameGuid, &CoreFvHandle->FvHandle, &VbtFileHandle);
  166. if (!EFI_ERROR(Status) && VbtFileHandle != NULL) {
  167. DEBUG ((DEBUG_INFO, "Find SectionByType \n"));
  168. Status = FvPpi->FindSectionByType (FvPpi, EFI_SECTION_RAW, VbtFileHandle, (VOID **) &VbtGuid);
  169. if (!EFI_ERROR (Status)) {
  170. DEBUG ((DEBUG_INFO, "GetFileInfo \n"));
  171. Status = FvPpi->GetFileInfo (FvPpi, VbtFileHandle, &FvFileInfo);
  172. Section = (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer;
  173. if (IS_SECTION2 (Section)) {
  174. ASSERT (SECTION2_SIZE (Section) > 0x00FFFFFF);
  175. *Size = SECTION2_SIZE (Section) - sizeof (EFI_COMMON_SECTION_HEADER2);
  176. *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER2));
  177. } else {
  178. *Size = SECTION_SIZE (Section) - sizeof (EFI_COMMON_SECTION_HEADER);
  179. *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER));
  180. }
  181. }
  182. }
  183. return EFI_SUCCESS;
  184. }
  185. /**
  186. Performs FSP SA PEI Policy initialization in pre-memory.
  187. @param[in][out] FspmUpd Pointer to FSP UPD Data.
  188. @retval EFI_SUCCESS FSP UPD Data is updated.
  189. @retval EFI_NOT_FOUND Fail to locate required PPI.
  190. @retval Other FSP UPD Data update process fail.
  191. **/
  192. EFI_STATUS
  193. EFIAPI
  194. PeiFspSaPolicyInitPreMem (
  195. IN OUT FSPM_UPD *FspmUpd
  196. )
  197. {
  198. EFI_STATUS Status;
  199. SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
  200. MEMORY_CONFIGURATION *MemConfig;
  201. MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
  202. SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
  203. PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig;
  204. SWITCHABLE_GRAPHICS_CONFIG *SgGpioData;
  205. GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig;
  206. OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig;
  207. VTD_CONFIG *Vtd;
  208. IPU_PREMEM_CONFIG *IpuPreMemPolicy;
  209. UINT8 Index;
  210. VOID *Buffer;
  211. SiPreMemPolicyPpi = NULL;
  212. MiscPeiPreMemConfig = NULL;
  213. MemConfig = NULL;
  214. MemConfigNoCrc = NULL;
  215. PciePeiPreMemConfig = NULL;
  216. SgGpioData = NULL;
  217. GtPreMemConfig = NULL;
  218. OcPreMemConfig = NULL;
  219. Vtd = NULL;
  220. IpuPreMemPolicy = NULL;
  221. //
  222. // Locate SiPreMemPolicyPpi
  223. //
  224. Status = PeiServicesLocatePpi(
  225. &gSiPreMemPolicyPpiGuid,
  226. 0,
  227. NULL,
  228. (VOID **) &SiPreMemPolicyPpi
  229. );
  230. ASSERT_EFI_ERROR (Status);
  231. if ((Status == EFI_SUCCESS) && (SiPreMemPolicyPpi != NULL)) {
  232. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
  233. ASSERT_EFI_ERROR (Status);
  234. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
  235. ASSERT_EFI_ERROR (Status);
  236. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
  237. ASSERT_EFI_ERROR (Status);
  238. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gGraphicsPeiPreMemConfigGuid, (VOID *) &GtPreMemConfig);
  239. ASSERT_EFI_ERROR (Status);
  240. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaPciePeiPreMemConfigGuid, (VOID *) &PciePeiPreMemConfig);
  241. ASSERT_EFI_ERROR (Status);
  242. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSwitchableGraphicsConfigGuid, (VOID *) &SgGpioData);
  243. ASSERT_EFI_ERROR (Status);
  244. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid, (VOID *) &Vtd);
  245. ASSERT_EFI_ERROR (Status);
  246. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gIpuPreMemConfigGuid, (VOID *) &IpuPreMemPolicy);
  247. ASSERT_EFI_ERROR (Status);
  248. Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaOverclockingPreMemConfigGuid, (VOID *) &OcPreMemConfig);
  249. ASSERT_EFI_ERROR (Status);
  250. }
  251. DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
  252. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
  253. if (Buffer) {
  254. CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12);
  255. CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 12, 12);
  256. }
  257. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
  258. if (Buffer) {
  259. CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8);
  260. CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffer + 8, 8);
  261. }
  262. DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n"));
  263. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
  264. if (Buffer) {
  265. CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6);
  266. }
  267. Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
  268. if (Buffer) {
  269. CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10);
  270. }
  271. //
  272. // Update UPD:MemorySpdPtrXX and SpdAddressTable
  273. //
  274. InternalUpdateSpdInfo (FspmUpd, MemConfigNoCrc, MiscPeiPreMemConfig);
  275. //
  276. // Update UPD:MemorySpdDataLen
  277. //
  278. FspmUpd->FspmConfig.MemorySpdDataLen = SA_MC_MAX_SPD_SIZE;
  279. if (MemConfigNoCrc != NULL) {
  280. //
  281. // Update UPD:PlatformMemorySize
  282. //
  283. //
  284. // @todo: This value is used since #183932. Revisit.
  285. //
  286. FspmUpd->FspmConfig.PlatformMemorySize = MemConfigNoCrc->PlatformMemorySize;
  287. FspmUpd->FspmConfig.CleanMemory = (UINT8) MemConfigNoCrc->CleanMemory;
  288. FspmUpd->FspmConfig.MemTestOnWarmBoot = (UINT8) MemConfigNoCrc->MemTestOnWarmBoot;
  289. }
  290. if (MemConfig != NULL) {
  291. //
  292. // Update UPD:DqPinsInterleaved
  293. //
  294. FspmUpd->FspmConfig.DqPinsInterleaved = (UINT8) MemConfig->DqPinsInterleaved;
  295. FspmUpd->FspmConfig.ProbelessTrace = MemConfig->ProbelessTrace;
  296. FspmUpd->FspmConfig.GdxcIotSize = MemConfig->GdxcIotSize;
  297. FspmUpd->FspmConfig.GdxcMotSize = MemConfig->GdxcMotSize;
  298. FspmUpd->FspmConfig.DualDimmPerChannelBoardType =(UINT8) MemConfig->DualDimmPerChannelBoardType;
  299. FspmUpd->FspmConfig.Ddr4MixedUDimm2DpcLimit =(UINT8) MemConfig->Ddr4MixedUDimm2DpcLimit;
  300. //
  301. // Update UPD:CaVrefConfig
  302. //
  303. FspmUpd->FspmConfig.CaVrefConfig = MemConfig->CaVrefConfig;
  304. FspmUpd->FspmConfig.SaGv = MemConfig->SaGv;
  305. FspmUpd->FspmConfig.FreqSaGvLow = MemConfig->FreqSaGvLow;
  306. FspmUpd->FspmConfig.FreqSaGvMid = MemConfig->FreqSaGvMid;
  307. FspmUpd->FspmConfig.RMT = (UINT8) MemConfig->RMT;
  308. FspmUpd->FspmConfig.DdrFreqLimit = MemConfig->DdrFreqLimit;
  309. FspmUpd->FspmConfig.SpdProfileSelected = MemConfig->SpdProfileSelected;
  310. FspmUpd->FspmConfig.VddVoltage = MemConfig->VddVoltage;
  311. FspmUpd->FspmConfig.RefClk = MemConfig->RefClk;
  312. FspmUpd->FspmConfig.Ratio = MemConfig->Ratio;
  313. FspmUpd->FspmConfig.OddRatioMode = (UINT8) MemConfig->OddRatioMode;
  314. FspmUpd->FspmConfig.tCL = (UINT8) MemConfig->tCL;
  315. FspmUpd->FspmConfig.tCWL = (UINT8) MemConfig->tCWL;
  316. FspmUpd->FspmConfig.tFAW = MemConfig->tFAW;
  317. FspmUpd->FspmConfig.tRAS = MemConfig->tRAS;
  318. FspmUpd->FspmConfig.tRCDtRP = (UINT8) MemConfig->tRCDtRP;
  319. FspmUpd->FspmConfig.tREFI = MemConfig->tREFI;
  320. FspmUpd->FspmConfig.tRFC = MemConfig->tRFC;
  321. FspmUpd->FspmConfig.tRRD = (UINT8) MemConfig->tRRD;
  322. FspmUpd->FspmConfig.tRTP = (UINT8) MemConfig->tRTP;
  323. FspmUpd->FspmConfig.tWR = (UINT8) MemConfig->tWR;
  324. FspmUpd->FspmConfig.tWTR = (UINT8) MemConfig->tWTR;
  325. FspmUpd->FspmConfig.NModeSupport = MemConfig->NModeSupport;
  326. FspmUpd->FspmConfig.DllBwEn0 = MemConfig->DllBwEn0;
  327. FspmUpd->FspmConfig.DllBwEn1 = MemConfig->DllBwEn1;
  328. FspmUpd->FspmConfig.DllBwEn2 = MemConfig->DllBwEn2;
  329. FspmUpd->FspmConfig.DllBwEn3 = MemConfig->DllBwEn3;
  330. FspmUpd->FspmConfig.MrcSafeConfig = (UINT8) MemConfig->MrcSafeConfig; // Typecasting as MrcSafeConfig is of UINT32 in MEMORY_CONFIGURATION
  331. FspmUpd->FspmConfig.LpDdrDqDqsReTraining = (UINT8) MemConfig->Lp4DqsOscEn;
  332. FspmUpd->FspmConfig.RmtPerTask = (UINT8) MemConfig->RmtPerTask;
  333. FspmUpd->FspmConfig.TrainTrace = (UINT8) MemConfig->TrainTrace;
  334. FspmUpd->FspmConfig.ScramblerSupport = (UINT8) MemConfig->ScramblerSupport;
  335. FspmUpd->FspmConfig.SafeMode = (UINT8) MemConfig->SafeMode;
  336. //
  337. // Update UPD:SmramMask and DisableDimmChannel
  338. //
  339. FspmUpd->FspmConfig.SmramMask = MemConfig->SmramMask;
  340. FspmUpd->FspmConfig.DisableDimmChannel0 = MemConfig->DisableDimmChannel[0];
  341. FspmUpd->FspmConfig.DisableDimmChannel1 = MemConfig->DisableDimmChannel[1];
  342. FspmUpd->FspmConfig.HobBufferSize = MemConfig->HobBufferSize;
  343. FspmUpd->FspmConfig.ECT = (UINT8) MemConfig->ECT;
  344. FspmUpd->FspmConfig.SOT = (UINT8) MemConfig->SOT;
  345. FspmUpd->FspmConfig.ERDMPRTC2D = (UINT8) MemConfig->ERDMPRTC2D;
  346. FspmUpd->FspmConfig.RDMPRT = (UINT8) MemConfig->RDMPRT;
  347. FspmUpd->FspmConfig.RCVET = (UINT8) MemConfig->RCVET;
  348. FspmUpd->FspmConfig.JWRL = (UINT8) MemConfig->JWRL;
  349. FspmUpd->FspmConfig.EWRTC2D = (UINT8) MemConfig->EWRTC2D;
  350. FspmUpd->FspmConfig.ERDTC2D = (UINT8) MemConfig->ERDTC2D;
  351. FspmUpd->FspmConfig.WRTC1D = (UINT8) MemConfig->WRTC1D;
  352. FspmUpd->FspmConfig.WRVC1D = (UINT8) MemConfig->WRVC1D;
  353. FspmUpd->FspmConfig.RDTC1D = (UINT8) MemConfig->RDTC1D;
  354. FspmUpd->FspmConfig.DIMMODTT = (UINT8) MemConfig->DIMMODTT;
  355. FspmUpd->FspmConfig.DIMMRONT = (UINT8) MemConfig->DIMMRONT;
  356. FspmUpd->FspmConfig.WRSRT = (UINT8) MemConfig->WRSRT;
  357. FspmUpd->FspmConfig.RDODTT = (UINT8) MemConfig->RDODTT;
  358. FspmUpd->FspmConfig.RDEQT = (UINT8) MemConfig->RDEQT;
  359. FspmUpd->FspmConfig.RDAPT = (UINT8) MemConfig->RDAPT;
  360. FspmUpd->FspmConfig.WRTC2D = (UINT8) MemConfig->WRTC2D;
  361. FspmUpd->FspmConfig.RDTC2D = (UINT8) MemConfig->RDTC2D;
  362. FspmUpd->FspmConfig.WRVC2D = (UINT8) MemConfig->WRVC2D;
  363. FspmUpd->FspmConfig.RDVC2D = (UINT8) MemConfig->RDVC2D;
  364. FspmUpd->FspmConfig.CMDVC = (UINT8) MemConfig->CMDVC;
  365. FspmUpd->FspmConfig.LCT = (UINT8) MemConfig->LCT;
  366. FspmUpd->FspmConfig.RTL = (UINT8) MemConfig->RTL;
  367. FspmUpd->FspmConfig.TAT = (UINT8) MemConfig->TAT;
  368. FspmUpd->FspmConfig.RCVENC1D = (UINT8) MemConfig->RCVENC1D;
  369. FspmUpd->FspmConfig.RMT = (UINT8) MemConfig->RMT;
  370. FspmUpd->FspmConfig.MEMTST = (UINT8) MemConfig->MEMTST;
  371. FspmUpd->FspmConfig.ALIASCHK = (UINT8) MemConfig->ALIASCHK;
  372. FspmUpd->FspmConfig.RMC = (UINT8) MemConfig->RMC;
  373. FspmUpd->FspmConfig.WRDSUDT = (UINT8) MemConfig->WRDSUDT;
  374. FspmUpd->FspmConfig.EnBER = (UINT8) MemConfig->EnBER;
  375. FspmUpd->FspmConfig.EccSupport = (UINT8) MemConfig->EccSupport;
  376. FspmUpd->FspmConfig.RemapEnable = (UINT8) MemConfig->RemapEnable;
  377. FspmUpd->FspmConfig.ScramblerSupport = (UINT8) MemConfig->ScramblerSupport;
  378. FspmUpd->FspmConfig.MrcFastBoot = (UINT8) MemConfig->MrcFastBoot;
  379. FspmUpd->FspmConfig.RankInterleave = (UINT8) MemConfig->RankInterleave;
  380. FspmUpd->FspmConfig.EnhancedInterleave = (UINT8) MemConfig->EnhancedInterleave;
  381. FspmUpd->FspmConfig.MemoryTrace = (UINT8) MemConfig->MemoryTrace;
  382. FspmUpd->FspmConfig.ChHashEnable = (UINT8) MemConfig->ChHashEnable;
  383. FspmUpd->FspmConfig.EnableExtts = (UINT8) MemConfig->EnableExtts;
  384. FspmUpd->FspmConfig.EnableCltm = (UINT8) MemConfig->EnableCltm;
  385. FspmUpd->FspmConfig.EnableOltm = (UINT8) MemConfig->EnableOltm;
  386. FspmUpd->FspmConfig.EnablePwrDn = (UINT8) MemConfig->EnablePwrDn;
  387. FspmUpd->FspmConfig.EnablePwrDnLpddr = (UINT8) MemConfig->EnablePwrDnLpddr;
  388. FspmUpd->FspmConfig.UserPowerWeightsEn = (UINT8) MemConfig->UserPowerWeightsEn;
  389. FspmUpd->FspmConfig.RaplLim2Lock = (UINT8) MemConfig->RaplLim2Lock;
  390. FspmUpd->FspmConfig.RaplLim2Ena = (UINT8) MemConfig->RaplLim2Ena;
  391. FspmUpd->FspmConfig.RaplLim1Ena = (UINT8) MemConfig->RaplLim1Ena;
  392. FspmUpd->FspmConfig.SrefCfgEna = (UINT8) MemConfig->SrefCfgEna;
  393. FspmUpd->FspmConfig.ThrtCkeMinDefeatLpddr = (UINT8) MemConfig->ThrtCkeMinDefeatLpddr;
  394. FspmUpd->FspmConfig.ThrtCkeMinDefeat = (UINT8) MemConfig->ThrtCkeMinDefeat;
  395. FspmUpd->FspmConfig.RhPrevention = (UINT8) MemConfig->RhPrevention;
  396. FspmUpd->FspmConfig.ExitOnFailure = (UINT8) MemConfig->ExitOnFailure;
  397. FspmUpd->FspmConfig.DdrThermalSensor = (UINT8) MemConfig->DdrThermalSensor;
  398. FspmUpd->FspmConfig.Ddr4DdpSharedClock = (UINT8) MemConfig->Ddr4DdpSharedClock;
  399. FspmUpd->FspmConfig.Ddr4DdpSharedZq = (UINT8) MemConfig->SharedZqPin;
  400. FspmUpd->FspmConfig.BClkFrequency = MemConfig->BClkFrequency;
  401. FspmUpd->FspmConfig.ChHashInterleaveBit = MemConfig->ChHashInterleaveBit;
  402. FspmUpd->FspmConfig.ChHashMask = MemConfig->ChHashMask;
  403. FspmUpd->FspmConfig.EnergyScaleFact = MemConfig->EnergyScaleFact;
  404. FspmUpd->FspmConfig.Idd3n = MemConfig->Idd3n;
  405. FspmUpd->FspmConfig.Idd3p = MemConfig->Idd3p;
  406. FspmUpd->FspmConfig.CMDSR = (UINT8) MemConfig->CMDSR;
  407. FspmUpd->FspmConfig.CMDDSEQ = (UINT8) MemConfig->CMDDSEQ;
  408. FspmUpd->FspmConfig.CMDNORM = (UINT8) MemConfig->CMDNORM;
  409. FspmUpd->FspmConfig.EWRDSEQ = (UINT8) MemConfig->EWRDSEQ;
  410. FspmUpd->FspmConfig.FreqSaGvLow = MemConfig->FreqSaGvLow;
  411. FspmUpd->FspmConfig.RhActProbability = MemConfig->RhActProbability;
  412. FspmUpd->FspmConfig.RaplLim2WindX = MemConfig->RaplLim2WindX;
  413. FspmUpd->FspmConfig.RaplLim2WindY = MemConfig->RaplLim2WindY;
  414. FspmUpd->FspmConfig.RaplLim1WindX = MemConfig->RaplLim1WindX;
  415. FspmUpd->FspmConfig.RaplLim1WindY = MemConfig->RaplLim1WindY;
  416. FspmUpd->FspmConfig.RaplLim2Pwr = MemConfig->RaplLim2Pwr;
  417. FspmUpd->FspmConfig.RaplLim1Pwr = MemConfig->RaplLim1Pwr;
  418. FspmUpd->FspmConfig.WarmThresholdCh0Dimm0 = MemConfig->WarmThresholdCh0Dimm0;
  419. FspmUpd->FspmConfig.WarmThresholdCh0Dimm1 = MemConfig->WarmThresholdCh0Dimm1;
  420. FspmUpd->FspmConfig.WarmThresholdCh1Dimm0 = MemConfig->WarmThresholdCh1Dimm0;
  421. FspmUpd->FspmConfig.WarmThresholdCh1Dimm1 = MemConfig->WarmThresholdCh1Dimm1;
  422. FspmUpd->FspmConfig.HotThresholdCh0Dimm0 = MemConfig->HotThresholdCh0Dimm0;
  423. FspmUpd->FspmConfig.HotThresholdCh0Dimm1 = MemConfig->HotThresholdCh0Dimm1;
  424. FspmUpd->FspmConfig.HotThresholdCh1Dimm0 = MemConfig->HotThresholdCh1Dimm0;
  425. FspmUpd->FspmConfig.HotThresholdCh1Dimm1 = MemConfig->HotThresholdCh1Dimm1;
  426. FspmUpd->FspmConfig.WarmBudgetCh0Dimm0 = MemConfig->WarmBudgetCh0Dimm0;
  427. FspmUpd->FspmConfig.WarmBudgetCh0Dimm1 = MemConfig->WarmBudgetCh0Dimm1;
  428. FspmUpd->FspmConfig.WarmBudgetCh1Dimm0 = MemConfig->WarmBudgetCh1Dimm0;
  429. FspmUpd->FspmConfig.WarmBudgetCh1Dimm1 = MemConfig->WarmBudgetCh1Dimm1;
  430. FspmUpd->FspmConfig.HotBudgetCh0Dimm0 = MemConfig->HotBudgetCh0Dimm0;
  431. FspmUpd->FspmConfig.HotBudgetCh0Dimm1 = MemConfig->HotBudgetCh0Dimm1;
  432. FspmUpd->FspmConfig.HotBudgetCh1Dimm0 = MemConfig->HotBudgetCh1Dimm0;
  433. FspmUpd->FspmConfig.HotBudgetCh1Dimm1 = MemConfig->HotBudgetCh1Dimm1;
  434. FspmUpd->FspmConfig.IdleEnergyCh0Dimm0 = MemConfig->IdleEnergyCh0Dimm0;
  435. FspmUpd->FspmConfig.IdleEnergyCh0Dimm1 = MemConfig->IdleEnergyCh0Dimm1;
  436. FspmUpd->FspmConfig.IdleEnergyCh1Dimm0 = MemConfig->IdleEnergyCh1Dimm0;
  437. FspmUpd->FspmConfig.IdleEnergyCh1Dimm1 = MemConfig->IdleEnergyCh1Dimm1;
  438. FspmUpd->FspmConfig.PdEnergyCh0Dimm0 = MemConfig->PdEnergyCh0Dimm0;
  439. FspmUpd->FspmConfig.PdEnergyCh0Dimm1 = MemConfig->PdEnergyCh0Dimm1;
  440. FspmUpd->FspmConfig.PdEnergyCh1Dimm0 = MemConfig->PdEnergyCh1Dimm0;
  441. FspmUpd->FspmConfig.PdEnergyCh1Dimm1 = MemConfig->PdEnergyCh1Dimm1;
  442. FspmUpd->FspmConfig.ActEnergyCh0Dimm0 = MemConfig->ActEnergyCh0Dimm0;
  443. FspmUpd->FspmConfig.ActEnergyCh0Dimm1 = MemConfig->ActEnergyCh0Dimm1;
  444. FspmUpd->FspmConfig.ActEnergyCh1Dimm0 = MemConfig->ActEnergyCh1Dimm0;
  445. FspmUpd->FspmConfig.ActEnergyCh1Dimm1 = MemConfig->ActEnergyCh1Dimm1;
  446. FspmUpd->FspmConfig.RdEnergyCh0Dimm0 = MemConfig->RdEnergyCh0Dimm0;
  447. FspmUpd->FspmConfig.RdEnergyCh0Dimm1 = MemConfig->RdEnergyCh0Dimm1;
  448. FspmUpd->FspmConfig.RdEnergyCh1Dimm0 = MemConfig->RdEnergyCh1Dimm0;
  449. FspmUpd->FspmConfig.RdEnergyCh1Dimm1 = MemConfig->RdEnergyCh1Dimm1;
  450. FspmUpd->FspmConfig.WrEnergyCh0Dimm0 = MemConfig->WrEnergyCh0Dimm0;
  451. FspmUpd->FspmConfig.WrEnergyCh0Dimm1 = MemConfig->WrEnergyCh0Dimm1;
  452. FspmUpd->FspmConfig.WrEnergyCh1Dimm0 = MemConfig->WrEnergyCh1Dimm0;
  453. FspmUpd->FspmConfig.WrEnergyCh1Dimm1 = MemConfig->WrEnergyCh1Dimm1;
  454. FspmUpd->FspmConfig.ThrtCkeMinTmr = MemConfig->ThrtCkeMinTmr;
  455. FspmUpd->FspmConfig.CkeRankMapping = MemConfig->CkeRankMapping;
  456. FspmUpd->FspmConfig.CaVrefConfig = MemConfig->CaVrefConfig;
  457. FspmUpd->FspmConfig.RaplPwrFlCh1 = MemConfig->RaplPwrFlCh1;
  458. FspmUpd->FspmConfig.RaplPwrFlCh0 = MemConfig->RaplPwrFlCh0;
  459. FspmUpd->FspmConfig.EnCmdRate = MemConfig->EnCmdRate;
  460. FspmUpd->FspmConfig.Refresh2X = MemConfig->Refresh2X;
  461. FspmUpd->FspmConfig.EpgEnable = MemConfig->EpgEnable;
  462. FspmUpd->FspmConfig.RhSolution = MemConfig->RhSolution;
  463. FspmUpd->FspmConfig.UserThresholdEnable = MemConfig->UserThresholdEnable;
  464. FspmUpd->FspmConfig.UserBudgetEnable = MemConfig->UserBudgetEnable;
  465. FspmUpd->FspmConfig.TsodTcritMax = MemConfig->TsodTcritMax;
  466. FspmUpd->FspmConfig.TsodEventMode = MemConfig->TsodEventMode;
  467. FspmUpd->FspmConfig.TsodEventPolarity = MemConfig->TsodEventPolarity;
  468. FspmUpd->FspmConfig.TsodCriticalEventOnly = MemConfig->TsodCriticalEventOnly;
  469. FspmUpd->FspmConfig.TsodEventOutputControl = MemConfig->TsodEventOutputControl;
  470. FspmUpd->FspmConfig.TsodAlarmwindowLockBit = MemConfig->TsodAlarmwindowLockBit;
  471. FspmUpd->FspmConfig.TsodCriticaltripLockBit = MemConfig->TsodCriticaltripLockBit;
  472. FspmUpd->FspmConfig.TsodShutdownMode = MemConfig->TsodShutdownMode;
  473. FspmUpd->FspmConfig.TsodThigMax = MemConfig->TsodThigMax;
  474. FspmUpd->FspmConfig.TsodManualEnable = MemConfig->TsodManualEnable;
  475. FspmUpd->FspmConfig.IsvtIoPort = MemConfig->IsvtIoPort;
  476. FspmUpd->FspmConfig.ForceOltmOrRefresh2x = MemConfig->ForceOltmOrRefresh2x;
  477. FspmUpd->FspmConfig.PwdwnIdleCounter = MemConfig->PwdwnIdleCounter;
  478. FspmUpd->FspmConfig.CmdRanksTerminated = MemConfig->CmdRanksTerminated;
  479. FspmUpd->FspmConfig.GdxcEnable = MemConfig->GdxcEnable;
  480. FspmUpd->FspmConfig.RMTLoopCount = MemConfig->RMTLoopCount;
  481. // DDR4 Memory Timings
  482. FspmUpd->FspmTestConfig.tRRD_L = (UINT8) MemConfig->tRRD_L;
  483. FspmUpd->FspmTestConfig.tRRD_S = (UINT8) MemConfig->tRRD_S;
  484. FspmUpd->FspmTestConfig.tWTR_L = (UINT8) MemConfig->tWTR_L;
  485. FspmUpd->FspmTestConfig.tWTR_S = (UINT8) MemConfig->tWTR_S;
  486. // TurnAround Timing
  487. // Read-to-Read
  488. FspmUpd->FspmTestConfig.tRd2RdSG = MemConfig->tRd2RdSG;
  489. FspmUpd->FspmTestConfig.tRd2RdDG = MemConfig->tRd2RdDG;
  490. FspmUpd->FspmTestConfig.tRd2RdDR = MemConfig->tRd2RdDR;
  491. FspmUpd->FspmTestConfig.tRd2RdDD = MemConfig->tRd2RdDD;
  492. // Write-to-Read
  493. FspmUpd->FspmTestConfig.tWr2RdSG = MemConfig->tWr2RdSG;
  494. FspmUpd->FspmTestConfig.tWr2RdDG = MemConfig->tWr2RdDG;
  495. FspmUpd->FspmTestConfig.tWr2RdDR = MemConfig->tWr2RdDR;
  496. FspmUpd->FspmTestConfig.tWr2RdDD = MemConfig->tWr2RdDD;
  497. // Write-to-Write
  498. FspmUpd->FspmTestConfig.tWr2WrSG = MemConfig->tWr2WrSG;
  499. FspmUpd->FspmTestConfig.tWr2WrDG = MemConfig->tWr2WrDG;
  500. FspmUpd->FspmTestConfig.tWr2WrDR = MemConfig->tWr2WrDR;
  501. FspmUpd->FspmTestConfig.tWr2WrDD = MemConfig->tWr2WrDD;
  502. // Read-to-Write
  503. FspmUpd->FspmTestConfig.tRd2WrSG = MemConfig->tRd2WrSG;
  504. FspmUpd->FspmTestConfig.tRd2WrDG = MemConfig->tRd2WrDG;
  505. FspmUpd->FspmTestConfig.tRd2WrDR = MemConfig->tRd2WrDR;
  506. FspmUpd->FspmTestConfig.tRd2WrDD = MemConfig->tRd2WrDD;
  507. }
  508. if (MiscPeiPreMemConfig != NULL) {
  509. FspmUpd->FspmConfig.IedSize = MiscPeiPreMemConfig->IedSize;
  510. FspmUpd->FspmConfig.UserBd = MiscPeiPreMemConfig->UserBd;
  511. FspmUpd->FspmConfig.SgDelayAfterPwrEn = MiscPeiPreMemConfig->SgDelayAfterPwrEn;
  512. FspmUpd->FspmConfig.SgDelayAfterHoldReset = MiscPeiPreMemConfig->SgDelayAfterHoldReset;
  513. FspmUpd->FspmConfig.MmioSize = MiscPeiPreMemConfig->MmioSize;
  514. FspmUpd->FspmConfig.MmioSizeAdjustment = MiscPeiPreMemConfig->MmioSizeAdjustment;
  515. FspmUpd->FspmConfig.TsegSize = MiscPeiPreMemConfig->TsegSize;
  516. FspmUpd->FspmTestConfig.SkipExtGfxScan = (UINT8) MiscPeiPreMemConfig->SkipExtGfxScan;
  517. FspmUpd->FspmTestConfig.BdatEnable = (UINT8) MiscPeiPreMemConfig->BdatEnable;
  518. FspmUpd->FspmTestConfig.BdatTestType = (UINT8) MiscPeiPreMemConfig->BdatTestType;
  519. FspmUpd->FspmTestConfig.ScanExtGfxForLegacyOpRom = (UINT8) MiscPeiPreMemConfig->ScanExtGfxForLegacyOpRom;
  520. FspmUpd->FspmTestConfig.LockPTMregs = (UINT8) MiscPeiPreMemConfig->LockPTMregs;
  521. }
  522. if (Vtd != NULL) {
  523. FspmUpd->FspmConfig.X2ApicOptOut = (UINT8) Vtd->X2ApicOptOut;
  524. FspmUpd->FspmConfig.VtdBaseAddress[0] = Vtd->BaseAddress[0];
  525. FspmUpd->FspmConfig.VtdBaseAddress[1] = Vtd->BaseAddress[1];
  526. FspmUpd->FspmConfig.VtdBaseAddress[2] = Vtd->BaseAddress[2];
  527. FspmUpd->FspmTestConfig.VtdDisable = (UINT8) Vtd->VtdDisable;
  528. }
  529. if (PciePeiPreMemConfig != NULL) {
  530. FspmUpd->FspmConfig.DmiGen3ProgramStaticEq = (UINT8) PciePeiPreMemConfig->DmiGen3ProgramStaticEq;
  531. FspmUpd->FspmConfig.Peg0Enable = (UINT8) PciePeiPreMemConfig->Peg0Enable;
  532. FspmUpd->FspmConfig.Peg1Enable = (UINT8) PciePeiPreMemConfig->Peg1Enable;
  533. FspmUpd->FspmConfig.Peg2Enable = (UINT8) PciePeiPreMemConfig->Peg2Enable;
  534. FspmUpd->FspmConfig.Peg3Enable = (UINT8) PciePeiPreMemConfig->Peg3Enable;
  535. FspmUpd->FspmConfig.Peg0MaxLinkSpeed = (UINT8) PciePeiPreMemConfig->Peg0MaxLinkSpeed;
  536. FspmUpd->FspmConfig.Peg1MaxLinkSpeed = (UINT8) PciePeiPreMemConfig->Peg1MaxLinkSpeed;
  537. FspmUpd->FspmConfig.Peg2MaxLinkSpeed = (UINT8) PciePeiPreMemConfig->Peg2MaxLinkSpeed;
  538. FspmUpd->FspmConfig.Peg3MaxLinkSpeed = (UINT8) PciePeiPreMemConfig->Peg3MaxLinkSpeed;
  539. FspmUpd->FspmConfig.Peg0MaxLinkWidth = (UINT8) PciePeiPreMemConfig->Peg0MaxLinkWidth;
  540. FspmUpd->FspmConfig.Peg1MaxLinkWidth = (UINT8) PciePeiPreMemConfig->Peg1MaxLinkWidth;
  541. FspmUpd->FspmConfig.Peg2MaxLinkWidth = (UINT8) PciePeiPreMemConfig->Peg2MaxLinkWidth;
  542. FspmUpd->FspmConfig.Peg3MaxLinkWidth = (UINT8) PciePeiPreMemConfig->Peg3MaxLinkWidth;
  543. FspmUpd->FspmConfig.Peg0PowerDownUnusedLanes = (UINT8) PciePeiPreMemConfig->Peg0PowerDownUnusedLanes;
  544. FspmUpd->FspmConfig.Peg1PowerDownUnusedLanes = (UINT8) PciePeiPreMemConfig->Peg1PowerDownUnusedLanes;
  545. FspmUpd->FspmConfig.Peg2PowerDownUnusedLanes = (UINT8) PciePeiPreMemConfig->Peg2PowerDownUnusedLanes;
  546. FspmUpd->FspmConfig.Peg3PowerDownUnusedLanes = (UINT8) PciePeiPreMemConfig->Peg3PowerDownUnusedLanes;
  547. FspmUpd->FspmConfig.InitPcieAspmAfterOprom = (UINT8) PciePeiPreMemConfig->InitPcieAspmAfterOprom;
  548. FspmUpd->FspmConfig.PegDisableSpreadSpectrumClocking = (UINT8) PciePeiPreMemConfig->PegDisableSpreadSpectrumClocking;
  549. for (Index = 0; Index < SA_DMI_MAX_LANE; Index++) {
  550. FspmUpd->FspmConfig.DmiGen3RootPortPreset[Index] = PciePeiPreMemConfig->DmiGen3RootPortPreset[Index];
  551. FspmUpd->FspmConfig.DmiGen3EndPointPreset[Index] = PciePeiPreMemConfig->DmiGen3EndPointPreset[Index];
  552. FspmUpd->FspmConfig.DmiGen3EndPointHint[Index] = PciePeiPreMemConfig->DmiGen3EndPointHint[Index];
  553. }
  554. for (Index = 0; Index < SA_DMI_MAX_BUNDLE; Index++) {
  555. FspmUpd->FspmConfig.DmiGen3RxCtlePeaking[Index] = PciePeiPreMemConfig->DmiGen3RxCtlePeaking[Index];
  556. }
  557. for (Index = 0; Index < SA_PEG_MAX_BUNDLE ; Index++) {
  558. FspmUpd->FspmConfig.PegGen3RxCtlePeaking[Index] = PciePeiPreMemConfig->PegGen3RxCtlePeaking[Index];
  559. }
  560. FspmUpd->FspmConfig.PegDataPtr = (UINT32) PciePeiPreMemConfig->PegDataPtr;
  561. CopyMem((VOID *)FspmUpd->FspmConfig.PegGpioData, &PciePeiPreMemConfig->PegGpioData, sizeof (PEG_GPIO_DATA));
  562. FspmUpd->FspmConfig.DmiDeEmphasis = PciePeiPreMemConfig->DmiDeEmphasis;
  563. for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) {
  564. FspmUpd->FspmConfig.PegRootPortHPE[Index] = PciePeiPreMemConfig->PegRootPortHPE[Index];
  565. }
  566. FspmUpd->FspmTestConfig.DmiMaxLinkSpeed = (UINT8) PciePeiPreMemConfig->DmiMaxLinkSpeed;
  567. FspmUpd->FspmTestConfig.DmiGen3EqPh2Enable = (UINT8) PciePeiPreMemConfig->DmiGen3EqPh2Enable;
  568. FspmUpd->FspmTestConfig.DmiGen3EqPh3Method = (UINT8) PciePeiPreMemConfig->DmiGen3EqPh3Method;
  569. FspmUpd->FspmTestConfig.Peg0Gen3EqPh2Enable = (UINT8) PciePeiPreMemConfig->Peg0Gen3EqPh2Enable;
  570. FspmUpd->FspmTestConfig.Peg1Gen3EqPh2Enable = (UINT8) PciePeiPreMemConfig->Peg1Gen3EqPh2Enable;
  571. FspmUpd->FspmTestConfig.Peg2Gen3EqPh2Enable = (UINT8) PciePeiPreMemConfig->Peg2Gen3EqPh2Enable;
  572. FspmUpd->FspmTestConfig.Peg3Gen3EqPh2Enable = (UINT8) PciePeiPreMemConfig->Peg3Gen3EqPh2Enable;
  573. FspmUpd->FspmTestConfig.Peg0Gen3EqPh3Method = (UINT8) PciePeiPreMemConfig->Peg0Gen3EqPh3Method;
  574. FspmUpd->FspmTestConfig.Peg1Gen3EqPh3Method = (UINT8) PciePeiPreMemConfig->Peg1Gen3EqPh3Method;
  575. FspmUpd->FspmTestConfig.Peg2Gen3EqPh3Method = (UINT8) PciePeiPreMemConfig->Peg2Gen3EqPh3Method;
  576. FspmUpd->FspmTestConfig.Peg3Gen3EqPh3Method = (UINT8) PciePeiPreMemConfig->Peg3Gen3EqPh3Method;
  577. FspmUpd->FspmTestConfig.PegGen3ProgramStaticEq = (UINT8) PciePeiPreMemConfig->PegGen3ProgramStaticEq;
  578. FspmUpd->FspmTestConfig.Gen3SwEqAlwaysAttempt = (UINT8) PciePeiPreMemConfig->Gen3SwEqAlwaysAttempt;
  579. FspmUpd->FspmTestConfig.Gen3SwEqNumberOfPresets = (UINT8) PciePeiPreMemConfig->Gen3SwEqNumberOfPresets;
  580. FspmUpd->FspmTestConfig.Gen3SwEqEnableVocTest = (UINT8) PciePeiPreMemConfig->Gen3SwEqEnableVocTest;
  581. FspmUpd->FspmTestConfig.PegRxCemTestingMode = (UINT8) PciePeiPreMemConfig->PegRxCemTestingMode;
  582. FspmUpd->FspmTestConfig.PegRxCemLoopbackLane = (UINT8) PciePeiPreMemConfig->PegRxCemLoopbackLane;
  583. FspmUpd->FspmTestConfig.PegGenerateBdatMarginTable = (UINT8) PciePeiPreMemConfig->PegGenerateBdatMarginTable;
  584. FspmUpd->FspmTestConfig.PegRxCemNonProtocolAwareness = (UINT8) PciePeiPreMemConfig->PegRxCemNonProtocolAwareness;
  585. FspmUpd->FspmTestConfig.PegGen3RxCtleOverride = (UINT8) PciePeiPreMemConfig->PegGen3RxCtleOverride;
  586. for (Index = 0; Index < SA_PEG_MAX_LANE; Index++) {
  587. FspmUpd->FspmTestConfig.PegGen3RootPortPreset[Index] = PciePeiPreMemConfig->PegGen3RootPortPreset[Index];
  588. FspmUpd->FspmTestConfig.PegGen3EndPointPreset[Index] = PciePeiPreMemConfig->PegGen3EndPointPreset[Index];
  589. FspmUpd->FspmTestConfig.PegGen3EndPointHint[Index] = PciePeiPreMemConfig->PegGen3EndPointHint[Index];
  590. }
  591. FspmUpd->FspmTestConfig.Gen3SwEqJitterDwellTime = PciePeiPreMemConfig->Gen3SwEqJitterDwellTime;
  592. FspmUpd->FspmTestConfig.Gen3SwEqJitterErrorTarget = PciePeiPreMemConfig->Gen3SwEqJitterErrorTarget;
  593. FspmUpd->FspmTestConfig.Gen3SwEqVocDwellTime = PciePeiPreMemConfig->Gen3SwEqVocDwellTime;
  594. FspmUpd->FspmTestConfig.Gen3SwEqVocErrorTarget = PciePeiPreMemConfig->Gen3SwEqVocErrorTarget;
  595. }
  596. if (GtPreMemConfig != NULL) {
  597. FspmUpd->FspmConfig.PrimaryDisplay = (UINT8) GtPreMemConfig->PrimaryDisplay;
  598. FspmUpd->FspmConfig.InternalGfx = (UINT8) GtPreMemConfig->InternalGraphics;
  599. FspmUpd->FspmConfig.IgdDvmt50PreAlloc = (UINT8) GtPreMemConfig->IgdDvmt50PreAlloc;
  600. FspmUpd->FspmConfig.ApertureSize = (UINT8) GtPreMemConfig->ApertureSize;
  601. FspmUpd->FspmConfig.GttMmAdr = GtPreMemConfig->GttMmAdr;
  602. FspmUpd->FspmConfig.GmAdr = GtPreMemConfig->GmAdr;
  603. FspmUpd->FspmConfig.GttSize = GtPreMemConfig->GttSize;
  604. FspmUpd->FspmConfig.PsmiRegionSize = (UINT8) GtPreMemConfig->PsmiRegionSize;
  605. FspmUpd->FspmConfig.GtPsmiSupport = (UINT8)GtPreMemConfig->GtPsmiSupport;
  606. FspmUpd->FspmTestConfig.PanelPowerEnable = (UINT8) GtPreMemConfig->PanelPowerEnable;
  607. FspmUpd->FspmTestConfig.DeltaT12PowerCycleDelayPreMem = (UINT16) GtPreMemConfig->DeltaT12PowerCycleDelayPreMem;
  608. }
  609. if (SgGpioData != NULL) {
  610. CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie0Gpio, &SgGpioData->SaRtd3Pcie0Gpio, sizeof (SA_PCIE_RTD3_GPIO));
  611. CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie1Gpio, &SgGpioData->SaRtd3Pcie1Gpio, sizeof (SA_PCIE_RTD3_GPIO));
  612. CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie2Gpio, &SgGpioData->SaRtd3Pcie2Gpio, sizeof (SA_PCIE_RTD3_GPIO));
  613. FspmUpd->FspmConfig.RootPortIndex = SgGpioData->RootPortIndex;
  614. }
  615. if (IpuPreMemPolicy != NULL) {
  616. FspmUpd->FspmConfig.SaIpuEnable = (UINT8) IpuPreMemPolicy->SaIpuEnable;
  617. FspmUpd->FspmConfig.SaIpuImrConfiguration = (UINT8) IpuPreMemPolicy->SaIpuImrConfiguration;
  618. }
  619. if (OcPreMemConfig != NULL) {
  620. FspmUpd->FspmConfig.SaOcSupport = (UINT8) OcPreMemConfig->OcSupport;
  621. FspmUpd->FspmConfig.RealtimeMemoryTiming = (UINT8) OcPreMemConfig->RealtimeMemoryTiming;
  622. FspmUpd->FspmConfig.GtVoltageMode = (UINT8) OcPreMemConfig->GtVoltageMode;
  623. FspmUpd->FspmConfig.GtMaxOcRatio = OcPreMemConfig->GtMaxOcRatio;
  624. FspmUpd->FspmConfig.GtVoltageOffset = OcPreMemConfig->GtVoltageOffset;
  625. FspmUpd->FspmConfig.GtVoltageOverride = OcPreMemConfig->GtVoltageOverride;
  626. FspmUpd->FspmConfig.GtExtraTurboVoltage = OcPreMemConfig->GtExtraTurboVoltage;
  627. FspmUpd->FspmConfig.SaVoltageOffset = OcPreMemConfig->SaVoltageOffset;
  628. FspmUpd->FspmConfig.GtusMaxOcRatio = OcPreMemConfig->GtusMaxOcRatio;
  629. FspmUpd->FspmConfig.GtusVoltageMode = (UINT8) OcPreMemConfig->GtusVoltageMode;
  630. FspmUpd->FspmConfig.GtusVoltageOffset = OcPreMemConfig->GtusVoltageOffset;
  631. FspmUpd->FspmConfig.GtusVoltageOverride = OcPreMemConfig->GtusVoltageOverride;
  632. FspmUpd->FspmConfig.GtusExtraTurboVoltage = OcPreMemConfig->GtusExtraTurboVoltage;
  633. }
  634. return EFI_SUCCESS;
  635. }
  636. /**
  637. Performs FSP SA PEI Policy initialization.
  638. @param[in][out] FspsUpd Pointer to FSP UPD Data.
  639. @retval EFI_SUCCESS FSP UPD Data is updated.
  640. @retval EFI_NOT_FOUND Fail to locate required PPI.
  641. @retval Other FSP UPD Data update process fail.
  642. **/
  643. EFI_STATUS
  644. EFIAPI
  645. PeiFspSaPolicyInit (
  646. IN OUT FSPS_UPD *FspsUpd
  647. )
  648. {
  649. EFI_STATUS Status;
  650. SI_POLICY_PPI *SiPolicyPpi;
  651. SA_MISC_PEI_CONFIG *MiscPeiConfig;
  652. GRAPHICS_PEI_CONFIG *GtConfig;
  653. PCIE_PEI_CONFIG *PciePeiConfig;
  654. GNA_CONFIG *GnaConfig;
  655. UINT8 Index;
  656. EFI_BOOT_MODE BootMode;
  657. MiscPeiConfig = NULL;
  658. GtConfig = NULL;
  659. PciePeiConfig = NULL;
  660. GnaConfig = NULL;
  661. //
  662. // @todo This could be cleared up after FSP provides ExitBootServices NotifyPhase.
  663. //
  664. Status = PeiServicesGetBootMode (&BootMode);
  665. ASSERT_EFI_ERROR (Status);
  666. //
  667. // Locate SiPolicyPpi
  668. //
  669. SiPolicyPpi = NULL;
  670. Status = PeiServicesLocatePpi(
  671. &gSiPolicyPpiGuid,
  672. 0,
  673. NULL,
  674. (VOID **)&SiPolicyPpi
  675. );
  676. if ((Status == EFI_SUCCESS) && (SiPolicyPpi != NULL)) {
  677. MiscPeiConfig = NULL;
  678. Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid, (VOID *) &MiscPeiConfig);
  679. ASSERT_EFI_ERROR (Status);
  680. GtConfig = NULL;
  681. Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
  682. ASSERT_EFI_ERROR (Status);
  683. GnaConfig = NULL;
  684. Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGnaConfigGuid, (VOID *) &GnaConfig);
  685. ASSERT_EFI_ERROR (Status);
  686. PciePeiConfig = NULL;
  687. Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSaPciePeiConfigGuid, (VOID *) &PciePeiConfig);
  688. ASSERT_EFI_ERROR (Status);
  689. }
  690. DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Wrapper UpdatePeiSaPolicy\n"));
  691. if (MiscPeiConfig != NULL) {
  692. FspsUpd->FspsConfig.Device4Enable = (UINT8) MiscPeiConfig->Device4Enable;
  693. FspsUpd->FspsConfig.CridEnable = (UINT8) MiscPeiConfig->CridEnable;
  694. FspsUpd->FspsTestConfig.ChapDeviceEnable = (UINT8) MiscPeiConfig->ChapDeviceEnable;
  695. FspsUpd->FspsTestConfig.SkipPamLock = (UINT8) MiscPeiConfig->SkipPamLock;
  696. FspsUpd->FspsTestConfig.EdramTestMode = (UINT8) MiscPeiConfig->EdramTestMode;
  697. }
  698. if (PciePeiConfig != NULL) {
  699. FspsUpd->FspsConfig.DmiAspm = (UINT8) PciePeiConfig->DmiAspm;
  700. FspsUpd->FspsTestConfig.DmiExtSync = (UINT8) PciePeiConfig->DmiExtSync;
  701. FspsUpd->FspsTestConfig.DmiIot = (UINT8) PciePeiConfig->DmiIot;
  702. for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) {
  703. FspsUpd->FspsConfig.PegDeEmphasis[Index] = PciePeiConfig->PegDeEmphasis[Index];
  704. FspsUpd->FspsConfig.PegSlotPowerLimitValue[Index] = PciePeiConfig->PegSlotPowerLimitValue[Index];
  705. FspsUpd->FspsConfig.PegSlotPowerLimitScale[Index] = PciePeiConfig->PegSlotPowerLimitScale[Index];
  706. FspsUpd->FspsConfig.PegPhysicalSlotNumber[Index] = PciePeiConfig->PegPhysicalSlotNumber[Index];
  707. FspsUpd->FspsTestConfig.PegMaxPayload[Index] = PciePeiConfig->PegMaxPayload[Index];
  708. }
  709. }
  710. if (GtConfig != NULL) {
  711. FspsUpd->FspsConfig.PavpEnable = (UINT8) GtConfig->PavpEnable;
  712. FspsUpd->FspsConfig.CdClock = (UINT8) GtConfig->CdClock;
  713. FspsUpd->FspsTestConfig.RenderStandby = (UINT8) GtConfig->RenderStandby;
  714. FspsUpd->FspsTestConfig.PmSupport = (UINT8) GtConfig->PmSupport;
  715. FspsUpd->FspsTestConfig.CdynmaxClampEnable = (UINT8) GtConfig->CdynmaxClampEnable;
  716. FspsUpd->FspsTestConfig.GtFreqMax = (UINT8) GtConfig->GtFreqMax;
  717. FspsUpd->FspsTestConfig.DisableTurboGt = (UINT8) GtConfig->DisableTurboGt;
  718. FspsUpd->FspsConfig.SkipS3CdClockInit = (UINT8)GtConfig->SkipS3CdClockInit;
  719. //
  720. // For FSP, FspsUpd->FspsConfig.PeiGraphicsPeimInit is always enabled as default.
  721. //
  722. FspsUpd->FspsConfig.PeiGraphicsPeimInit = (UINT8) GtConfig->PeiGraphicsPeimInit; // SA: InternalOnly: For Internal validation we still need to enable both Enable/Disable Cases
  723. //
  724. // Update UPD: VBT & LogoPtr
  725. //
  726. if (BootMode == BOOT_ON_S3_RESUME) {
  727. FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32) NULL;
  728. } else {
  729. FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32) GtConfig->GraphicsConfigPtr;
  730. }
  731. DEBUG(( DEBUG_INFO, "VbtPtr from GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr));
  732. FspsUpd->FspsConfig.LogoPtr = (UINT32) GtConfig->LogoPtr;
  733. FspsUpd->FspsConfig.LogoSize = GtConfig->LogoSize;
  734. DEBUG(( DEBUG_INFO, "LogoPtr from PeiFspSaPolicyInit GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoPtr));
  735. DEBUG(( DEBUG_INFO, "LogoSize from PeiFspSaPolicyInit GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoSize));
  736. FspsUpd->FspsConfig.BltBufferAddress = (UINT32) GtConfig->BltBufferAddress;
  737. FspsUpd->FspsConfig.BltBufferSize = (UINT32) GtConfig->BltBufferSize;
  738. //
  739. // Update DDI/DDC configuration
  740. //
  741. FspsUpd->FspsConfig.DdiPortEdp = GtConfig->DdiConfiguration.DdiPortEdp;
  742. FspsUpd->FspsConfig.DdiPortBHpd = GtConfig->DdiConfiguration.DdiPortBHpd;
  743. FspsUpd->FspsConfig.DdiPortCHpd = GtConfig->DdiConfiguration.DdiPortCHpd;
  744. FspsUpd->FspsConfig.DdiPortDHpd = GtConfig->DdiConfiguration.DdiPortDHpd;
  745. FspsUpd->FspsConfig.DdiPortFHpd = GtConfig->DdiConfiguration.DdiPortFHpd;
  746. FspsUpd->FspsConfig.DdiPortBDdc = GtConfig->DdiConfiguration.DdiPortBDdc;
  747. FspsUpd->FspsConfig.DdiPortCDdc = GtConfig->DdiConfiguration.DdiPortCDdc;
  748. FspsUpd->FspsConfig.DdiPortDDdc = GtConfig->DdiConfiguration.DdiPortDDdc;
  749. FspsUpd->FspsConfig.DdiPortFDdc = GtConfig->DdiConfiguration.DdiPortFDdc;
  750. }
  751. if (GnaConfig != NULL) {
  752. FspsUpd->FspsConfig.GnaEnable = (UINT8) GnaConfig->GnaEnable;
  753. #ifdef TESTMENU_FLAG
  754. #endif // TESTMENU_FLAG
  755. }
  756. return EFI_SUCCESS;
  757. }