PeiFspPchPolicyInitLib.c 44 KB

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  1. /** @file
  2. Implementation of Fsp PCH Policy Initialization.
  3. Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <PeiFspPolicyInitLib.h>
  7. #include <Ppi/SiPolicy.h>
  8. #include <Library/MemoryAllocationLib.h>
  9. #include <Library/PeiServicesLib.h>
  10. #include <Library/PchInfoLib.h>
  11. #include <Library/ConfigBlockLib.h>
  12. /**
  13. Performs FSP PCH PEI Policy pre mem initialization.
  14. @param[in][out] FspmUpd Pointer to FSP UPD Data.
  15. @retval EFI_SUCCESS FSP UPD Data is updated.
  16. @retval EFI_NOT_FOUND Fail to locate required PPI.
  17. @retval Other FSP UPD Data update process fail.
  18. **/
  19. EFI_STATUS
  20. EFIAPI
  21. PeiFspPchPolicyInitPreMem (
  22. IN OUT FSPM_UPD *FspmUpd
  23. )
  24. {
  25. EFI_STATUS Status;
  26. UINTN Index;
  27. UINTN MaxPcieRootPorts;
  28. SI_PREMEM_POLICY_PPI *SiPreMemPolicy;
  29. PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig;
  30. PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig;
  31. PCH_DCI_PREMEM_CONFIG *DciPreMemConfig;
  32. PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig;
  33. PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig;
  34. PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;
  35. PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig;
  36. PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig;
  37. PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig;
  38. PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig;
  39. PCH_ISH_PREMEM_CONFIG *IshPreMemConfig;
  40. DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicyPreMem\n"));
  41. DEBUG((DEBUG_INFO | DEBUG_INIT, "FspmUpd = 0x%x\n", FspmUpd));
  42. //
  43. // Locate PchPreMemPolicyPpi
  44. //
  45. SiPreMemPolicy = NULL;
  46. Status = PeiServicesLocatePpi (
  47. &gSiPreMemPolicyPpiGuid,
  48. 0,
  49. NULL,
  50. (VOID **) &SiPreMemPolicy
  51. );
  52. if (EFI_ERROR (Status)) {
  53. return EFI_NOT_FOUND;
  54. }
  55. Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchTraceHubPreMemConfigGuid, (VOID *) &PchTraceHubPreMemConfig);
  56. ASSERT_EFI_ERROR (Status);
  57. Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gSmbusPreMemConfigGuid, (VOID *) &SmbusPreMemConfig);
  58. ASSERT_EFI_ERROR (Status);
  59. Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gDciPreMemConfigGuid, (VOID *) &DciPreMemConfig);
  60. ASSERT_EFI_ERROR (Status);
  61. Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig);
  62. ASSERT_EFI_ERROR (Status);
  63. Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig);
  64. ASSERT_EFI_ERROR (Status);
  65. Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gLpcPreMemConfigGuid, (VOID *) &LpcPreMemConfig);
  66. ASSERT_EFI_ERROR (Status);
  67. Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig);
  68. ASSERT_EFI_ERROR (Status);
  69. Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gWatchDogPreMemConfigGuid, (VOID *) &WdtPreMemConfig);
  70. ASSERT_EFI_ERROR (Status);
  71. Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
  72. ASSERT_EFI_ERROR (Status);
  73. Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHdAudioPreMemConfigGuid, (VOID *) &HdaPreMemConfig);
  74. ASSERT_EFI_ERROR (Status);
  75. Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gIshPreMemConfigGuid, (VOID *) &IshPreMemConfig);
  76. ASSERT_EFI_ERROR (Status);
  77. DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ UpdatePeiPchPolicyPreMem\n"));
  78. //
  79. // Update PCIE RP policies
  80. //
  81. // MaxPcieRootPorts = 16;
  82. MaxPcieRootPorts = GetPchMaxPciePortNum ();
  83. // MaxPcieRootPorts = 16;
  84. FspmUpd->FspmConfig.PcieRpEnableMask = PcieRpPreMemConfig->RpEnabledMask & ((1 << MaxPcieRootPorts) - 1);
  85. FspmUpd->FspmConfig.PcieImrEnabled = PcieRpPreMemConfig->PcieImrEnabled;
  86. FspmUpd->FspmConfig.PcieImrSize = PcieRpPreMemConfig->PcieImrSize;
  87. FspmUpd->FspmConfig.ImrRpSelection = PcieRpPreMemConfig->ImrRpSelection;
  88. //
  89. // Update TraceHub policies
  90. //
  91. FspmUpd->FspmConfig.PchTraceHubMode = (UINT8) PchTraceHubPreMemConfig->EnableMode;
  92. FspmUpd->FspmConfig.PchTraceHubMemReg0Size = (UINT8) PchTraceHubPreMemConfig->MemReg0Size;
  93. FspmUpd->FspmConfig.PchTraceHubMemReg1Size = (UINT8) PchTraceHubPreMemConfig->MemReg1Size;
  94. //
  95. // Update Smbus policies
  96. //
  97. FspmUpd->FspmConfig.SmbusEnable = (UINT8)SmbusPreMemConfig->Enable;
  98. FspmUpd->FspmConfig.SmbusArpEnable = (UINT8)SmbusPreMemConfig->ArpEnable;
  99. FspmUpd->FspmTestConfig.SmbusDynamicPowerGating = (UINT8)SmbusPreMemConfig->DynamicPowerGating;
  100. FspmUpd->FspmTestConfig.SmbusSpdWriteDisable = (UINT8)SmbusPreMemConfig->SpdWriteDisable;
  101. FspmUpd->FspmConfig.PchSmbAlertEnable = (UINT8)SmbusPreMemConfig->SmbAlertEnable;
  102. FspmUpd->FspmConfig.PchSmbusIoBase = (UINT16)SmbusPreMemConfig->SmbusIoBase;
  103. FspmUpd->FspmConfig.PchNumRsvdSmbusAddresses = (UINT8)SmbusPreMemConfig->NumRsvdSmbusAddresses;
  104. FspmUpd->FspmConfig.RsvdSmbusAddressTablePtr = (UINT32)SmbusPreMemConfig->RsvdSmbusAddressTable;
  105. DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ1 UpdatePeiPchPolicyPreMem\n"));
  106. //
  107. // Update Dci policies
  108. //
  109. FspmUpd->FspmConfig.PlatformDebugConsent = (UINT8)DciPreMemConfig->PlatformDebugConsent;
  110. DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ11 UpdatePeiPchPolicyPreMem\n"));
  111. FspmUpd->FspmConfig.DciUsb3TypecUfpDbg = (UINT8)DciPreMemConfig->DciUsb3TypecUfpDbg;
  112. //
  113. // Update HSIO PCIE policies
  114. //
  115. for (Index = 0; Index < MaxPcieRootPorts; Index ++) {
  116. FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable;
  117. FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle;
  118. FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmpEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEnable;
  119. FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmp[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp;
  120. FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmpEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEnable;
  121. FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmp[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp;
  122. FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmpEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEnable;
  123. FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmp[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp;
  124. FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmphEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable;
  125. FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmph[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph;
  126. FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5Enable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable;
  127. FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5;
  128. FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0Enable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable;
  129. FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0;
  130. }
  131. //
  132. // Update HSIO SATA policies
  133. //
  134. for (Index = 0; Index < PCH_MAX_SATA_PORTS; Index ++) {
  135. FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMagEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEnable;
  136. FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMag[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag;
  137. FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMagEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEnable;
  138. FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMag[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag;
  139. FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable;
  140. FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag;
  141. FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable;
  142. FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp;
  143. FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable;
  144. FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp;
  145. FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmpEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmpEnable;
  146. FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmp[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp;
  147. FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmphEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable;
  148. FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmph[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph;
  149. FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmphEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable;
  150. FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmph[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph;
  151. FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmphEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable;
  152. FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmph[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph;
  153. }
  154. DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ2 UpdatePeiPchPolicyPreMem\n"));
  155. // Update LPC policies
  156. //
  157. FspmUpd->FspmConfig.PchLpcEnhancePort8xhDecoding = (UINT8)LpcPreMemConfig->EnhancePort8xhDecoding;
  158. //
  159. // Update Pch General Premem policies
  160. //
  161. FspmUpd->FspmConfig.PchPort80Route = (UINT8)PchGeneralPreMemConfig->Port80Route;
  162. //
  163. // Update Wdt policies
  164. //
  165. FspmUpd->FspmTestConfig.WdtDisableAndLock = (UINT8)WdtPreMemConfig->DisableAndLock;
  166. //
  167. // HdAudioConfig
  168. //
  169. FspmUpd->FspmConfig.PchHdaEnable = (UINT8)HdaPreMemConfig->Enable;
  170. //
  171. // IshConfig
  172. //
  173. FspmUpd->FspmConfig.PchIshEnable = (UINT8)IshPreMemConfig->Enable;
  174. DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ3 UpdatePeiPchPolicyPreMem\n"));
  175. return EFI_SUCCESS;
  176. }
  177. /**
  178. Performs FSP PCH PEI Policy initialization.
  179. @param[in][out] FspsUpd Pointer to FSP UPD Data.
  180. @retval EFI_SUCCESS FSP UPD Data is updated.
  181. @retval EFI_NOT_FOUND Fail to locate required PPI.
  182. @retval Other FSP UPD Data update process fail.
  183. **/
  184. EFI_STATUS
  185. EFIAPI
  186. PeiFspPchPolicyInit (
  187. IN OUT FSPS_UPD *FspsUpd
  188. )
  189. {
  190. EFI_STATUS Status;
  191. UINTN Index;
  192. UINTN MaxPcieRootPorts;
  193. UINT8 Data8;
  194. SI_POLICY_PPI *SiPolicy;
  195. PCH_LAN_CONFIG *LanConfig;
  196. PCH_HDAUDIO_CONFIG *HdAudioConfig;
  197. PCH_SCS_CONFIG *ScsConfig;
  198. PCH_ISH_CONFIG *IshConfig;
  199. PCH_SATA_CONFIG *SataConfig;
  200. USB_CONFIG *UsbConfig;
  201. PCH_SERIAL_IO_CONFIG *SerialIoConfig;
  202. PCH_INTERRUPT_CONFIG *InterruptConfig;
  203. PCH_LOCK_DOWN_CONFIG *LockDownConfig;
  204. PCH_CNVI_CONFIG *CnviConfig;
  205. PCH_HSIO_CONFIG *HsioConfig;
  206. PCH_ESPI_CONFIG *EspiConfig;
  207. PCH_PCIE_CONFIG *PcieRpConfig;
  208. PCH_DMI_CONFIG *DmiConfig;
  209. PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig;
  210. PCH_IOAPIC_CONFIG *IoApicConfig;
  211. PCH_P2SB_CONFIG *P2sbConfig;
  212. PCH_GENERAL_CONFIG *PchGeneralConfig;
  213. PCH_PM_CONFIG *PmConfig;
  214. PCH_LPC_SIRQ_CONFIG *PchSerialIrqConfig;
  215. PCH_THERMAL_CONFIG *PchThermalConfig;
  216. DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n"));
  217. //
  218. // Locate SiPolicyPpi
  219. //
  220. SiPolicy = NULL;
  221. Status = PeiServicesLocatePpi (
  222. &gSiPolicyPpiGuid,
  223. 0,
  224. NULL,
  225. (VOID **) &SiPolicy
  226. );
  227. if (EFI_ERROR (Status)) {
  228. return EFI_NOT_FOUND;
  229. }
  230. Status = GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) &LanConfig);
  231. ASSERT_EFI_ERROR (Status);
  232. Status = GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig);
  233. ASSERT_EFI_ERROR (Status);
  234. Status = GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) &ScsConfig);
  235. ASSERT_EFI_ERROR (Status);
  236. Status = GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) &IshConfig);
  237. ASSERT_EFI_ERROR (Status);
  238. Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig);
  239. ASSERT_EFI_ERROR (Status);
  240. Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig);
  241. ASSERT_EFI_ERROR (Status);
  242. Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
  243. ASSERT_EFI_ERROR (Status);
  244. Status = GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VOID *) &InterruptConfig);
  245. ASSERT_EFI_ERROR (Status);
  246. Status = GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
  247. ASSERT_EFI_ERROR (Status);
  248. Status = GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID *) &PcieRpConfig);
  249. ASSERT_EFI_ERROR (Status);
  250. Status = GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) &DmiConfig);
  251. ASSERT_EFI_ERROR (Status);
  252. Status = GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig);
  253. ASSERT_EFI_ERROR (Status);
  254. Status = GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID *) &IoApicConfig);
  255. ASSERT_EFI_ERROR (Status);
  256. Status = GetConfigBlock ((VOID *) SiPolicy, &gP2sbConfigGuid, (VOID *) &P2sbConfig);
  257. ASSERT_EFI_ERROR (Status);
  258. Status = GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
  259. ASSERT_EFI_ERROR (Status);
  260. Status = GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &PmConfig);
  261. ASSERT_EFI_ERROR (Status);
  262. Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VOID *) &PchSerialIrqConfig);
  263. ASSERT_EFI_ERROR (Status);
  264. Status = GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID *) &PchThermalConfig);
  265. ASSERT_EFI_ERROR (Status);
  266. Status = GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *) &CnviConfig);
  267. ASSERT_EFI_ERROR (Status);
  268. Status = GetConfigBlock ((VOID *) SiPolicy, &gHsioConfigGuid, (VOID *) &HsioConfig);
  269. ASSERT_EFI_ERROR (Status);
  270. Status = GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID *) &EspiConfig);
  271. ASSERT_EFI_ERROR (Status);
  272. //
  273. // Update LAN policies
  274. //
  275. FspsUpd->FspsConfig.PchLanEnable = (UINT8)LanConfig->Enable;
  276. FspsUpd->FspsConfig.PchLanLtrEnable = (UINT8)LanConfig->LtrEnable;
  277. //
  278. // Update HDA policies
  279. //
  280. FspsUpd->FspsConfig.PchHdaDspEnable = (UINT8)HdAudioConfig->DspEnable;
  281. FspsUpd->FspsConfig.PchHdaPme = (UINT8)HdAudioConfig->Pme;
  282. FspsUpd->FspsConfig.PchHdaVcType = (UINT8)HdAudioConfig->VcType;
  283. FspsUpd->FspsConfig.PchHdaLinkFrequency = (UINT8)HdAudioConfig->HdAudioLinkFrequency;
  284. FspsUpd->FspsConfig.PchHdaIDispLinkFrequency = (UINT8)HdAudioConfig->IDispLinkFrequency;
  285. FspsUpd->FspsConfig.PchHdaIDispLinkTmode = (UINT8)HdAudioConfig->IDispLinkTmode;
  286. FspsUpd->FspsConfig.PchHdaDspUaaCompliance = (UINT8)HdAudioConfig->DspUaaCompliance;
  287. FspsUpd->FspsConfig.PchHdaIDispCodecDisconnect = (UINT8)HdAudioConfig->IDispCodecDisconnect;
  288. FspsUpd->FspsConfig.PchHdaCodecSxWakeCapability = (UINT8)HdAudioConfig->CodecSxWakeCapability;
  289. FspsUpd->FspsTestConfig.PchHdaResetWaitTimer = (UINT16)HdAudioConfig->ResetWaitTimer;
  290. FspsUpd->FspsConfig.PchHdaVerbTableEntryNum = HdAudioConfig->VerbTableEntryNum;
  291. FspsUpd->FspsConfig.PchHdaVerbTablePtr = HdAudioConfig->VerbTablePtr;
  292. FspsUpd->FspsConfig.PchHdaAudioLinkHda = (UINT8)HdAudioConfig->AudioLinkHda;
  293. FspsUpd->FspsConfig.PchHdaAudioLinkDmic0 = (UINT8)HdAudioConfig->AudioLinkDmic0;
  294. FspsUpd->FspsConfig.PchHdaAudioLinkDmic1 = (UINT8)HdAudioConfig->AudioLinkDmic1;
  295. FspsUpd->FspsConfig.PchHdaAudioLinkSsp0 = (UINT8)HdAudioConfig->AudioLinkSsp0;
  296. FspsUpd->FspsConfig.PchHdaAudioLinkSsp1 = (UINT8)HdAudioConfig->AudioLinkSsp1;
  297. FspsUpd->FspsConfig.PchHdaAudioLinkSsp2 = (UINT8)HdAudioConfig->AudioLinkSsp2;
  298. FspsUpd->FspsConfig.PchHdaAudioLinkSndw1 = (UINT8)HdAudioConfig->AudioLinkSndw1;
  299. FspsUpd->FspsConfig.PchHdaAudioLinkSndw2 = (UINT8)HdAudioConfig->AudioLinkSndw2;
  300. FspsUpd->FspsConfig.PchHdaAudioLinkSndw3 = (UINT8)HdAudioConfig->AudioLinkSndw3;
  301. FspsUpd->FspsConfig.PchHdaAudioLinkSndw4 = (UINT8)HdAudioConfig->AudioLinkSndw4;
  302. FspsUpd->FspsConfig.PchHdaSndwBufferRcomp = (UINT8)HdAudioConfig->SndwBufferRcomp;
  303. //
  304. // Update SCS policies
  305. //
  306. FspsUpd->FspsConfig.ScsEmmcEnabled = (UINT8)ScsConfig->ScsEmmcEnabled;
  307. FspsUpd->FspsConfig.ScsEmmcHs400Enabled = (UINT8)ScsConfig->ScsEmmcHs400Enabled;
  308. FspsUpd->FspsConfig.ScsSdCardEnabled = (UINT8)ScsConfig->ScsSdcardEnabled;
  309. FspsUpd->FspsConfig.SdCardPowerEnableActiveHigh = (UINT8)ScsConfig->SdCardPowerEnableActiveHigh;
  310. #ifdef CFL_SIMICS
  311. FspsUpd->FspsConfig.ScsUfsEnabled = 0;
  312. #else
  313. FspsUpd->FspsConfig.ScsUfsEnabled = (UINT8)ScsConfig->ScsUfsEnabled;
  314. #endif
  315. FspsUpd->FspsConfig.PchScsEmmcHs400TuningRequired = (UINT8)ScsConfig->ScsEmmcHs400TuningRequired;
  316. FspsUpd->FspsConfig.PchScsEmmcHs400DllDataValid = (UINT8)ScsConfig->ScsEmmcHs400DllDataValid;
  317. FspsUpd->FspsConfig.PchScsEmmcHs400RxStrobeDll1 = (UINT8)ScsConfig->ScsEmmcHs400RxStrobeDll1;
  318. FspsUpd->FspsConfig.PchScsEmmcHs400TxDataDll = (UINT8)ScsConfig->ScsEmmcHs400TxDataDll;
  319. FspsUpd->FspsConfig.PchScsEmmcHs400DriverStrength = (UINT8)ScsConfig->ScsEmmcHs400DriverStrength;
  320. //
  321. // Update ISH policies
  322. //
  323. FspsUpd->FspsConfig.PchIshSpiGpioAssign = (UINT8)IshConfig->SpiGpioAssign;
  324. FspsUpd->FspsConfig.PchIshUart0GpioAssign = (UINT8)IshConfig->Uart0GpioAssign;
  325. FspsUpd->FspsConfig.PchIshUart1GpioAssign = (UINT8)IshConfig->Uart1GpioAssign;
  326. FspsUpd->FspsConfig.PchIshI2c0GpioAssign = (UINT8)IshConfig->I2c0GpioAssign;
  327. FspsUpd->FspsConfig.PchIshI2c1GpioAssign = (UINT8)IshConfig->I2c1GpioAssign;
  328. FspsUpd->FspsConfig.PchIshI2c2GpioAssign = (UINT8)IshConfig->I2c2GpioAssign;
  329. FspsUpd->FspsConfig.PchIshGp0GpioAssign = (UINT8)IshConfig->Gp0GpioAssign;
  330. FspsUpd->FspsConfig.PchIshGp1GpioAssign = (UINT8)IshConfig->Gp1GpioAssign;
  331. FspsUpd->FspsConfig.PchIshGp2GpioAssign = (UINT8)IshConfig->Gp2GpioAssign;
  332. FspsUpd->FspsConfig.PchIshGp3GpioAssign = (UINT8)IshConfig->Gp3GpioAssign;
  333. FspsUpd->FspsConfig.PchIshGp4GpioAssign = (UINT8)IshConfig->Gp4GpioAssign;
  334. FspsUpd->FspsConfig.PchIshGp5GpioAssign = (UINT8)IshConfig->Gp5GpioAssign;
  335. FspsUpd->FspsConfig.PchIshGp6GpioAssign = (UINT8)IshConfig->Gp6GpioAssign;
  336. FspsUpd->FspsConfig.PchIshGp7GpioAssign = (UINT8)IshConfig->Gp7GpioAssign;
  337. FspsUpd->FspsConfig.PchIshPdtUnlock = (UINT8)IshConfig->PdtUnlock;
  338. //
  339. // Update PCIE RP RootPort policies
  340. //
  341. MaxPcieRootPorts = GetPchMaxPciePortNum ();
  342. FspsUpd->FspsConfig.PcieRpDpcMask = 0;
  343. FspsUpd->FspsConfig.PcieRpDpcExtensionsMask = 0;
  344. FspsUpd->FspsConfig.PcieRpPtmMask = 0;
  345. for (Index = 0; Index < MaxPcieRootPorts; Index ++) {
  346. FspsUpd->FspsConfig.PcieRpHotPlug[Index] = (UINT8)PcieRpConfig->RootPort[Index].HotPlug;
  347. FspsUpd->FspsConfig.PcieRpSlotImplemented[Index] = (UINT8)PcieRpConfig->RootPort[Index].SlotImplemented;
  348. FspsUpd->FspsConfig.PcieRpPmSci[Index] = (UINT8)PcieRpConfig->RootPort[Index].PmSci;
  349. FspsUpd->FspsConfig.PcieRpExtSync[Index] = (UINT8)PcieRpConfig->RootPort[Index].ExtSync;
  350. FspsUpd->FspsConfig.PcieRpTransmitterHalfSwing[Index] = (UINT8)PcieRpConfig->RootPort[Index].TransmitterHalfSwing;
  351. FspsUpd->FspsConfig.PcieRpClkReqDetect[Index] = (UINT8)PcieRpConfig->RootPort[Index].ClkReqDetect;
  352. FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[Index] = (UINT8)PcieRpConfig->RootPort[Index].AdvancedErrorReporting;
  353. FspsUpd->FspsConfig.PcieRpUnsupportedRequestReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].UnsupportedRequestReport;
  354. FspsUpd->FspsConfig.PcieRpFatalErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].FatalErrorReport;
  355. FspsUpd->FspsConfig.PcieRpNoFatalErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].NoFatalErrorReport;
  356. FspsUpd->FspsConfig.PcieRpCorrectableErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].CorrectableErrorReport;
  357. FspsUpd->FspsConfig.PcieRpSystemErrorOnFatalError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnFatalError;
  358. FspsUpd->FspsConfig.PcieRpSystemErrorOnNonFatalError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnNonFatalError;
  359. FspsUpd->FspsConfig.PcieRpSystemErrorOnCorrectableError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnCorrectableError;
  360. FspsUpd->FspsConfig.PcieRpMaxPayload[Index] = (UINT8)PcieRpConfig->RootPort[Index].MaxPayload;
  361. if (PcieRpConfig->RootPort[Index].DpcEnabled) {
  362. FspsUpd->FspsConfig.PcieRpDpcMask |= (BIT0<<Index);
  363. }
  364. if (PcieRpConfig->RootPort[Index].RpDpcExtensionsEnabled) {
  365. FspsUpd->FspsConfig.PcieRpDpcExtensionsMask |= (BIT0<<Index);
  366. }
  367. if (PcieRpConfig->RootPort[Index].PtmEnabled) {
  368. FspsUpd->FspsConfig.PcieRpPtmMask |= (BIT0<<Index);
  369. }
  370. FspsUpd->FspsConfig.PcieRpPcieSpeed[Index] = (UINT8)PcieRpConfig->RootPort[Index].PcieSpeed;
  371. FspsUpd->FspsConfig.PcieRpGen3EqPh3Method[Index] = (UINT8)PcieRpConfig->RootPort[Index].Gen3EqPh3Method;
  372. FspsUpd->FspsConfig.PcieRpPhysicalSlotNumber[Index] = (UINT8)PcieRpConfig->RootPort[Index].PhysicalSlotNumber;
  373. FspsUpd->FspsConfig.PcieRpCompletionTimeout[Index] = (UINT8)PcieRpConfig->RootPort[Index].CompletionTimeout;
  374. FspsUpd->FspsConfig.PcieRpAspm[Index] = (UINT8)PcieRpConfig->RootPort[Index].Aspm;
  375. FspsUpd->FspsConfig.PcieRpL1Substates[Index] = (UINT8)PcieRpConfig->RootPort[Index].L1Substates;
  376. FspsUpd->FspsConfig.PcieRpLtrEnable[Index] = (UINT8)PcieRpConfig->RootPort[Index].LtrEnable;
  377. FspsUpd->FspsConfig.PcieRpLtrConfigLock[Index] = (UINT8)PcieRpConfig->RootPort[Index].LtrConfigLock;
  378. FspsUpd->FspsConfig.PcieRpAcsEnabled[Index] = (UINT8)PcieRpConfig->RootPort[Index].AcsEnabled;
  379. FspsUpd->FspsConfig.PcieRpDetectTimeoutMs[Index] = (UINT16)PcieRpConfig->RootPort[Index].DetectTimeoutMs;
  380. FspsUpd->FspsConfig.PcieRootPortGen2PllL1CgDisable[Index] = (UINT8)PcieRpConfig->RootPort[Index].PcieRootPortGen2PllL1CgDisable;
  381. FspsUpd->FspsTestConfig.PcieRpLtrMaxSnoopLatency[Index] = (UINT16)PcieRpConfig->RootPort[Index].LtrMaxSnoopLatency;
  382. FspsUpd->FspsTestConfig.PcieRpLtrMaxNoSnoopLatency[Index] = (UINT16)PcieRpConfig->RootPort[Index].LtrMaxNoSnoopLatency;
  383. FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMode[Index] = (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMode;
  384. FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMultiplier[Index] = (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMultiplier;
  385. FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideValue;
  386. FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMode[Index] = (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMode;
  387. FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMultiplier[Index] = (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier;
  388. FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideValue;
  389. FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitScale[Index] = (UINT8)PcieRpConfig->RootPort[Index].SlotPowerLimitScale;
  390. FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].SlotPowerLimitValue;
  391. FspsUpd->FspsTestConfig.PcieRpUptp[Index] = (UINT8)PcieRpConfig->RootPort[Index].Uptp;
  392. FspsUpd->FspsTestConfig.PcieRpDptp[Index] = (UINT8)PcieRpConfig->RootPort[Index].Dptp;
  393. }
  394. for (Index = 0; Index < GetPchMaxPcieClockNum (); Index ++) {
  395. FspsUpd->FspsConfig.PcieClkSrcUsage[Index] = PcieRpConfig->PcieClock[Index].Usage;
  396. FspsUpd->FspsConfig.PcieClkSrcClkReq[Index] = PcieRpConfig->PcieClock[Index].ClkReq;
  397. }
  398. //
  399. // Update PCIE RP EqPh3LaneParam policies
  400. //
  401. for (Index = 0; Index < MaxPcieRootPorts; Index ++) {
  402. FspsUpd->FspsConfig.PcieEqPh3LaneParamCm[Index] = (UINT8)PcieRpConfig->EqPh3LaneParam[Index].Cm;
  403. FspsUpd->FspsConfig.PcieEqPh3LaneParamCp[Index] = (UINT8)PcieRpConfig->EqPh3LaneParam[Index].Cp;
  404. }
  405. //
  406. // Update PCIE RP SwEqCoeffList policies
  407. //
  408. for (Index = 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index ++) {
  409. FspsUpd->FspsConfig.PcieSwEqCoeffListCm[Index] = (UINT8)PcieRpConfig->SwEqCoeffList[Index].Cm;
  410. FspsUpd->FspsConfig.PcieSwEqCoeffListCp[Index] = (UINT8)PcieRpConfig->SwEqCoeffList[Index].Cp;
  411. }
  412. //
  413. // Update PCIE RP policies
  414. //
  415. FspsUpd->FspsTestConfig.PcieEnablePort8xhDecode = (UINT8)PcieRpConfig->EnablePort8xhDecode;
  416. FspsUpd->FspsTestConfig.PchPciePort8xhDecodePortIndex = (UINT8)PcieRpConfig->PchPciePort8xhDecodePortIndex;
  417. FspsUpd->FspsConfig.PcieDisableRootPortClockGating = (UINT8)PcieRpConfig->DisableRootPortClockGating;
  418. FspsUpd->FspsConfig.PcieEnablePeerMemoryWrite = (UINT8)PcieRpConfig->EnablePeerMemoryWrite;
  419. FspsUpd->FspsConfig.PcieComplianceTestMode = (UINT8)PcieRpConfig->ComplianceTestMode;
  420. FspsUpd->FspsConfig.PcieRpFunctionSwap = (UINT8)PcieRpConfig->RpFunctionSwap;
  421. FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = PcieRpConfig->PcieDeviceOverrideTablePtr;
  422. //
  423. // Update Sata Policies
  424. //
  425. FspsUpd->FspsConfig.SataEnable = (UINT8)SataConfig->Enable;
  426. FspsUpd->FspsTestConfig.SataTestMode = (UINT8)SataConfig->TestMode;
  427. FspsUpd->FspsConfig.SataSalpSupport = (UINT8)SataConfig->SalpSupport;
  428. FspsUpd->FspsConfig.SataPwrOptEnable = (UINT8)SataConfig->PwrOptEnable;
  429. FspsUpd->FspsConfig.EsataSpeedLimit = (UINT8)SataConfig->EsataSpeedLimit;
  430. FspsUpd->FspsConfig.SataLedEnable = (UINT8)SataConfig->LedEnable;
  431. FspsUpd->FspsConfig.SataMode = (UINT8)SataConfig->SataMode;
  432. FspsUpd->FspsConfig.SataSpeedLimit = (UINT8)SataConfig->SpeedLimit;
  433. for (Index = 0; Index < PCH_MAX_SATA_PORTS; Index++) {
  434. FspsUpd->FspsConfig.SataPortsEnable[Index] = (UINT8)SataConfig->PortSettings[Index].Enable;
  435. FspsUpd->FspsConfig.SataPortsHotPlug[Index] = (UINT8)SataConfig->PortSettings[Index].HotPlug;
  436. FspsUpd->FspsConfig.SataPortsInterlockSw[Index] = (UINT8)SataConfig->PortSettings[Index].InterlockSw;
  437. FspsUpd->FspsConfig.SataPortsExternal[Index] = (UINT8)SataConfig->PortSettings[Index].External;
  438. FspsUpd->FspsConfig.SataPortsSpinUp[Index] = (UINT8)SataConfig->PortSettings[Index].SpinUp;
  439. FspsUpd->FspsConfig.SataPortsSolidStateDrive[Index] = (UINT8)SataConfig->PortSettings[Index].SolidStateDrive;
  440. FspsUpd->FspsConfig.SataPortsDevSlp[Index] = (UINT8)SataConfig->PortSettings[Index].DevSlp;
  441. FspsUpd->FspsConfig.SataPortsEnableDitoConfig[Index] = (UINT8)SataConfig->PortSettings[Index].EnableDitoConfig;
  442. FspsUpd->FspsConfig.SataPortsDmVal[Index] = (UINT8)SataConfig->PortSettings[Index].DmVal;
  443. FspsUpd->FspsConfig.SataPortsDitoVal[Index] = (UINT16)SataConfig->PortSettings[Index].DitoVal;
  444. FspsUpd->FspsConfig.SataPortsZpOdd[Index] = (UINT8)SataConfig->PortSettings[Index].ZpOdd;
  445. }
  446. FspsUpd->FspsConfig.SataRstRaidDeviceId = (UINT8)SataConfig->Rst.RaidDeviceId;
  447. FspsUpd->FspsConfig.SataRstInterrupt = (UINT8)SataConfig->Rst.SataRstInterrupt;
  448. FspsUpd->FspsConfig.SataRstRaid0 = (UINT8)SataConfig->Rst.Raid0;
  449. FspsUpd->FspsConfig.SataRstRaid1 = (UINT8)SataConfig->Rst.Raid1;
  450. FspsUpd->FspsConfig.SataRstRaid10 = (UINT8)SataConfig->Rst.Raid10;
  451. FspsUpd->FspsConfig.SataRstRaid5 = (UINT8)SataConfig->Rst.Raid5;
  452. FspsUpd->FspsConfig.SataRstIrrt = (UINT8)SataConfig->Rst.Irrt;
  453. FspsUpd->FspsConfig.SataRstOromUiBanner = (UINT8)SataConfig->Rst.OromUiBanner;
  454. FspsUpd->FspsConfig.SataRstOromUiDelay = (UINT8)SataConfig->Rst.OromUiDelay;
  455. FspsUpd->FspsConfig.SataRstHddUnlock = (UINT8)SataConfig->Rst.HddUnlock;
  456. FspsUpd->FspsConfig.SataRstLedLocate = (UINT8)SataConfig->Rst.LedLocate;
  457. FspsUpd->FspsConfig.SataRstIrrtOnly = (UINT8)SataConfig->Rst.IrrtOnly;
  458. FspsUpd->FspsConfig.SataRstSmartStorage = (UINT8)SataConfig->Rst.SmartStorage;
  459. FspsUpd->FspsConfig.SataRstOptaneMemory = (UINT8)SataConfig->Rst.OptaneMemory;
  460. FspsUpd->FspsConfig.SataRstLegacyOrom = (UINT8)SataConfig->Rst.LegacyOrom;
  461. FspsUpd->FspsConfig.SataRstCpuAttachedStorage = (UINT8)SataConfig->Rst.CpuAttachedStorage;
  462. for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
  463. FspsUpd->FspsConfig.SataRstPcieEnable[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].Enable;
  464. FspsUpd->FspsConfig.SataRstPcieStoragePort[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].RstPcieStoragePort;
  465. FspsUpd->FspsConfig.SataRstPcieDeviceResetDelay[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].DeviceResetDelay;
  466. }
  467. FspsUpd->FspsConfig.SataP0T1M = (UINT8)SataConfig->ThermalThrottling.P0T1M;
  468. FspsUpd->FspsConfig.SataP0T2M = (UINT8)SataConfig->ThermalThrottling.P0T2M;
  469. FspsUpd->FspsConfig.SataP0T3M = (UINT8)SataConfig->ThermalThrottling.P0T3M;
  470. FspsUpd->FspsConfig.SataP0TDisp = (UINT8)SataConfig->ThermalThrottling.P0TDisp;
  471. FspsUpd->FspsConfig.SataP1T1M = (UINT8)SataConfig->ThermalThrottling.P1T1M;
  472. FspsUpd->FspsConfig.SataP1T2M = (UINT8)SataConfig->ThermalThrottling.P1T2M;
  473. FspsUpd->FspsConfig.SataP1T3M = (UINT8)SataConfig->ThermalThrottling.P1T3M;
  474. FspsUpd->FspsConfig.SataP1TDisp = (UINT8)SataConfig->ThermalThrottling.P1TDisp;
  475. FspsUpd->FspsConfig.SataP0Tinact = (UINT8)SataConfig->ThermalThrottling.P0Tinact;
  476. FspsUpd->FspsConfig.SataP0TDispFinit = (UINT8)SataConfig->ThermalThrottling.P0TDispFinit;
  477. FspsUpd->FspsConfig.SataP1Tinact = (UINT8)SataConfig->ThermalThrottling.P1Tinact;
  478. FspsUpd->FspsConfig.SataP1TDispFinit = (UINT8)SataConfig->ThermalThrottling.P1TDispFinit;
  479. FspsUpd->FspsConfig.SataThermalSuggestedSetting = (UINT8)SataConfig->ThermalThrottling.SuggestedSetting;
  480. //
  481. // Update USB policies
  482. //
  483. FspsUpd->FspsConfig.PchEnableComplianceMode = (UINT8)UsbConfig->EnableComplianceMode;
  484. FspsUpd->FspsConfig.UsbPdoProgramming = (UINT8)UsbConfig->PdoProgramming;
  485. FspsUpd->FspsConfig.PchUsbOverCurrentEnable = (UINT8)UsbConfig->OverCurrentEnable;
  486. FspsUpd->FspsConfig.PchUsb2PhySusPgEnable = (UINT8)UsbConfig->Usb2PhySusPgEnable;
  487. FspsUpd->FspsTestConfig.PchXhciOcLock = (UINT8)UsbConfig->XhciOcLock;
  488. for (Index = 0; Index < PCH_MAX_USB2_PORTS; Index++) {
  489. FspsUpd->FspsConfig.PortUsb20Enable[Index] = (UINT8)UsbConfig->PortUsb20[Index].Enable;
  490. FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] = (UINT8)UsbConfig->PortUsb20[Index].OverCurrentPin;
  491. FspsUpd->FspsConfig.Usb2AfePetxiset[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Petxiset;
  492. FspsUpd->FspsConfig.Usb2AfeTxiset[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Txiset;
  493. FspsUpd->FspsConfig.Usb2AfePredeemp[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Predeemp;
  494. FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Pehalfbit;
  495. }
  496. for (Index = 0; Index < PCH_MAX_USB3_PORTS; Index++) {
  497. FspsUpd->FspsConfig.PortUsb30Enable[Index] = (UINT8)UsbConfig->PortUsb30[Index].Enable;
  498. FspsUpd->FspsConfig.Usb3OverCurrentPin[Index] = (UINT8)UsbConfig->PortUsb30[Index].OverCurrentPin;
  499. FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDeEmphEnable;
  500. FspsUpd->FspsConfig.Usb3HsioTxDeEmph[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDeEmph;
  501. FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmpEnable[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDownscaleAmpEnable;
  502. FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmp[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDownscaleAmp;
  503. Data8 = 0;
  504. Data8 |= UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfgEnable ? B_XHCI_HSIO_CTRL_ADAPT_OFFSET_CFG_EN : 0;
  505. Data8 |= UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelNEnable ? B_XHCI_HSIO_FILTER_SELECT_N_EN : 0;
  506. Data8 |= UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelPEnable ? B_XHCI_HSIO_FILTER_SELECT_P_EN : 0;
  507. Data8 |= UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnResEnable ? B_XHCI_HSIO_LFPS_CFG_PULLUP_DWN_RES_EN : 0;
  508. FspsUpd->FspsConfig.PchUsbHsioRxTuningEnable[Index] = Data8;
  509. Data8 = ((UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfg & 0x1F) << N_XHCI_UPD_HSIO_CTRL_ADAPT_OFFSET_CFG) |
  510. ((UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnRes & 0x7) << N_XHCI_UPD_HSIO_LFPS_CFG_PULLUP_DWN_RES);
  511. FspsUpd->FspsConfig.PchUsbHsioRxTuningParameters[Index] = Data8;
  512. Data8 = ((UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelN & 0x7) << N_XHCI_UPD_HSIO_FILTER_SELECT_N) |
  513. ((UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelP & 0x7) << N_XHCI_UPD_HSIO_FILTER_SELECT_P);
  514. FspsUpd->FspsConfig.PchUsbHsioFilterSel[Index] = Data8;
  515. }
  516. FspsUpd->FspsConfig.XdciEnable = (UINT8)UsbConfig->XdciConfig.Enable;
  517. //
  518. // Update SerialIo policies
  519. //
  520. for (Index = 0; Index < GetPchMaxSerialIoControllersNum (); Index++) {
  521. FspsUpd->FspsConfig.SerialIoDevMode[Index] = SerialIoConfig->DevMode[Index];
  522. }
  523. for (Index = 0; Index < GetPchMaxSerialIoSpiControllersNum (); Index++) {
  524. FspsUpd->FspsConfig.SerialIoSpiCsPolarity[Index] = SerialIoConfig->SpiCsPolarity[Index];
  525. }
  526. for (Index = 0; Index < GetPchMaxSerialIoUartControllersNum (); Index++) {
  527. FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[Index] = SerialIoConfig->UartHwFlowCtrl[Index];
  528. }
  529. for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++) {
  530. FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[Index] = SerialIoConfig->I2cPadsTermination[Index];
  531. }
  532. FspsUpd->FspsConfig.SerialIoDebugUartNumber = (UINT8)SerialIoConfig->DebugUartNumber;
  533. FspsUpd->FspsConfig.SerialIoEnableDebugUartAfterPost = (UINT8)SerialIoConfig->EnableDebugUartAfterPost;
  534. FspsUpd->FspsConfig.SerialIoUart0PinMuxing = (UINT8)SerialIoConfig->Uart0PinMuxing;
  535. //
  536. // Update Interrupt policies
  537. //
  538. FspsUpd->FspsConfig.DevIntConfigPtr = (UINT32)InterruptConfig->DevIntConfig;
  539. FspsUpd->FspsConfig.NumOfDevIntConfig = InterruptConfig->NumOfDevIntConfig;
  540. for (Index = 0; Index < PCH_MAX_PXRC_CONFIG; Index ++) {
  541. FspsUpd->FspsConfig.PxRcConfig[Index] = (UINT8)InterruptConfig->PxRcConfig[Index];
  542. }
  543. FspsUpd->FspsConfig.GpioIrqRoute = (UINT8)InterruptConfig->GpioIrqRoute;
  544. FspsUpd->FspsConfig.SciIrqSelect = (UINT8)InterruptConfig->SciIrqSelect;
  545. FspsUpd->FspsConfig.TcoIrqSelect = (UINT8)InterruptConfig->TcoIrqSelect;
  546. FspsUpd->FspsConfig.TcoIrqEnable = (UINT8)InterruptConfig->TcoIrqEnable;
  547. //
  548. // Update LockDown policies
  549. //
  550. FspsUpd->FspsTestConfig.PchLockDownGlobalSmi = (UINT8)LockDownConfig->GlobalSmi;
  551. FspsUpd->FspsTestConfig.PchLockDownBiosInterface = (UINT8)LockDownConfig->BiosInterface;
  552. FspsUpd->FspsConfig.PchLockDownBiosLock = (UINT8)LockDownConfig->BiosLock;
  553. FspsUpd->FspsConfig.PchLockDownRtcMemoryLock = (UINT8)LockDownConfig->RtcMemoryLock;
  554. FspsUpd->FspsTestConfig.PchUnlockGpioPads = (UINT8)LockDownConfig->UnlockGpioPads;
  555. //
  556. // Update Dmi policies
  557. //
  558. FspsUpd->FspsConfig.PchPwrOptEnable = (UINT8)DmiConfig->PwrOptEnable;
  559. FspsUpd->FspsConfig.PchDmiAspmCtrl = (UINT8)DmiConfig->DmiAspmCtrl;
  560. //
  561. // Update Flash Protection policies
  562. //
  563. for (Index = 0; Index < PCH_FLASH_PROTECTED_RANGES; Index ++) {
  564. FspsUpd->FspsConfig.PchWriteProtectionEnable[Index] = (UINT8)FlashProtectionConfig->ProtectRange[Index].WriteProtectionEnable;
  565. FspsUpd->FspsConfig.PchReadProtectionEnable[Index] = (UINT8)FlashProtectionConfig->ProtectRange[Index].ReadProtectionEnable;
  566. FspsUpd->FspsConfig.PchProtectedRangeLimit[Index] = (UINT16)FlashProtectionConfig->ProtectRange[Index].ProtectedRangeLimit;
  567. FspsUpd->FspsConfig.PchProtectedRangeBase[Index] = (UINT16)FlashProtectionConfig->ProtectRange[Index].ProtectedRangeBase;
  568. }
  569. //
  570. // Update IO Apic policies
  571. //
  572. FspsUpd->FspsConfig.PchIoApicEntry24_119 = (UINT8)IoApicConfig->IoApicEntry24_119;
  573. FspsUpd->FspsConfig.Enable8254ClockGating = (UINT8)IoApicConfig->Enable8254ClockGating;
  574. FspsUpd->FspsConfig.Enable8254ClockGatingOnS3 = (UINT8)IoApicConfig->Enable8254ClockGatingOnS3;
  575. FspsUpd->FspsConfig.PchIoApicId = (UINT8)IoApicConfig->IoApicId;
  576. //
  577. // Update P2sb policies
  578. //
  579. FspsUpd->FspsTestConfig.PchSbAccessUnlock = (UINT8)P2sbConfig->SbAccessUnlock;
  580. //
  581. // Update Pch General policies
  582. //
  583. FspsUpd->FspsConfig.PchCrid = (UINT8)PchGeneralConfig->Crid;
  584. FspsUpd->FspsConfig.PchLegacyIoLowLatency = (UINT8)PchGeneralConfig->LegacyIoLowLatency;
  585. //
  586. // Update Pm policies
  587. //
  588. FspsUpd->FspsConfig.PchPmPmeB0S5Dis = (UINT8)PmConfig->WakeConfig.PmeB0S5Dis;
  589. FspsUpd->FspsConfig.PchPmWolEnableOverride = (UINT8)PmConfig->WakeConfig.WolEnableOverride;
  590. FspsUpd->FspsConfig.PchPmPcieWakeFromDeepSx = (UINT8)PmConfig->WakeConfig.PcieWakeFromDeepSx;
  591. FspsUpd->FspsConfig.PchPmWoWlanEnable = (UINT8)PmConfig->WakeConfig.WoWlanEnable;
  592. FspsUpd->FspsConfig.PchPmWoWlanDeepSxEnable = (UINT8)PmConfig->WakeConfig.WoWlanDeepSxEnable;
  593. FspsUpd->FspsConfig.PchPmLanWakeFromDeepSx = (UINT8)PmConfig->WakeConfig.LanWakeFromDeepSx;
  594. FspsUpd->FspsConfig.PchPmDeepSxPol = (UINT8)PmConfig->PchDeepSxPol;
  595. FspsUpd->FspsConfig.PchPmSlpS3MinAssert = (UINT8)PmConfig->PchSlpS3MinAssert;
  596. FspsUpd->FspsConfig.PchPmSlpS4MinAssert = (UINT8)PmConfig->PchSlpS4MinAssert;
  597. FspsUpd->FspsConfig.PchPmSlpSusMinAssert = (UINT8)PmConfig->PchSlpSusMinAssert;
  598. FspsUpd->FspsConfig.PchPmSlpAMinAssert = (UINT8)PmConfig->PchSlpAMinAssert;
  599. FspsUpd->FspsConfig.PchPmLpcClockRun = (UINT8)PmConfig->LpcClockRun;
  600. FspsUpd->FspsConfig.PchPmSlpStrchSusUp = (UINT8)PmConfig->SlpStrchSusUp;
  601. FspsUpd->FspsConfig.PchPmSlpLanLowDc = (UINT8)PmConfig->SlpLanLowDc;
  602. FspsUpd->FspsConfig.PchPmPwrBtnOverridePeriod = (UINT8)PmConfig->PwrBtnOverridePeriod;
  603. FspsUpd->FspsTestConfig.PchPmDisableEnergyReport = (UINT8)PmConfig->DisableEnergyReport;
  604. FspsUpd->FspsConfig.PchPmDisableDsxAcPresentPulldown = (UINT8)PmConfig->DisableDsxAcPresentPulldown;
  605. FspsUpd->FspsConfig.PchPmDisableNativePowerButton = (UINT8)PmConfig->DisableNativePowerButton;
  606. FspsUpd->FspsConfig.PmcPowerButtonDebounce = PmConfig->PowerButtonDebounce;
  607. FspsUpd->FspsConfig.PchPmSlpS0Enable = (UINT8)PmConfig->SlpS0Enable;
  608. FspsUpd->FspsConfig.PchPmMeWakeSts = (UINT8)PmConfig->MeWakeSts;
  609. FspsUpd->FspsConfig.PchPmWolOvrWkSts = (UINT8)PmConfig->WolOvrWkSts;
  610. FspsUpd->FspsConfig.EnableTcoTimer = (UINT8)PmConfig->EnableTcoTimer;
  611. FspsUpd->FspsConfig.PchPmVrAlert = (UINT8)PmConfig->VrAlert;
  612. FspsUpd->FspsConfig.PchPmPwrCycDur = (UINT8)PmConfig->PchPwrCycDur;
  613. FspsUpd->FspsConfig.PchPmPciePllSsc = (UINT8)PmConfig->PciePllSsc;
  614. FspsUpd->FspsConfig.PchPmSlpS0VmRuntimeControl = (UINT8)PmConfig->SlpS0VmRuntimeControl;
  615. FspsUpd->FspsConfig.PchPmSlpS0Vm070VSupport = (UINT8)PmConfig->SlpS0Vm070VSupport;
  616. FspsUpd->FspsConfig.PchPmSlpS0Vm075VSupport = (UINT8)PmConfig->SlpS0Vm075VSupport;
  617. FspsUpd->FspsConfig.SlpS0Override = (UINT8)PmConfig->SlpS0Override;
  618. FspsUpd->FspsConfig.SlpS0DisQForDebug = (UINT8)PmConfig->SlpS0DisQForDebug;
  619. FspsUpd->FspsConfig.PmcDbgMsgEn = (UINT8)PmConfig->PmcDbgMsgEn;
  620. FspsUpd->FspsConfig.PsOnEnable = (UINT8)PmConfig->PsOnEnable;
  621. FspsUpd->FspsConfig.PmcCpuC10GatePinEnable = (UINT8)PmConfig->CpuC10GatePinEnable;
  622. FspsUpd->FspsConfig.PmcModPhySusPgEnable = (UINT8)PmConfig->ModPhySusPgEnable;
  623. FspsUpd->FspsConfig.SlpS0WithGbeSupport = (UINT8)PmConfig->SlpS0WithGbeSupport;
  624. //
  625. // Update Pch Serial IRQ policies
  626. //
  627. FspsUpd->FspsConfig.PchSirqEnable = (UINT8)PchSerialIrqConfig->SirqEnable;
  628. FspsUpd->FspsConfig.PchSirqMode = (UINT8)PchSerialIrqConfig->SirqMode;
  629. FspsUpd->FspsConfig.PchStartFramePulse = (UINT8)PchSerialIrqConfig->StartFramePulse;
  630. //
  631. // Update Pch Thermal policies
  632. //
  633. FspsUpd->FspsConfig.PchTsmicLock = (UINT8)PchThermalConfig->TsmicLock;
  634. FspsUpd->FspsConfig.PchHotEnable = (UINT8)PchThermalConfig->PchHotEnable;
  635. FspsUpd->FspsConfig.PchT0Level = (UINT16)PchThermalConfig->TTLevels.T0Level;
  636. FspsUpd->FspsConfig.PchT1Level = (UINT16)PchThermalConfig->TTLevels.T1Level;
  637. FspsUpd->FspsConfig.PchT2Level = (UINT16)PchThermalConfig->TTLevels.T2Level;
  638. FspsUpd->FspsConfig.PchTTEnable = (UINT8)PchThermalConfig->TTLevels.TTEnable;
  639. FspsUpd->FspsConfig.PchTTState13Enable = (UINT8)PchThermalConfig->TTLevels.TTState13Enable;
  640. FspsUpd->FspsConfig.PchTTLock = (UINT8)PchThermalConfig->TTLevels.TTLock;
  641. FspsUpd->FspsConfig.TTSuggestedSetting = (UINT8)PchThermalConfig->TTLevels.SuggestedSetting;
  642. FspsUpd->FspsConfig.TTCrossThrottling = (UINT8)PchThermalConfig->TTLevels.PchCrossThrottling;
  643. FspsUpd->FspsConfig.PchDmiTsawEn = (UINT8)PchThermalConfig->DmiHaAWC.DmiTsawEn;
  644. FspsUpd->FspsConfig.DmiSuggestedSetting = (UINT8)PchThermalConfig->DmiHaAWC.SuggestedSetting;
  645. FspsUpd->FspsConfig.DmiTS0TW = (UINT8)PchThermalConfig->DmiHaAWC.TS0TW;
  646. FspsUpd->FspsConfig.DmiTS1TW = (UINT8)PchThermalConfig->DmiHaAWC.TS1TW;
  647. FspsUpd->FspsConfig.DmiTS2TW = (UINT8)PchThermalConfig->DmiHaAWC.TS2TW;
  648. FspsUpd->FspsConfig.DmiTS3TW = (UINT8)PchThermalConfig->DmiHaAWC.TS3TW;
  649. FspsUpd->FspsConfig.PchMemoryThrottlingEnable = (UINT8)PchThermalConfig->MemoryThrottling.Enable;
  650. FspsUpd->FspsConfig.PchMemoryPmsyncEnable[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].PmsyncEnable;
  651. FspsUpd->FspsConfig.PchMemoryPmsyncEnable[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].PmsyncEnable;
  652. FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].C0TransmitEnable;
  653. FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].C0TransmitEnable;
  654. FspsUpd->FspsConfig.PchMemoryPinSelection[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].PinSelection;
  655. FspsUpd->FspsConfig.PchMemoryPinSelection[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].PinSelection;
  656. FspsUpd->FspsConfig.PchTemperatureHotLevel = (UINT16)PchThermalConfig->PchHotLevel;
  657. //
  658. // Update Pch CNVi policies
  659. //
  660. FspsUpd->FspsConfig.PchCnviMode = (UINT8)CnviConfig->Mode;
  661. FspsUpd->FspsConfig.PchCnviMfUart1Type = (UINT8)CnviConfig->MfUart1Type;
  662. //
  663. // Update Pch HSIO policies
  664. //
  665. FspsUpd->FspsConfig.ChipsetInitBinPtr = HsioConfig->ChipsetInitBinPtr;
  666. FspsUpd->FspsConfig.ChipsetInitBinLen = HsioConfig->ChipsetInitBinLen;
  667. //
  668. // Update Pch Espi policies
  669. //
  670. FspsUpd->FspsConfig.PchEspiLgmrEnable = (UINT8)EspiConfig->LgmrEnable;
  671. return EFI_SUCCESS;
  672. }