SpiCommon.c 31 KB

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  1. /** @file
  2. PCH SPI Common Driver implements the SPI Host Controller Compatibility Interface.
  3. Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Uefi/UefiBaseType.h>
  7. #include <Library/IoLib.h>
  8. #include <Library/DebugLib.h>
  9. #include <Library/BaseMemoryLib.h>
  10. #include <IndustryStandard/Pci30.h>
  11. #include <PchAccess.h>
  12. #include <Protocol/Spi.h>
  13. #include <IncludePrivate/Library/PchSpiCommonLib.h>
  14. #include <Register/X58Ich10.h>
  15. /**
  16. Initialize an SPI protocol instance.
  17. @param[in] SpiInstance Pointer to SpiInstance to initialize
  18. @retval EFI_SUCCESS The protocol instance was properly initialized
  19. @exception EFI_UNSUPPORTED The PCH is not supported by this module
  20. **/
  21. EFI_STATUS
  22. SpiProtocolConstructor (
  23. IN SPI_INSTANCE *SpiInstance
  24. )
  25. {
  26. UINTN PchSpiBar0;
  27. //
  28. // Initialize the SPI protocol instance
  29. //
  30. SpiInstance->Signature = PCH_SPI_PRIVATE_DATA_SIGNATURE;
  31. SpiInstance->Handle = NULL;
  32. SpiInstance->SpiProtocol.Revision = PCH_SPI_SERVICES_REVISION;
  33. SpiInstance->SpiProtocol.FlashRead = SpiProtocolFlashRead;
  34. SpiInstance->SpiProtocol.FlashWrite = SpiProtocolFlashWrite;
  35. SpiInstance->SpiProtocol.FlashErase = SpiProtocolFlashErase;
  36. SpiInstance->SpiProtocol.FlashReadSfdp = SpiProtocolFlashReadSfdp;
  37. SpiInstance->SpiProtocol.FlashReadJedecId = SpiProtocolFlashReadJedecId;
  38. SpiInstance->SpiProtocol.FlashWriteStatus = SpiProtocolFlashWriteStatus;
  39. SpiInstance->SpiProtocol.FlashReadStatus = SpiProtocolFlashReadStatus;
  40. SpiInstance->SpiProtocol.GetRegionAddress = SpiProtocolGetRegionAddress;
  41. SpiInstance->SpiProtocol.ReadPchSoftStrap = SpiProtocolReadPchSoftStrap;
  42. SpiInstance->SpiProtocol.ReadCpuSoftStrap = SpiProtocolReadCpuSoftStrap;
  43. SpiInstance->PchAcpiBase = ICH10_PMBASE_IO;
  44. ASSERT (SpiInstance->PchAcpiBase != 0);
  45. PchSpiBar0 = RCRB + SPIBAR;
  46. if (PchSpiBar0 == 0) {
  47. DEBUG ((DEBUG_ERROR, "ERROR : PchSpiBar0 is invalid!\n"));
  48. ASSERT (FALSE);
  49. }
  50. if ((MmioRead32 (PchSpiBar0 + R_PCH_SPI_HSFSC) & B_PCH_SPI_HSFSC_FDV) == 0) {
  51. DEBUG ((DEBUG_ERROR, "ERROR : SPI Flash Signature invalid, cannot use the Hardware Sequencing registers!\n"));
  52. ASSERT (FALSE);
  53. }
  54. SpiInstance->ReadPermission = 0xffff;
  55. SpiInstance->WritePermission = 0xffff;
  56. DEBUG ((DEBUG_INFO, "Flash Region Permission: Read- 0x%04x; Write= 0x%04x\n",
  57. SpiInstance->ReadPermission,
  58. SpiInstance->WritePermission));
  59. //
  60. SpiInstance->TotalFlashSize = PcdGet32(PcdFlashAreaSize);
  61. DEBUG ((DEBUG_INFO, "Total Flash Size : %0x\n", SpiInstance->TotalFlashSize));
  62. return EFI_SUCCESS;
  63. }
  64. /**
  65. Delay for at least the request number of microseconds for Runtime usage.
  66. @param[in] ABase Acpi base address
  67. @param[in] Microseconds Number of microseconds to delay.
  68. **/
  69. VOID
  70. EFIAPI
  71. PchPmTimerStallRuntimeSafe (
  72. IN UINT16 ABase,
  73. IN UINTN Microseconds
  74. )
  75. {
  76. UINTN Ticks;
  77. UINTN Counts;
  78. UINTN CurrentTick;
  79. UINTN OriginalTick;
  80. UINTN RemainingTick;
  81. if (Microseconds == 0) {
  82. return;
  83. }
  84. OriginalTick = IoRead32 ((UINTN) (ABase + R_PCH_ACPI_PM1_TMR)) & B_PCH_ACPI_PM1_TMR_VAL;
  85. CurrentTick = OriginalTick;
  86. //
  87. // The timer frequency is 3.579545 MHz, so 1 ms corresponds 3.58 clocks
  88. //
  89. Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
  90. //
  91. // The loops needed by timer overflow
  92. //
  93. Counts = Ticks / V_PCH_ACPI_PM1_TMR_MAX_VAL;
  94. //
  95. // Remaining clocks within one loop
  96. //
  97. RemainingTick = Ticks % V_PCH_ACPI_PM1_TMR_MAX_VAL;
  98. //
  99. // not intend to use TMROF_STS bit of register PM1_STS, because this adds extra
  100. // one I/O operation, and maybe generate SMI
  101. //
  102. while ((Counts != 0) || (RemainingTick > CurrentTick)) {
  103. CurrentTick = IoRead32 ((UINTN) (ABase + R_PCH_ACPI_PM1_TMR)) & B_PCH_ACPI_PM1_TMR_VAL;
  104. //
  105. // Check if timer overflow
  106. //
  107. if ((CurrentTick < OriginalTick)) {
  108. if (Counts != 0) {
  109. Counts--;
  110. } else {
  111. //
  112. // If timer overflow and Counts equ to 0, that means we already stalled more than
  113. // RemainingTick, break the loop here
  114. //
  115. break;
  116. }
  117. }
  118. OriginalTick = CurrentTick;
  119. }
  120. }
  121. /**
  122. Read data from the flash part.
  123. @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
  124. @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
  125. @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
  126. @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
  127. @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received.
  128. It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
  129. @retval EFI_SUCCESS Command succeed.
  130. @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
  131. @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
  132. **/
  133. EFI_STATUS
  134. EFIAPI
  135. SpiProtocolFlashRead (
  136. IN EFI_SPI_PROTOCOL *This,
  137. IN FLASH_REGION_TYPE FlashRegionType,
  138. IN UINT32 Address,
  139. IN UINT32 ByteCount,
  140. OUT UINT8 *Buffer
  141. )
  142. {
  143. EFI_STATUS Status;
  144. //
  145. // Sends the command to the SPI interface to execute.
  146. //
  147. Status = SendSpiCmd (
  148. This,
  149. FlashRegionType,
  150. FlashCycleRead,
  151. Address,
  152. ByteCount,
  153. Buffer
  154. );
  155. return Status;
  156. }
  157. /**
  158. Write data to the flash part.
  159. @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
  160. @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
  161. @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
  162. @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
  163. @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
  164. @retval EFI_SUCCESS Command succeed.
  165. @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
  166. @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
  167. **/
  168. EFI_STATUS
  169. EFIAPI
  170. SpiProtocolFlashWrite (
  171. IN EFI_SPI_PROTOCOL *This,
  172. IN FLASH_REGION_TYPE FlashRegionType,
  173. IN UINT32 Address,
  174. IN UINT32 ByteCount,
  175. IN UINT8 *Buffer
  176. )
  177. {
  178. EFI_STATUS Status;
  179. //
  180. // Sends the command to the SPI interface to execute.
  181. //
  182. Status = SendSpiCmd (
  183. This,
  184. FlashRegionType,
  185. FlashCycleWrite,
  186. Address,
  187. ByteCount,
  188. Buffer
  189. );
  190. return Status;
  191. }
  192. /**
  193. Erase some area on the flash part.
  194. @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
  195. @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
  196. @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
  197. @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
  198. @retval EFI_SUCCESS Command succeed.
  199. @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
  200. @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
  201. **/
  202. EFI_STATUS
  203. EFIAPI
  204. SpiProtocolFlashErase (
  205. IN EFI_SPI_PROTOCOL *This,
  206. IN FLASH_REGION_TYPE FlashRegionType,
  207. IN UINT32 Address,
  208. IN UINT32 ByteCount
  209. )
  210. {
  211. EFI_STATUS Status;
  212. //
  213. // Sends the command to the SPI interface to execute.
  214. //
  215. Status = SendSpiCmd (
  216. This,
  217. FlashRegionType,
  218. FlashCycleErase,
  219. Address,
  220. ByteCount,
  221. NULL
  222. );
  223. return Status;
  224. }
  225. /**
  226. Read SFDP data from the flash part.
  227. @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
  228. @param[in] ComponentNumber The Componen Number for chip select
  229. @param[in] Address The starting byte address for SFDP data read.
  230. @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle
  231. @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
  232. It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read
  233. @retval EFI_SUCCESS Command succeed.
  234. @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
  235. @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
  236. **/
  237. EFI_STATUS
  238. EFIAPI
  239. SpiProtocolFlashReadSfdp (
  240. IN EFI_SPI_PROTOCOL *This,
  241. IN UINT8 ComponentNumber,
  242. IN UINT32 Address,
  243. IN UINT32 ByteCount,
  244. OUT UINT8 *SfdpData
  245. )
  246. {
  247. SPI_INSTANCE *SpiInstance;
  248. EFI_STATUS Status;
  249. UINT32 FlashAddress;
  250. SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
  251. Status = EFI_SUCCESS;
  252. if (ComponentNumber > SpiInstance->NumberOfComponents) {
  253. ASSERT (FALSE);
  254. return EFI_INVALID_PARAMETER;
  255. }
  256. FlashAddress = 0;
  257. if (ComponentNumber == FlashComponent1) {
  258. FlashAddress = SpiInstance->Component1StartAddr;
  259. }
  260. FlashAddress += Address;
  261. //
  262. // Sends the command to the SPI interface to execute.
  263. //
  264. Status = SendSpiCmd (
  265. This,
  266. FlashRegionAll,
  267. FlashCycleReadSfdp,
  268. FlashAddress,
  269. ByteCount,
  270. SfdpData
  271. );
  272. return Status;
  273. }
  274. /**
  275. Read Jedec Id from the flash part.
  276. @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
  277. @param[in] ComponentNumber The Componen Number for chip select
  278. @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
  279. @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
  280. It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
  281. @retval EFI_SUCCESS Command succeed.
  282. @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
  283. @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
  284. **/
  285. EFI_STATUS
  286. EFIAPI
  287. SpiProtocolFlashReadJedecId (
  288. IN EFI_SPI_PROTOCOL *This,
  289. IN UINT8 ComponentNumber,
  290. IN UINT32 ByteCount,
  291. OUT UINT8 *JedecId
  292. )
  293. {
  294. SPI_INSTANCE *SpiInstance;
  295. EFI_STATUS Status;
  296. UINT32 Address;
  297. SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
  298. Status = EFI_SUCCESS;
  299. if (ComponentNumber > SpiInstance->NumberOfComponents) {
  300. ASSERT (FALSE);
  301. return EFI_INVALID_PARAMETER;
  302. }
  303. Address = 0;
  304. if (ComponentNumber == FlashComponent1) {
  305. Address = SpiInstance->Component1StartAddr;
  306. }
  307. //
  308. // Sends the command to the SPI interface to execute.
  309. //
  310. Status = SendSpiCmd (
  311. This,
  312. FlashRegionAll,
  313. FlashCycleReadJedecId,
  314. Address,
  315. ByteCount,
  316. JedecId
  317. );
  318. return Status;
  319. }
  320. /**
  321. Write the status register in the flash part.
  322. @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
  323. @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
  324. @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
  325. @retval EFI_SUCCESS Command succeed.
  326. @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
  327. @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
  328. **/
  329. EFI_STATUS
  330. EFIAPI
  331. SpiProtocolFlashWriteStatus (
  332. IN EFI_SPI_PROTOCOL *This,
  333. IN UINT32 ByteCount,
  334. IN UINT8 *StatusValue
  335. )
  336. {
  337. EFI_STATUS Status;
  338. //
  339. // Sends the command to the SPI interface to execute.
  340. //
  341. Status = SendSpiCmd (
  342. This,
  343. FlashRegionAll,
  344. FlashCycleWriteStatus,
  345. 0,
  346. ByteCount,
  347. StatusValue
  348. );
  349. return Status;
  350. }
  351. /**
  352. Read status register in the flash part.
  353. @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
  354. @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
  355. @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
  356. @retval EFI_SUCCESS Command succeed.
  357. @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
  358. @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
  359. **/
  360. EFI_STATUS
  361. EFIAPI
  362. SpiProtocolFlashReadStatus (
  363. IN EFI_SPI_PROTOCOL *This,
  364. IN UINT32 ByteCount,
  365. OUT UINT8 *StatusValue
  366. )
  367. {
  368. EFI_STATUS Status;
  369. //
  370. // Sends the command to the SPI interface to execute.
  371. //
  372. Status = SendSpiCmd (
  373. This,
  374. FlashRegionAll,
  375. FlashCycleReadStatus,
  376. 0,
  377. ByteCount,
  378. StatusValue
  379. );
  380. return Status;
  381. }
  382. /**
  383. Get the SPI region base and size, based on the enum type
  384. @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
  385. @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
  386. @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
  387. @param[out] RegionSize The size for the Region 'n'
  388. @retval EFI_SUCCESS Read success
  389. @retval EFI_INVALID_PARAMETER Invalid region type given
  390. @retval EFI_DEVICE_ERROR The region is not used
  391. **/
  392. EFI_STATUS
  393. EFIAPI
  394. SpiProtocolGetRegionAddress (
  395. IN EFI_SPI_PROTOCOL *This,
  396. IN FLASH_REGION_TYPE FlashRegionType,
  397. OUT UINT32 *BaseAddress,
  398. OUT UINT32 *RegionSize
  399. )
  400. {
  401. SPI_INSTANCE *SpiInstance;
  402. UINTN PchSpiBar0;
  403. UINT32 ReadValue;
  404. SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
  405. if (FlashRegionType >= FlashRegionMax) {
  406. return EFI_INVALID_PARAMETER;
  407. }
  408. if (FlashRegionType == FlashRegionAll) {
  409. *BaseAddress = 0;
  410. *RegionSize = SpiInstance->TotalFlashSize;
  411. return EFI_SUCCESS;
  412. }
  413. PchSpiBar0 = AcquireSpiBar0 (SpiInstance);
  414. ReadValue = MmioRead32 (PchSpiBar0 + (R_PCH_SPI_FREG0_FLASHD + (S_PCH_SPI_FREGX * ((UINT32) FlashRegionType))));
  415. ReleaseSpiBar0 (SpiInstance);
  416. //
  417. // If the region is not used, the Region Base is 7FFFh and Region Limit is 0000h
  418. //
  419. if (ReadValue == B_PCH_SPI_FREGX_BASE_MASK) {
  420. return EFI_DEVICE_ERROR;
  421. }
  422. *BaseAddress = ((ReadValue & B_PCH_SPI_FREGX_BASE_MASK) >> N_PCH_SPI_FREGX_BASE) <<
  423. N_PCH_SPI_FREGX_BASE_REPR;
  424. //
  425. // Region limit address Bits[11:0] are assumed to be FFFh
  426. //
  427. *RegionSize = ((((ReadValue & B_PCH_SPI_FREGX_LIMIT_MASK) >> N_PCH_SPI_FREGX_LIMIT) + 1) <<
  428. N_PCH_SPI_FREGX_LIMIT_REPR) - *BaseAddress;
  429. return EFI_SUCCESS;
  430. }
  431. /**
  432. Read PCH Soft Strap Values
  433. @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
  434. @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
  435. @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
  436. @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value.
  437. If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
  438. It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
  439. @retval EFI_SUCCESS Command succeed.
  440. @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
  441. @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
  442. **/
  443. EFI_STATUS
  444. EFIAPI
  445. SpiProtocolReadPchSoftStrap (
  446. IN EFI_SPI_PROTOCOL *This,
  447. IN UINT32 SoftStrapAddr,
  448. IN UINT32 ByteCount,
  449. OUT VOID *SoftStrapValue
  450. )
  451. {
  452. SPI_INSTANCE *SpiInstance;
  453. UINT32 StrapFlashAddr;
  454. EFI_STATUS Status;
  455. SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
  456. if (ByteCount == 0) {
  457. *(UINT16 *) SoftStrapValue = SpiInstance->PchStrapSize;
  458. return EFI_SUCCESS;
  459. }
  460. if ((SoftStrapAddr + ByteCount) > (UINT32) SpiInstance->PchStrapSize) {
  461. ASSERT (FALSE);
  462. return EFI_INVALID_PARAMETER;
  463. }
  464. //
  465. // PCH Strap Flash Address = FPSBA + RamAddr
  466. //
  467. StrapFlashAddr = SpiInstance->PchStrapBaseAddr + SoftStrapAddr;
  468. //
  469. // Read PCH Soft straps from using execute command
  470. //
  471. Status = SendSpiCmd (
  472. This,
  473. FlashRegionDescriptor,
  474. FlashCycleRead,
  475. StrapFlashAddr,
  476. ByteCount,
  477. SoftStrapValue
  478. );
  479. return Status;
  480. }
  481. /**
  482. Read CPU Soft Strap Values
  483. @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
  484. @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
  485. @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle.
  486. @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value.
  487. If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
  488. It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
  489. @retval EFI_SUCCESS Command succeed.
  490. @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
  491. @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
  492. **/
  493. EFI_STATUS
  494. EFIAPI
  495. SpiProtocolReadCpuSoftStrap (
  496. IN EFI_SPI_PROTOCOL *This,
  497. IN UINT32 SoftStrapAddr,
  498. IN UINT32 ByteCount,
  499. OUT VOID *SoftStrapValue
  500. )
  501. {
  502. SPI_INSTANCE *SpiInstance;
  503. UINT32 StrapFlashAddr;
  504. EFI_STATUS Status;
  505. SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
  506. if (ByteCount == 0) {
  507. *(UINT16 *) SoftStrapValue = SpiInstance->CpuStrapSize;
  508. return EFI_SUCCESS;
  509. }
  510. if ((SoftStrapAddr + ByteCount) > (UINT32) SpiInstance->CpuStrapSize) {
  511. ASSERT (FALSE);
  512. return EFI_INVALID_PARAMETER;
  513. }
  514. //
  515. // CPU Strap Flash Address = FCPUSBA + RamAddr
  516. //
  517. StrapFlashAddr = SpiInstance->CpuStrapBaseAddr + SoftStrapAddr;
  518. //
  519. // Read Cpu Soft straps from using execute command
  520. //
  521. Status = SendSpiCmd (
  522. This,
  523. FlashRegionDescriptor,
  524. FlashCycleRead,
  525. StrapFlashAddr,
  526. ByteCount,
  527. SoftStrapValue
  528. );
  529. return Status;
  530. }
  531. /**
  532. This function sends the programmed SPI command to the slave device.
  533. @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
  534. @param[in] SpiRegionType The SPI Region type for flash cycle which is listed in the Descriptor
  535. @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (Hardware Sequencing Flash Control Register) register
  536. @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
  537. @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
  538. @param[in,out] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.
  539. @retval EFI_SUCCESS SPI command completes successfully.
  540. @retval EFI_DEVICE_ERROR Device error, the command aborts abnormally.
  541. @retval EFI_ACCESS_DENIED Some unrecognized command encountered in hardware sequencing mode
  542. @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
  543. **/
  544. EFI_STATUS
  545. SendSpiCmd (
  546. IN EFI_SPI_PROTOCOL *This,
  547. IN FLASH_REGION_TYPE FlashRegionType,
  548. IN FLASH_CYCLE_TYPE FlashCycleType,
  549. IN UINT32 Address,
  550. IN UINT32 ByteCount,
  551. IN OUT UINT8 *Buffer
  552. )
  553. {
  554. EFI_STATUS Status;
  555. UINT32 Index;
  556. SPI_INSTANCE *SpiInstance;
  557. UINTN SpiBaseAddress;
  558. UINTN PchSpiBar0;
  559. UINT32 HardwareSpiAddr;
  560. UINT32 FlashRegionSize;
  561. UINT32 SpiDataCount;
  562. UINT32 FlashCycle;
  563. UINT32 SmiEnSave;
  564. UINT16 ABase;
  565. Status = EFI_SUCCESS;
  566. SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
  567. SpiBaseAddress = SpiInstance->PchSpiBase;
  568. PchSpiBar0 = AcquireSpiBar0 (SpiInstance);
  569. SpiBaseAddress = SpiInstance->PchSpiBase;
  570. ABase = SpiInstance->PchAcpiBase;
  571. //
  572. // Disable SMIs to make sure normal mode flash access is not interrupted by an SMI
  573. // whose SMI handler accesses flash (e.g. for error logging)
  574. //
  575. // *** NOTE: if the SMI_LOCK bit is set (i.e., PMC PCI Offset A0h [4]='1'),
  576. // clearing B_GBL_SMI_EN will not have effect. In this situation, some other
  577. // synchronization methods must be applied here or in the consumer of the
  578. // SendSpiCmd. An example method is disabling the specific SMI sources
  579. // whose SMI handlers access flash before flash cycle and re-enabling the SMI
  580. // sources after the flash cycle .
  581. //
  582. SmiEnSave = IoRead32 ((UINTN) (ABase + R_PCH_SMI_EN));
  583. IoWrite32 ((UINTN) (ABase + R_PCH_SMI_EN), SmiEnSave & (UINT32) (~B_PCH_SMI_EN_GBL_SMI));
  584. //
  585. // If it's write cycle, disable Prefetching, Caching and disable BIOS Write Protect
  586. //
  587. if ((FlashCycleType == FlashCycleWrite) ||
  588. (FlashCycleType == FlashCycleErase)) {
  589. Status = DisableBiosWriteProtect ();
  590. if (EFI_ERROR (Status)) {
  591. goto SendSpiCmdEnd;
  592. }
  593. }
  594. //
  595. // Make sure it's safe to program the command.
  596. //
  597. if (!WaitForSpiCycleComplete (This, PchSpiBar0, FALSE)) {
  598. Status = EFI_DEVICE_ERROR;
  599. goto SendSpiCmdEnd;
  600. }
  601. Status = SpiProtocolGetRegionAddress (This, FlashRegionType, &HardwareSpiAddr, &FlashRegionSize);
  602. if (EFI_ERROR (Status)) {
  603. goto SendSpiCmdEnd;
  604. }
  605. HardwareSpiAddr += Address;
  606. if ((Address + ByteCount) > FlashRegionSize) {
  607. Status = EFI_INVALID_PARAMETER;
  608. goto SendSpiCmdEnd;
  609. }
  610. //
  611. // Check for PCH SPI hardware sequencing required commands
  612. //
  613. FlashCycle = 0;
  614. switch (FlashCycleType) {
  615. case FlashCycleRead:
  616. FlashCycle = (UINT32) (V_PCH_SPI_HSFSC_CYCLE_READ << N_PCH_SPI_HSFSC_CYCLE);
  617. break;
  618. case FlashCycleWrite:
  619. FlashCycle = (UINT32) (V_PCH_SPI_HSFSC_CYCLE_WRITE << N_PCH_SPI_HSFSC_CYCLE);
  620. break;
  621. case FlashCycleErase:
  622. if (((ByteCount % SIZE_4KB) != 0) ||
  623. ((HardwareSpiAddr % SIZE_4KB) != 0)) {
  624. ASSERT (FALSE);
  625. Status = EFI_INVALID_PARAMETER;
  626. goto SendSpiCmdEnd;
  627. }
  628. break;
  629. case FlashCycleReadSfdp:
  630. FlashCycle = (UINT32) (V_PCH_SPI_HSFSC_CYCLE_READ_SFDP << N_PCH_SPI_HSFSC_CYCLE);
  631. break;
  632. case FlashCycleReadJedecId:
  633. FlashCycle = (UINT32) (V_PCH_SPI_HSFSC_CYCLE_READ_JEDEC_ID << N_PCH_SPI_HSFSC_CYCLE);
  634. break;
  635. case FlashCycleWriteStatus:
  636. FlashCycle = (UINT32) (V_PCH_SPI_HSFSC_CYCLE_WRITE_STATUS << N_PCH_SPI_HSFSC_CYCLE);
  637. break;
  638. case FlashCycleReadStatus:
  639. FlashCycle = (UINT32) (V_PCH_SPI_HSFSC_CYCLE_READ_STATUS << N_PCH_SPI_HSFSC_CYCLE);
  640. break;
  641. default:
  642. //
  643. // Unrecognized Operation
  644. //
  645. ASSERT (FALSE);
  646. Status = EFI_INVALID_PARAMETER;
  647. goto SendSpiCmdEnd;
  648. break;
  649. }
  650. do {
  651. SpiDataCount = ByteCount;
  652. if ((FlashCycleType == FlashCycleRead) ||
  653. (FlashCycleType == FlashCycleWrite) ||
  654. (FlashCycleType == FlashCycleReadSfdp)) {
  655. //
  656. // Trim at 256 byte boundary per operation,
  657. // - PCH SPI controller requires trimming at 4KB boundary
  658. // - Some SPI chips require trimming at 256 byte boundary for write operation
  659. // - Trimming has limited performance impact as we can read / write atmost 64 byte
  660. // per operation
  661. //
  662. if (HardwareSpiAddr + ByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 - 1))) {
  663. SpiDataCount = (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32) (HardwareSpiAddr);
  664. }
  665. //
  666. // Calculate the number of bytes to shift in/out during the SPI data cycle.
  667. // Valid settings for the number of bytes duing each data portion of the
  668. // PCH SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48, 56, 64
  669. //
  670. if (SpiDataCount >= 64) {
  671. SpiDataCount = 64;
  672. } else if ((SpiDataCount &~0x07) != 0) {
  673. SpiDataCount = SpiDataCount &~0x07;
  674. }
  675. }
  676. if (FlashCycleType == FlashCycleErase) {
  677. if (((ByteCount / SIZE_64KB) != 0) &&
  678. ((ByteCount % SIZE_64KB) == 0) &&
  679. ((HardwareSpiAddr % SIZE_64KB) == 0)) {
  680. if (HardwareSpiAddr < SpiInstance->Component1StartAddr) {
  681. //
  682. // Check whether Component0 support 64k Erase
  683. //
  684. if ((SpiInstance->SfdpVscc0Value & B_PCH_SPI_SFDPX_VSCCX_EO_64K) != 0) {
  685. SpiDataCount = SIZE_64KB;
  686. } else {
  687. SpiDataCount = SIZE_4KB;
  688. }
  689. } else {
  690. //
  691. // Check whether Component1 support 64k Erase
  692. //
  693. if ((SpiInstance->SfdpVscc1Value & B_PCH_SPI_SFDPX_VSCCX_EO_64K) != 0) {
  694. SpiDataCount = SIZE_64KB;
  695. } else {
  696. SpiDataCount = SIZE_4KB;
  697. }
  698. }
  699. } else {
  700. SpiDataCount = SIZE_4KB;
  701. }
  702. if (SpiDataCount == SIZE_4KB) {
  703. FlashCycle = (UINT32) (V_PCH_SPI_HSFSC_CYCLE_4K_ERASE << N_PCH_SPI_HSFSC_CYCLE);
  704. } else {
  705. FlashCycle = (UINT32) (V_PCH_SPI_HSFSC_CYCLE_64K_ERASE << N_PCH_SPI_HSFSC_CYCLE);
  706. }
  707. }
  708. //
  709. // If it's write cycle, load data into the SPI data buffer.
  710. //
  711. if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleWriteStatus)) {
  712. if ((SpiDataCount & 0x07) != 0) {
  713. //
  714. // Use Byte write if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
  715. //
  716. for (Index = 0; Index < SpiDataCount; Index++) {
  717. MmioWrite8 (PchSpiBar0 + R_PCH_SPI_FDATA00 + Index, Buffer[Index]);
  718. }
  719. } else {
  720. //
  721. // Use Dword write if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
  722. //
  723. for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
  724. MmioWrite32 (PchSpiBar0 + R_PCH_SPI_FDATA00 + Index, *(UINT32 *) (Buffer + Index));
  725. }
  726. }
  727. }
  728. //
  729. // Set the Flash Address
  730. //
  731. MmioWrite32 (
  732. (PchSpiBar0 + R_PCH_SPI_FADDR),
  733. (UINT32) (HardwareSpiAddr & B_PCH_SPI_FADDR_MASK)
  734. );
  735. //
  736. // Set Data count, Flash cycle, and Set Go bit to start a cycle
  737. //
  738. MmioAndThenOr32 (
  739. PchSpiBar0 + R_PCH_SPI_HSFSC,
  740. (UINT32) (~(B_PCH_SPI_HSFSC_FDBC_MASK | B_PCH_SPI_HSFSC_CYCLE_MASK)),
  741. (UINT32) ((((SpiDataCount - 1) << N_PCH_SPI_HSFSC_FDBC) & B_PCH_SPI_HSFSC_FDBC_MASK) | FlashCycle | B_PCH_SPI_HSFSC_CYCLE_FGO)
  742. );
  743. //
  744. // end of command execution
  745. //
  746. // Wait the SPI cycle to complete.
  747. //
  748. if (!WaitForSpiCycleComplete (This, PchSpiBar0, TRUE)) {
  749. ASSERT (FALSE);
  750. Status = EFI_DEVICE_ERROR;
  751. goto SendSpiCmdEnd;
  752. }
  753. //
  754. // If it's read cycle, load data into the call's buffer.
  755. //
  756. if ((FlashCycleType == FlashCycleRead) ||
  757. (FlashCycleType == FlashCycleReadSfdp) ||
  758. (FlashCycleType == FlashCycleReadJedecId) ||
  759. (FlashCycleType == FlashCycleReadStatus)) {
  760. if ((SpiDataCount & 0x07) != 0) {
  761. //
  762. // Use Byte read if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
  763. //
  764. for (Index = 0; Index < SpiDataCount; Index++) {
  765. Buffer[Index] = MmioRead8 (PchSpiBar0 + R_PCH_SPI_FDATA00 + Index);
  766. }
  767. } else {
  768. //
  769. // Use Dword read if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
  770. //
  771. for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
  772. *(UINT32 *) (Buffer + Index) = MmioRead32 (PchSpiBar0 + R_PCH_SPI_FDATA00 + Index);
  773. }
  774. }
  775. }
  776. HardwareSpiAddr += SpiDataCount;
  777. Buffer += SpiDataCount;
  778. ByteCount -= SpiDataCount;
  779. } while (ByteCount > 0);
  780. SendSpiCmdEnd:
  781. //
  782. // Restore the settings for SPI Prefetching and Caching and enable BIOS Write Protect
  783. //
  784. if ((FlashCycleType == FlashCycleWrite) ||
  785. (FlashCycleType == FlashCycleErase)) {
  786. EnableBiosWriteProtect ();
  787. }
  788. //
  789. // Restore SMIs.
  790. //
  791. IoWrite32 ((UINTN) (ABase + R_PCH_SMI_EN), SmiEnSave);
  792. ReleaseSpiBar0 (SpiInstance);
  793. return Status;
  794. }
  795. /**
  796. Wait execution cycle to complete on the SPI interface.
  797. @param[in] This The SPI protocol instance
  798. @param[in] PchSpiBar0 Spi MMIO base address
  799. @param[in] ErrorCheck TRUE if the SpiCycle needs to do the error check
  800. @retval TRUE SPI cycle completed on the interface.
  801. @retval FALSE Time out while waiting the SPI cycle to complete.
  802. It's not safe to program the next command on the SPI interface.
  803. **/
  804. BOOLEAN
  805. WaitForSpiCycleComplete (
  806. IN EFI_SPI_PROTOCOL *This,
  807. IN UINTN PchSpiBar0,
  808. IN BOOLEAN ErrorCheck
  809. )
  810. {
  811. UINT64 WaitTicks;
  812. UINT64 WaitCount;
  813. UINT32 Data32;
  814. SPI_INSTANCE *SpiInstance;
  815. SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
  816. //
  817. // Convert the wait period allowed into to tick count
  818. //
  819. WaitCount = SPI_WAIT_TIME / SPI_WAIT_PERIOD;
  820. //
  821. // Wait for the SPI cycle to complete.
  822. //
  823. for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {
  824. Data32 = MmioRead32 (PchSpiBar0 + R_PCH_SPI_HSFSC);
  825. if ((Data32 & B_PCH_SPI_HSFSC_SCIP) == 0) {
  826. MmioWrite32 (PchSpiBar0 + R_PCH_SPI_HSFSC, B_PCH_SPI_HSFSC_FCERR | B_PCH_SPI_HSFSC_FDONE);
  827. if (((Data32 & B_PCH_SPI_HSFSC_FCERR) != 0) && (ErrorCheck == TRUE)) {
  828. return FALSE;
  829. } else {
  830. return TRUE;
  831. }
  832. }
  833. PchPmTimerStallRuntimeSafe (SpiInstance->PchAcpiBase, SPI_WAIT_PERIOD);
  834. }
  835. return FALSE;
  836. }