X58Ich10.h 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114
  1. /** @file
  2. Various register numbers and value bits based on the following publications:
  3. - Intel(R) datasheet 319973-003
  4. - Intel(R) datasheet 319974-017US
  5. Copyright (C) 2015, Red Hat, Inc.
  6. Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
  7. Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
  8. SPDX-License-Identifier: BSD-2-Clause-Patent
  9. **/
  10. #ifndef __X58_ICH10_H__
  11. #define __X58_ICH10_H__
  12. #include <Library/PciLib.h>
  13. #include <IndustryStandard/Pci22.h>
  14. //
  15. // Simics Host Bridge DID Address
  16. //
  17. #define SIMICS_HOSTBRIDGE_DID \
  18. PCI_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_OFFSET)
  19. //
  20. // Host Bridge Device ID (DID) value for ICH10
  21. //
  22. #define INTEL_ICH10_DEVICE_ID 0x3400
  23. //
  24. // B/D/F/Type: 0/0/0/PCI
  25. //
  26. #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
  27. #define DRAMC_REGISTER_X58(Offset) PCI_LIB_ADDRESS (0, 20, 0, (Offset))
  28. #define MCH_GGC 0x52
  29. #define MCH_GGC_IVD BIT1
  30. #define MCH_PCIEXBAR_LOW 0x10C
  31. #define MCH_PCIEXBAR_LID 0x10E
  32. #define MCH_PCIEXBAR_SHIFT 16
  33. #define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF
  34. #define MCH_PCIEXBAR_BUS_FF 0
  35. #define MCH_PCIEXBAR_EN BIT0
  36. #define MCH_PCIEXBAR_HIGH 0x64
  37. #define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0
  38. #define MCH_SMRAM 0x9D
  39. #define MCH_SMRAM_D_LCK BIT4
  40. #define MCH_SMRAM_G_SMRAME BIT3
  41. #define MCH_ESMRAMC 0x9E
  42. #define MCH_ESMRAMC_H_SMRAME BIT7
  43. #define MCH_ESMRAMC_E_SMERR BIT6
  44. #define MCH_ESMRAMC_SM_CACHE BIT5
  45. #define MCH_ESMRAMC_SM_L1 BIT4
  46. #define MCH_ESMRAMC_SM_L2 BIT3
  47. #define MCH_ESMRAMC_TSEG_8MB BIT3
  48. #define MCH_ESMRAMC_TSEG_2MB BIT2
  49. #define MCH_ESMRAMC_TSEG_1MB BIT1
  50. #define MCH_ESMRAMC_TSEG_MASK (BIT3 | BIT2 | BIT1)
  51. #define MCH_ESMRAMC_T_EN BIT0
  52. #define MCH_GBSM 0xA4
  53. #define MCH_GBSM_MB_SHIFT 20
  54. #define MCH_BGSM 0xA8
  55. #define MCH_BGSM_MB_SHIFT 20
  56. #define MCH_TSEGMB 0xA8
  57. #define MCH_TSEGMB_MB_SHIFT 20
  58. #define MCH_TOLUD 0xD0
  59. //
  60. // B/D/F/Type: 0/0x1f/0/PCI
  61. //
  62. #define POWER_MGMT_REGISTER_ICH10(Offset) \
  63. PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))
  64. #define ICH10_PMBASE 0x40
  65. #define ICH10_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
  66. BIT10 | BIT9 | BIT8 | BIT7)
  67. #define ICH10_ACPI_CNTL 0x44
  68. #define ICH10_ACPI_CNTL_ACPI_EN BIT7
  69. #define ICH10_GEN_PMCON_1 0xA0
  70. #define ICH10_GEN_PMCON_1_SMI_LOCK BIT4
  71. #define ICH10_RCBA 0xF0
  72. #define ICH10_RCBA_EN BIT0
  73. #define ICH10_PMBASE_IO 0x400
  74. //
  75. // IO ports
  76. //
  77. #define ICH10_APM_CNT 0xB2
  78. #define ICH10_APM_STS 0xB3
  79. //
  80. // IO ports relative to PMBASE
  81. //
  82. #define ICH10_PMBASE_OFS_SMI_EN 0x30
  83. #define ICH10_SMI_EN_APMC_EN BIT5
  84. #define ICH10_SMI_EN_GBL_SMI_EN BIT0
  85. #define ICH10_SMI_EN_EOS BIT1 // End of SMI
  86. #define ICH10_PMBASE_OFS_SMI_STS 0x34
  87. #define ICH10_SMI_STS_APM BIT5 // APM Status
  88. #define ICH10_ROOT_COMPLEX_BASE 0xFED1C000
  89. #endif