PchRegsSpi.h 23 KB

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  1. /** @file
  2. Register names for PCH SPI device.
  3. Conventions:
  4. - Prefixes:
  5. Definitions beginning with "R_" are registers
  6. Definitions beginning with "B_" are bits within registers
  7. Definitions beginning with "V_" are meaningful values within the bits
  8. Definitions beginning with "S_" are register sizes
  9. Definitions beginning with "N_" are the bit position
  10. - In general, PCH registers are denoted by "_PCH_" in register names
  11. - Registers / bits that are different between PCH generations are denoted by
  12. "_PCH_[generation_name]_" in register/bit names.
  13. - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
  14. Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
  15. e.g., "_PCH_H_", "_PCH_LP_"
  16. Registers / bits names without _H_ or _LP_ apply for both H and LP.
  17. - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
  18. at the end of the register/bit names
  19. - Registers / bits of new devices introduced in a PCH generation will be just named
  20. as "_PCH_" without [generation_name] inserted.
  21. Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
  22. SPDX-License-Identifier: BSD-2-Clause-Patent
  23. **/
  24. #ifndef _PCH_REGS_SPI_H_
  25. #define _PCH_REGS_SPI_H_
  26. //
  27. // SPI Registers (D31:F5)
  28. //
  29. #define PCI_DEVICE_NUMBER_PCH_SPI 31
  30. #define PCI_FUNCTION_NUMBER_PCH_SPI 5
  31. #define R_PCH_SPI_BAR0 0x10
  32. #define B_PCH_SPI_BAR0_MASK 0x0FFF
  33. #define R_PCH_SPI_BDE 0xD8
  34. #define B_PCH_SPI_BDE_F8 0x8000
  35. #define B_PCH_SPI_BDE_F0 0x4000
  36. #define B_PCH_SPI_BDE_E8 0x2000
  37. #define B_PCH_SPI_BDE_E0 0x1000
  38. #define B_PCH_SPI_BDE_D8 0x0800
  39. #define B_PCH_SPI_BDE_D0 0x0400
  40. #define B_PCH_SPI_BDE_C8 0x0200
  41. #define B_PCH_SPI_BDE_C0 0x0100
  42. #define B_PCH_SPI_BDE_LEG_F 0x0080
  43. #define B_PCH_SPI_BDE_LEG_E 0x0040
  44. #define B_PCH_SPI_BDE_70 0x0008
  45. #define B_PCH_SPI_BDE_60 0x0004
  46. #define B_PCH_SPI_BDE_50 0x0002
  47. #define B_PCH_SPI_BDE_40 0x0001
  48. #define R_PCH_SPI_BC 0xDC
  49. #define S_PCH_SPI_BC 4
  50. #define N_PCH_SPI_BC_ASE_BWP 11
  51. #define B_PCH_SPI_BC_ASE_BWP BIT11
  52. #define N_PCH_SPI_BC_ASYNC_SS 10
  53. #define B_PCH_SPI_BC_ASYNC_SS BIT10
  54. #define B_PCH_SPI_BC_OSFH BIT9 ///< OS Function Hide
  55. #define N_PCH_SPI_BC_SYNC_SS 8
  56. #define B_PCH_SPI_BC_SYNC_SS BIT8
  57. #define B_PCH_SPI_BC_BILD BIT7
  58. #define B_PCH_SPI_BC_BBS BIT6 ///< Boot BIOS strap
  59. #define N_PCH_SPI_BC_BBS 6
  60. #define V_PCH_SPI_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI
  61. #define V_PCH_SPI_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC
  62. #define B_PCH_SPI_BC_EISS BIT5 ///< Enable InSMM.STS
  63. #define B_PCH_SPI_BC_TSS BIT4
  64. #define B_PCH_SPI_BC_SRC (BIT3 | BIT2)
  65. #define N_PCH_SPI_BC_SRC 2
  66. #define V_PCH_SPI_BC_SRC_PREF_EN_CACHE_EN 0x02 ///< Prefetching and Caching enabled
  67. #define V_PCH_SPI_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefetching and no caching
  68. #define V_PCH_SPI_BC_SRC_PREF_DIS_CACHE_EN 0x00 ///< No prefetching, but caching enabled
  69. #define B_PCH_SPI_BC_LE BIT1 ///< Lock Enable
  70. #define N_PCH_SPI_BC_BLE 1
  71. #define B_PCH_SPI_BC_WPD BIT0 ///< Write Protect Disable
  72. //
  73. // BIOS Flash Program Registers (based on SPI_BAR0)
  74. //
  75. #define R_PCH_SPI_BFPR 0x00 ///< BIOS Flash Primary Region Register(32bits), which is RO and contains the same value from FREG1
  76. #define B_PCH_SPI_BFPR_PRL 0x7FFF0000 ///< BIOS Flash Primary Region Limit mask
  77. #define N_PCH_SPI_BFPR_PRL 16 ///< BIOS Flash Primary Region Limit bit position
  78. #define B_PCH_SPI_BFPR_PRB 0x00007FFF ///< BIOS Flash Primary Region Base mask
  79. #define N_PCH_SPI_BFPR_PRB 0 ///< BIOS Flash Primary Region Base bit position
  80. #define R_PCH_SPI_HSFSC 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits)
  81. #define B_PCH_SPI_HSFSC_FSMIE BIT31 ///< Flash SPI SMI# Enable
  82. #define B_PCH_SPI_HSFSC_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
  83. #define N_PCH_SPI_HSFSC_FDBC 24
  84. #define B_PCH_SPI_HSFSC_CYCLE_MASK 0x001E0000 ///< Flash Cycle.
  85. #define N_PCH_SPI_HSFSC_CYCLE 17
  86. #define V_PCH_SPI_HSFSC_CYCLE_READ 0 ///< Flash Cycle Read
  87. #define V_PCH_SPI_HSFSC_CYCLE_WRITE 2 ///< Flash Cycle Write
  88. #define V_PCH_SPI_HSFSC_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase
  89. #define V_PCH_SPI_HSFSC_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase
  90. #define V_PCH_SPI_HSFSC_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP
  91. #define V_PCH_SPI_HSFSC_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID
  92. #define V_PCH_SPI_HSFSC_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status
  93. #define V_PCH_SPI_HSFSC_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status
  94. #define B_PCH_SPI_HSFSC_CYCLE_FGO BIT16 ///< Flash Cycle Go.
  95. #define B_PCH_SPI_HSFSC_FLOCKDN BIT15 ///< Flash Configuration Lock-Down
  96. #define B_PCH_SPI_HSFSC_FDV BIT14 ///< Flash Descriptor Valid, once valid software can use hareware sequencing regs
  97. #define B_PCH_SPI_HSFSC_FDOPSS BIT13 ///< Flash Descriptor Override Pin-Strap Status
  98. #define B_PCH_SPI_HSFSC_PRR34_LOCKDN BIT12 ///< PRR3 PRR4 Lock-Down
  99. #define B_PCH_SPI_HSFSC_SAF_CE BIT8 ///< SAF ctype error
  100. #define B_PCH_SPI_HSFSC_SAF_MODE_ACTIVE BIT7 ///< Indicates flash is attached either directly to the PCH via the SPI bus or EC/BMC
  101. #define B_PCH_SPI_HSFSC_SAF_LE BIT6 ///< SAF link error
  102. #define B_PCH_SPI_HSFSC_SCIP BIT5 ///< SPI cycle in progress
  103. #define B_PCH_SPI_HSFSC_SAF_DLE BIT4 ///< SAF Data length error
  104. #define B_PCH_SPI_HSFSC_SAF_ERROR BIT3 ///< SAF Error
  105. #define B_PCH_SPI_HSFSC_AEL BIT2 ///< Access Error Log
  106. #define B_PCH_SPI_HSFSC_FCERR BIT1 ///< Flash Cycle Error
  107. #define B_PCH_SPI_HSFSC_FDONE BIT0 ///< Flash Cycle Done
  108. #define R_PCH_SPI_FADDR 0x08 ///< SPI Flash Address
  109. #define B_PCH_SPI_FADDR_MASK 0x01FFFFFF ///< SPI Flash Address Mask (0~24bit)
  110. #define R_PCH_SPI_DLOCK 0x0C ///< Discrete Lock Bits
  111. #define B_PCH_SPI_DLOCK_PR0LOCKDN BIT8 ///< PR0LOCKDN
  112. #define R_PCH_SPI_FDATA00 0x10 ///< SPI Data 00 (32 bits)
  113. #define R_PCH_SPI_FDATA01 0x14 ///< SPI Data 01
  114. #define R_PCH_SPI_FDATA02 0x18 ///< SPI Data 02
  115. #define R_PCH_SPI_FDATA03 0x1C ///< SPI Data 03
  116. #define R_PCH_SPI_FDATA04 0x20 ///< SPI Data 04
  117. #define R_PCH_SPI_FDATA05 0x24 ///< SPI Data 05
  118. #define R_PCH_SPI_FDATA06 0x28 ///< SPI Data 06
  119. #define R_PCH_SPI_FDATA07 0x2C ///< SPI Data 07
  120. #define R_PCH_SPI_FDATA08 0x30 ///< SPI Data 08
  121. #define R_PCH_SPI_FDATA09 0x34 ///< SPI Data 09
  122. #define R_PCH_SPI_FDATA10 0x38 ///< SPI Data 10
  123. #define R_PCH_SPI_FDATA11 0x3C ///< SPI Data 11
  124. #define R_PCH_SPI_FDATA12 0x40 ///< SPI Data 12
  125. #define R_PCH_SPI_FDATA13 0x44 ///< SPI Data 13
  126. #define R_PCH_SPI_FDATA14 0x48 ///< SPI Data 14
  127. #define R_PCH_SPI_FDATA15 0x4C ///< SPI Data 15
  128. #define R_PCH_SPI_FRAP 0x50 ///< Flash Region Access Permisions Register
  129. #define B_PCH_SPI_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
  130. #define N_PCH_SPI_FRAP_BRWA 8 ///< BIOS Region Write Access bit position
  131. #define B_PCH_SPI_FRAP_BRRA_MASK 0x000000FF ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
  132. #define B_PCH_SPI_FRAP_BMRAG_MASK 0x00FF0000 ///< BIOS Master Read Access Grant
  133. #define B_PCH_SPI_FRAP_BMWAG_MASK 0xFF000000 ///< BIOS Master Write Access Grant
  134. #define R_PCH_SPI_FREG0_FLASHD 0x54 ///< Flash Region 0(Flash Descriptor)(32bits)
  135. #define R_PCH_SPI_FREG1_BIOS 0x58 ///< Flash Region 1(BIOS)(32bits)
  136. #define R_PCH_SPI_FREG2_ME 0x5C ///< Flash Region 2(ME)(32bits)
  137. #define R_PCH_SPI_FREG3_GBE 0x60 ///< Flash Region 3(GbE)(32bits)
  138. #define R_PCH_SPI_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4(Platform Data)(32bits)
  139. #define R_PCH_SPI_FREG5_DER 0x68 ///< Flash Region 5(Device Expansion Region)(32bits)
  140. #define S_PCH_SPI_FREGX 4 ///< Size of Flash Region register
  141. #define B_PCH_SPI_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh
  142. #define N_PCH_SPI_FREGX_LIMIT 16 ///< Region limit bit position
  143. #define N_PCH_SPI_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position
  144. #define B_PCH_SPI_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12]
  145. #define N_PCH_SPI_FREGX_BASE 0 ///< Region base bit position
  146. #define N_PCH_SPI_FREGX_BASE_REPR 12 ///< Region base bit represents position
  147. #define R_PCH_SPI_PR0 0x84 ///< Protected Region 0 Register
  148. #define R_PCH_SPI_PR1 0x88 ///< Protected Region 1 Register
  149. #define R_PCH_SPI_PR2 0x8C ///< Protected Region 2 Register
  150. #define R_PCH_SPI_PR3 0x90 ///< Protected Region 3 Register
  151. #define R_PCH_SPI_PR4 0x94 ///< Protected Region 4 Register
  152. #define S_PCH_SPI_PRX 4 ///< Protected Region X Register size
  153. #define B_PCH_SPI_PRX_WPE BIT31 ///< Write Protection Enable
  154. #define B_PCH_SPI_PRX_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask, [30:16] here represents upper limit of address [26:12]
  155. #define N_PCH_SPI_PRX_PRL 16 ///< Protected Range Limit bit position
  156. #define B_PCH_SPI_PRX_RPE BIT15 ///< Read Protection Enable
  157. #define B_PCH_SPI_PRX_PRB_MASK 0x00007FFF ///< Protected Range Base Mask, [14:0] here represents base limit of address [26:12]
  158. #define N_PCH_SPI_PRX_PRB 0 ///< Protected Range Base bit position
  159. #define R_PCH_SPI_SFRAP 0xB0 ///< Secondary Flash Regions Access Permisions Register
  160. #define R_PCH_SPI_FDOC 0xB4 ///< Flash Descriptor Observability Control Register(32 bits)
  161. #define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descritor Section Select
  162. #define V_PCH_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map
  163. #define V_PCH_SPI_FDOC_FDSS_COMP 0x1000 ///< Component
  164. #define V_PCH_SPI_FDOC_FDSS_REGN 0x2000 ///< Region
  165. #define V_PCH_SPI_FDOC_FDSS_MSTR 0x3000 ///< Master
  166. #define V_PCH_SPI_FDOC_FDSS_PCHS 0x4000 ///< PCH soft straps
  167. #define V_PCH_SPI_FDOC_FDSS_SFDP 0x5000 ///< SFDP Parameter Table
  168. #define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index
  169. #define R_PCH_SPI_FDOD 0xB8 ///< Flash Descriptor Observability Data Register(32 bits)
  170. #define R_PCH_SPI_SFDP0_VSCC0 0xC4 ///< Vendor Specific Component Capabilities Register(32 bits)
  171. #define B_PCH_SPI_SFDPX_VSCCX_CPPTV BIT31 ///< Component Property Parameter Table Valid
  172. #define B_PCH_SPI_SFDP0_VSCC0_VCL BIT30 ///< Vendor Component Lock
  173. #define B_PCH_SPI_SFDPX_VSCCX_EO_64K BIT29 ///< 64k Erase valid (EO_64k_valid)
  174. #define B_PCH_SPI_SFDPX_VSCCX_EO_4K BIT28 ///< 4k Erase valid (EO_4k_valid)
  175. #define B_PCH_SPI_SFDPX_VSCCX_RPMC BIT27 ///< RPMC Supported
  176. #define B_PCH_SPI_SFDPX_VSCCX_DPD BIT26 ///< Deep Powerdown Supported
  177. #define B_PCH_SPI_SFDPX_VSCCX_SUSRES BIT25 ///< Suspend/Resume Supported
  178. #define B_PCH_SPI_SFDPX_VSCCX_SOFTRES BIT24 ///< Soft Reset Supported
  179. #define B_PCH_SPI_SFDPX_VSCCX_64k_EO_MASK 0x00FF0000 ///< 64k Erase Opcode (EO_64k)
  180. #define B_PCH_SPI_SFDPX_VSCCX_4k_EO_MASK 0x0000FF00 ///< 4k Erase Opcode (EO_4k)
  181. #define B_PCH_SPI_SFDPX_VSCCX_QER (BIT7 | BIT6 | BIT5) ///< Quad Enable Requirements
  182. #define B_PCH_SPI_SFDPX_VSCCX_WEWS BIT4 ///< Write Enable on Write Status
  183. #define B_PCH_SPI_SFDPX_VSCCX_WSR BIT3 ///< Write Status Required
  184. #define B_PCH_SPI_SFDPX_VSCCX_WG_64B BIT2 ///< Write Granularity, 0: 1 Byte; 1: 64 Bytes
  185. #define R_PCH_SPI_SFDP1_VSCC1 0xC8 ///< Vendor Specific Component Capabilities Register(32 bits)
  186. #define R_PCH_SPI_PINTX 0xCC ///< Parameter Table Index
  187. #define N_PCH_SPI_PINTX_SPT 14
  188. #define V_PCH_SPI_PINTX_SPT_CPT0 0x0 ///< Component 0 Property Parameter Table
  189. #define V_PCH_SPI_PINTX_SPT_CPT1 0x1 ///< Component 1 Property Parameter Table
  190. #define N_PCH_SPI_PINTX_HORD 12
  191. #define V_PCH_SPI_PINTX_HORD_SFDP 0x0 ///< SFDP Header
  192. #define V_PCH_SPI_PINTX_HORD_PT 0x1 ///< Parameter Table Header
  193. #define V_PCH_SPI_PINTX_HORD_DATA 0x2 ///< Data
  194. #define R_PCH_SPI_PTDATA 0xD0 ///< Parameter Table Data
  195. #define R_PCH_SPI_SBRS 0xD4 ///< SPI Bus Requester Status
  196. #define R_PCH_SPI_SSML 0xF0 ///< Set Strap Msg Lock
  197. #define B_PCH_SPI_SSML_SSL BIT0 ///< Set_Strap Lock
  198. #define R_PCH_SPI_SSMC 0xF4 ///< Set Strap Msg Control
  199. #define B_PCH_SPI_SSMC_SSMS BIT0 ///< Set_Strap Mux Select
  200. #define R_PCH_SPI_SSMD 0xF8 ///< Set Strap Msg Data
  201. //
  202. // @todo Follow up with EDS owner if it should be 3FFF or FFFF.
  203. //
  204. #define B_PCH_SPI_SRD_SSD 0x0000FFFF ///< Set_Strap Data
  205. //
  206. // Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
  207. //
  208. #define R_PCH_SPI_FDBAR_FLVALSIG 0x00 ///< Flash Valid Signature
  209. #define V_PCH_SPI_FDBAR_FLVALSIG 0x0FF0A55A
  210. #define R_PCH_SPI_FDBAR_FLASH_MAP0 0x04
  211. #define B_PCH_SPI_FDBAR_FCBA 0x000000FF ///< Flash Component Base Address
  212. #define B_PCH_SPI_FDBAR_NC 0x00000300 ///< Number Of Components
  213. #define N_PCH_SPI_FDBAR_NC 8 ///< Number Of Components
  214. #define V_PCH_SPI_FDBAR_NC_1 0x00000000
  215. #define V_PCH_SPI_FDBAR_NC_2 0x00000100
  216. #define B_PCH_SPI_FDBAR_FRBA 0x00FF0000 ///< Flash Region Base Address
  217. #define B_PCH_SPI_FDBAR_NR 0x07000000 ///< Number Of Regions
  218. #define R_PCH_SPI_FDBAR_FLASH_MAP1 0x08
  219. #define B_PCH_SPI_FDBAR_FMBA 0x000000FF ///< Flash Master Base Address
  220. #define B_PCH_SPI_FDBAR_NM 0x00000700 ///< Number Of Masters
  221. #define B_PCH_SPI_FDBAR_FPSBA 0x00FF0000 ///< PCH Strap Base Address, [23:16] represents [11:4]
  222. #define N_PCH_SPI_FDBAR_FPSBA 16 ///< PCH Strap base Address bit position
  223. #define N_PCH_SPI_FDBAR_FPSBA_REPR 4 ///< PCH Strap base Address bit represents position
  224. #define B_PCH_SPI_FDBAR_PCHSL 0xFF000000 ///< PCH Strap Length, [31:24] represents number of Dwords
  225. #define N_PCH_SPI_FDBAR_PCHSL 24 ///< PCH Strap Length bit position
  226. #define R_PCH_SPI_FDBAR_FLASH_MAP2 0x0C
  227. #define B_PCH_SPI_FDBAR_FCPUSBA 0x000000FF ///< CPU Strap Base Address, [7:0] represents [11:4]
  228. #define N_PCH_SPI_FDBAR_FCPUSBA 0 ///< CPU Strap Base Address bit position
  229. #define N_PCH_SPI_FDBAR_FCPUSBA_REPR 4 ///< CPU Strap Base Address bit represents position
  230. #define B_PCH_SPI_FDBAR_CPUSL 0x0000FF00 ///< CPU Strap Length, [15:8] represents number of Dwords
  231. #define N_PCH_SPI_FDBAR_CPUSL 8 ///< CPU Strap Length bit position
  232. //
  233. // Flash Component Base Address (FCBA) from Flash Region 0
  234. //
  235. #define R_PCH_SPI_FCBA_FLCOMP 0x00 ///< Flash Components Register
  236. #define B_PCH_SPI_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27) ///< Read ID and Read Status Clock Frequency
  237. #define B_PCH_SPI_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24) ///< Write and Erase Clock Frequency
  238. #define B_PCH_SPI_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21) ///< Fast Read Clock Frequency
  239. #define B_PCH_SPI_FLCOMP_FR_SUP BIT20 ///< Fast Read Support.
  240. #define B_PCH_SPI_FLCOMP_RC_FREQ (BIT19 | BIT18 | BIT17) ///< Read Clock Frequency.
  241. #define V_PCH_SPI_FLCOMP_FREQ_48MHZ 0x02
  242. #define V_PCH_SPI_FLCOMP_FREQ_30MHZ 0x04
  243. #define V_PCH_SPI_FLCOMP_FREQ_17MHZ 0x06
  244. #define B_PCH_SPI_FLCOMP_COMP1_MASK 0xF0 ///< Flash Component 1 Size MASK
  245. #define N_PCH_SPI_FLCOMP_COMP1 4 ///< Flash Component 1 Size bit position
  246. #define B_PCH_SPI_FLCOMP_COMP0_MASK 0x0F ///< Flash Component 0 Size MASK
  247. #define V_PCH_SPI_FLCOMP_COMP_512KB 0x80000
  248. //
  249. // Descriptor Upper Map Section from Flash Region 0
  250. //
  251. #define R_PCH_SPI_FLASH_UMAP1 0xEFC ///< Flash Upper Map 1
  252. #define B_PCH_SPI_FLASH_UMAP1_VTBA 0x000000FF ///< VSCC Table Base Address
  253. #define B_PCH_SPI_FLASH_UMAP1_VTL 0x0000FF00 ///< VSCC Table Length
  254. #define R_PCH_SPI_VTBA_JID0 0x00 ///< JEDEC-ID 0 Register
  255. #define S_PCH_SPI_VTBA_JID0 0x04
  256. #define B_PCH_SPI_VTBA_JID0_VID 0x000000FF
  257. #define B_PCH_SPI_VTBA_JID0_DID0 0x0000FF00
  258. #define B_PCH_SPI_VTBA_JID0_DID1 0x00FF0000
  259. #define N_PCH_SPI_VTBA_JID0_DID0 0x08
  260. #define N_PCH_SPI_VTBA_JID0_DID1 0x10
  261. #define R_PCH_SPI_VTBA_VSCC0 0x04
  262. #define S_PCH_SPI_VTBA_VSCC0 0x04
  263. //
  264. // SPI Private Configuration Space Registers
  265. //
  266. #define R_PCH_PCR_SPI_CLK_CTL 0xC004
  267. #define R_PCH_PCR_SPI_PWR_CTL 0xC008
  268. #define R_PCH_PCR_SPI_ESPI_SOFTSTRAPS 0xC210
  269. #define B_PCH_PCR_SPI_ESPI_SOFTSTRAPS_SLAVE BIT12
  270. //
  271. // MMP0
  272. //
  273. #define R_PCH_SPI_STRP_MMP0 0xC4 ///< MMP0 Soft strap offset
  274. #define B_PCH_SPI_STRP_MMP0 0x10 ///< MMP0 Soft strap bit
  275. #define R_PCH_SPI_STRP_SFDP 0xF0 ///< PCH Soft Strap SFDP
  276. #define B_PCH_SPI_STRP_SFDP_QIORE BIT3 ///< Quad IO Read Enable
  277. #define B_PCH_SPI_STRP_SFDP_QORE BIT2 ///< Quad Output Read Enable
  278. #define B_PCH_SPI_STRP_SFDP_DIORE BIT1 ///< Dual IO Read Enable
  279. #define B_PCH_SPI_STRP_SFDP_DORE BIT0 ///< Dual Output Read Enable
  280. //
  281. // Descriptor Record 0
  282. //
  283. #define R_PCH_SPI_STRP_DSCR_0 0x00 ///< PCH Soft Strap 0
  284. #define B_PCH_SPI_STRP_DSCR_0_PTT_SUPP BIT22 ///< PTT Supported
  285. #endif