PchRegsPmc.h 46 KB

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  1. /** @file
  2. Register names for PCH PMC device
  3. Conventions:
  4. - Prefixes:
  5. Definitions beginning with "R_" are registers
  6. Definitions beginning with "B_" are bits within registers
  7. Definitions beginning with "V_" are meaningful values within the bits
  8. Definitions beginning with "S_" are register sizes
  9. Definitions beginning with "N_" are the bit position
  10. - In general, PCH registers are denoted by "_PCH_" in register names
  11. - Registers / bits that are different between PCH generations are denoted by
  12. "_PCH_[generation_name]_" in register/bit names.
  13. - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
  14. Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
  15. e.g., "_PCH_H_", "_PCH_LP_"
  16. Registers / bits names without _H_ or _LP_ apply for both H and LP.
  17. - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
  18. at the end of the register/bit names
  19. - Registers / bits of new devices introduced in a PCH generation will be just named
  20. as "_PCH_" without [generation_name] inserted.
  21. Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
  22. SPDX-License-Identifier: BSD-2-Clause-Patent
  23. **/
  24. #ifndef _PCH_REGS_PMC_H_
  25. #define _PCH_REGS_PMC_H_
  26. //
  27. // PMC Registers (D31:F2)
  28. //
  29. #define PCI_DEVICE_NUMBER_PCH_PMC 31
  30. #define PCI_FUNCTION_NUMBER_PCH_PMC 2
  31. #define R_PCH_PMC_PM_DATA_BAR 0x10
  32. #define B_PCH_PMC_PM_DATA_BAR 0xFFFFC000
  33. #define R_PCH_PMC_ACPI_BASE 0x40
  34. #define B_PCH_PMC_ACPI_BASE_BAR 0xFFFC
  35. #define R_PCH_PMC_ACPI_CNT 0x44
  36. #define B_PCH_PMC_ACPI_CNT_PWRM_EN BIT8 ///< PWRM enable
  37. #define B_PCH_PMC_ACPI_CNT_ACPI_EN BIT7 ///< ACPI eanble
  38. #define B_PCH_PMC_ACPI_CNT_SCIS (BIT2 | BIT1 | BIT0) ///< SCI IRQ select
  39. #define V_PCH_PMC_ACPI_CNT_SCIS_IRQ9 0
  40. #define V_PCH_PMC_ACPI_CNT_SCIS_IRQ10 1
  41. #define V_PCH_PMC_ACPI_CNT_SCIS_IRQ11 2
  42. #define V_PCH_PMC_ACPI_CNT_SCIS_IRQ20 4
  43. #define V_PCH_PMC_ACPI_CNT_SCIS_IRQ21 5
  44. #define V_PCH_PMC_ACPI_CNT_SCIS_IRQ22 6
  45. #define V_PCH_PMC_ACPI_CNT_SCIS_IRQ23 7
  46. #define R_PCH_PMC_PWRM_BASE 0x48
  47. #define B_PCH_PMC_PWRM_BASE_BAR 0xFFFF0000 ///< PWRM must be 64KB alignment to align the source decode.
  48. #define R_PCH_PMC_GEN_PMCON_A 0xA0
  49. #define B_PCH_PMC_GEN_PMCON_A_DC_PP_DIS BIT30
  50. #define B_PCH_PMC_GEN_PMCON_A_DSX_PP_DIS BIT29
  51. #define B_PCH_PMC_GEN_PMCON_A_AG3_PP_EN BIT28
  52. #define B_PCH_PMC_GEN_PMCON_A_SX_PP_EN BIT27
  53. #define B_PCH_PMC_GEN_PMCON_A_DISB BIT23
  54. #define B_PCH_PMC_GEN_PMCON_A_MEM_SR BIT21
  55. #define B_PCH_PMC_GEN_PMCON_A_MS4V BIT18
  56. #define B_PCH_PMC_GEN_PMCON_A_GBL_RST_STS BIT16
  57. #define B_PCH_PMC_GEN_PMCON_A_ALLOW_OPI_PLL_SD_INC0 BIT13
  58. #define B_PCH_PMC_GEN_PMCON_A_ALLOW_SPXB_CG_INC0 BIT12
  59. #define B_PCH_PMC_GEN_PMCON_A_BIOS_PCI_EXP_EN BIT10
  60. #define B_PCH_PMC_GEN_PMCON_A_PWRBTN_LVL BIT9
  61. #define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT7
  62. #define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON BIT6
  63. #define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON BIT5
  64. #define B_PCH_PMC_GEN_PMCON_A_SMI_LOCK BIT4
  65. #define B_PCH_PMC_GEN_PMCON_A_ESPI_SMI_LOCK BIT3 ///< ESPI SMI lock
  66. #define B_PCH_PMC_GEN_PMCON_A_PER_SMI_SEL 0x0003
  67. #define V_PCH_PMC_GEN_PMCON_A_PER_SMI_64S 0x0000
  68. #define V_PCH_PMC_GEN_PMCON_A_PER_SMI_32S 0x0001
  69. #define V_PCH_PMC_GEN_PMCON_A_PER_SMI_16S 0x0002
  70. #define V_PCH_PMC_GEN_PMCON_A_PER_SMI_8S 0x0003
  71. #define R_PCH_PMC_GEN_PMCON_B 0xA4
  72. #define B_PCH_PMC_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18 ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width
  73. #define B_PCH_PMC_GEN_PMCON_B_ACPI_BASE_LOCK BIT17 ///< Lock ACPI BASE at 0x40, only cleared by reset when set
  74. #define B_PCH_PMC_GEN_PMCON_B_PM_DATA_BAR_DIS BIT16
  75. #define B_PCH_PMC_GEN_PMCON_B_PME_B0_S5_DIS BIT15
  76. #define B_PCH_PMC_GEN_PMCON_B_SUS_PWR_FLR BIT14
  77. #define B_PCH_PMC_GEN_PMCON_B_WOL_EN_OVRD BIT13
  78. #define B_PCH_PMC_GEN_PMCON_B_DISABLE_SX_STRETCH BIT12
  79. #define B_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW 0xC00
  80. #define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_60US 0x000
  81. #define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_1MS 0x400
  82. #define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_50MS 0x800
  83. #define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_2S 0xC00
  84. #define B_PCH_PMC_GEN_PMCON_B_HOST_RST_STS BIT9
  85. #define B_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL 0xC0
  86. #define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_64MS 0xC0
  87. #define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_32MS 0x80
  88. #define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_16MS 0x40
  89. #define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_1_5MS 0x00
  90. #define B_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW 0x30
  91. #define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_1S 0x30
  92. #define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_2S 0x20
  93. #define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_3S 0x10
  94. #define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_4S 0x00
  95. #define B_PCH_PMC_GEN_PMCON_B_SLP_S4_ASE BIT3
  96. #define B_PCH_PMC_GEN_PMCON_B_RTC_PWR_STS BIT2
  97. #define B_PCH_PMC_GEN_PMCON_B_PWR_FLR BIT1
  98. #define B_PCH_PMC_GEN_PMCON_B_AFTERG3_EN BIT0
  99. #define R_PCH_PMC_BM_CX_CNF 0xA8
  100. #define B_PCH_PMC_BM_CX_CNF_STORAGE_BREAK_EN BIT31
  101. #define B_PCH_PMC_BM_CX_CNF_PCIE_BREAK_EN BIT30
  102. #define B_PCH_PMC_BM_CX_CNF_AZ_BREAK_EN BIT24
  103. #define B_PCH_PMC_BM_CX_CNF_DPSN_BREAK_EN BIT19
  104. #define B_PCH_PMC_BM_CX_CNF_XHCI_BREAK_EN BIT17
  105. #define B_PCH_PMC_BM_CX_CNF_SATA3_BREAK_EN BIT16
  106. #define B_PCH_PMC_BM_CX_CNF_SCRATCHPAD BIT15
  107. #define B_PCH_PMC_BM_CX_CNF_PHOLD_BM_STS_BLOCK BIT14
  108. #define B_PCH_PMC_BM_CX_CNF_MASK_CF BIT11
  109. #define B_PCH_PMC_BM_CX_CNF_BM_STS_ZERO_EN BIT10
  110. #define B_PCH_PMC_BM_CX_CNF_PM_SYNC_MSG_MODE BIT9
  111. #define R_PCH_PMC_ETR3 0xAC
  112. #define B_PCH_PMC_ETR3_CF9LOCK BIT31 ///< CF9h Lockdown
  113. #define B_PCH_PMC_ETR3_USB_CACHE_DIS BIT21
  114. #define B_PCH_PMC_ETR3_CF9GR BIT20 ///< CF9h Global Reset
  115. #define B_PCH_PMC_ETR3_SKIP_HOST_RST_HS BIT19
  116. #define B_PCH_PMC_ETR3_CWORWRE BIT18
  117. //
  118. // ACPI and legacy I/O register offsets from ACPIBASE
  119. //
  120. #define R_PCH_ACPI_PM1_STS 0x00
  121. #define S_PCH_ACPI_PM1_STS 2
  122. #define B_PCH_ACPI_PM1_STS_WAK BIT15
  123. #define B_PCH_ACPI_PM1_STS_PCIEXP_WAKE_STS BIT14
  124. #define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11
  125. #define B_PCH_ACPI_PM1_STS_RTC BIT10
  126. #define B_PCH_ACPI_PM1_STS_PWRBTN BIT8
  127. #define B_PCH_ACPI_PM1_STS_GBL BIT5
  128. #define B_PCH_ACPI_PM1_STS_BM BIT4
  129. #define B_PCH_ACPI_PM1_STS_TMROF BIT0
  130. #define N_PCH_ACPI_PM1_STS_WAK 15
  131. #define N_PCH_ACPI_PM1_STS_PCIEXP_WAKE_STS 14
  132. #define N_PCH_ACPI_PM1_STS_PRBTNOR 11
  133. #define N_PCH_ACPI_PM1_STS_RTC 10
  134. #define N_PCH_ACPI_PM1_STS_PWRBTN 8
  135. #define N_PCH_ACPI_PM1_STS_GBL 5
  136. #define N_PCH_ACPI_PM1_STS_BM 4
  137. #define N_PCH_ACPI_PM1_STS_TMROF 0
  138. #define R_PCH_ACPI_PM1_EN 0x02
  139. #define S_PCH_ACPI_PM1_EN 2
  140. #define B_PCH_ACPI_PM1_EN_PCIEXP_WAKE_DIS BIT14
  141. #define B_PCH_ACPI_PM1_EN_RTC BIT10
  142. #define B_PCH_ACPI_PM1_EN_PWRBTN BIT8
  143. #define B_PCH_ACPI_PM1_EN_GBL BIT5
  144. #define B_PCH_ACPI_PM1_EN_TMROF BIT0
  145. #define N_PCH_ACPI_PM1_EN_PCIEXP_WAKE_DIS 14
  146. #define N_PCH_ACPI_PM1_EN_RTC 10
  147. #define N_PCH_ACPI_PM1_EN_PWRBTN 8
  148. #define N_PCH_ACPI_PM1_EN_GBL 5
  149. #define N_PCH_ACPI_PM1_EN_TMROF 0
  150. #define R_PCH_ACPI_PM1_CNT 0x04
  151. #define S_PCH_ACPI_PM1_CNT 4
  152. #define B_PCH_ACPI_PM1_CNT_SLP_EN BIT13
  153. #define B_PCH_ACPI_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10)
  154. #define V_PCH_ACPI_PM1_CNT_S0 0
  155. #define V_PCH_ACPI_PM1_CNT_S1 BIT10
  156. #define V_PCH_ACPI_PM1_CNT_S3 (BIT12 | BIT10)
  157. #define V_PCH_ACPI_PM1_CNT_S4 (BIT12 | BIT11)
  158. #define V_PCH_ACPI_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
  159. #define B_PCH_ACPI_PM1_CNT_GBL_RLS BIT2
  160. #define B_PCH_ACPI_PM1_CNT_BM_RLD BIT1
  161. #define B_PCH_ACPI_PM1_CNT_SCI_EN BIT0
  162. #define R_PCH_ACPI_PM1_TMR 0x08
  163. #define V_PCH_ACPI_TMR_FREQUENCY 3579545
  164. #define B_PCH_ACPI_PM1_TMR_VAL 0xFFFFFF
  165. #define V_PCH_ACPI_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow
  166. #define R_PCH_SMI_EN 0x30
  167. #define S_PCH_SMI_EN 4
  168. #define B_PCH_SMI_EN_LEGACY_USB3 BIT31
  169. #define B_PCH_SMI_EN_GPIO_UNLOCK_SMI BIT27
  170. #define B_PCH_SMI_EN_LEGACY_USB2 BIT17
  171. #define B_PCH_SMI_EN_PERIODIC BIT14
  172. #define B_PCH_SMI_EN_TCO BIT13
  173. #define B_PCH_SMI_EN_MCSMI BIT11
  174. #define B_PCH_SMI_EN_BIOS_RLS BIT7
  175. #define B_PCH_SMI_EN_SWSMI_TMR BIT6
  176. #define B_PCH_SMI_EN_APMC BIT5
  177. #define B_PCH_SMI_EN_ON_SLP_EN BIT4
  178. #define B_PCH_SMI_EN_LEGACY_USB BIT3
  179. #define B_PCH_SMI_EN_BIOS BIT2
  180. #define B_PCH_SMI_EN_EOS BIT1
  181. #define B_PCH_SMI_EN_GBL_SMI BIT0
  182. #define N_PCH_SMI_EN_LEGACY_USB3 31
  183. #define N_PCH_SMI_EN_ESPI 28
  184. #define N_PCH_SMI_EN_GPIO_UNLOCK 27
  185. #define N_PCH_SMI_EN_INTEL_USB2 18
  186. #define N_PCH_SMI_EN_LEGACY_USB2 17
  187. #define N_PCH_SMI_EN_PERIODIC 14
  188. #define N_PCH_SMI_EN_TCO 13
  189. #define N_PCH_SMI_EN_MCSMI 11
  190. #define N_PCH_SMI_EN_BIOS_RLS 7
  191. #define N_PCH_SMI_EN_SWSMI_TMR 6
  192. #define N_PCH_SMI_EN_APMC 5
  193. #define N_PCH_SMI_EN_ON_SLP_EN 4
  194. #define N_PCH_SMI_EN_LEGACY_USB 3
  195. #define N_PCH_SMI_EN_BIOS 2
  196. #define N_PCH_SMI_EN_EOS 1
  197. #define N_PCH_SMI_EN_GBL_SMI 0
  198. #define R_PCH_SMI_STS 0x34
  199. #define S_PCH_SMI_STS 4
  200. #define B_PCH_SMI_STS_LEGACY_USB3 BIT31
  201. #define B_PCH_SMI_STS_GPIO_UNLOCK BIT27
  202. #define B_PCH_SMI_STS_SPI BIT26
  203. #define B_PCH_SMI_STS_MONITOR BIT21
  204. #define B_PCH_SMI_STS_PCI_EXP BIT20
  205. #define B_PCH_SMI_STS_PATCH BIT19
  206. #define B_PCH_SMI_STS_INTEL_USB2 BIT18
  207. #define B_PCH_SMI_STS_LEGACY_USB2 BIT17
  208. #define B_PCH_SMI_STS_SMBUS BIT16
  209. #define B_PCH_SMI_STS_SERIRQ BIT15
  210. #define B_PCH_SMI_STS_PERIODIC BIT14
  211. #define B_PCH_SMI_STS_TCO BIT13
  212. #define B_PCH_SMI_STS_DEVMON BIT12
  213. #define B_PCH_SMI_STS_MCSMI BIT11
  214. #define B_PCH_SMI_STS_GPIO_SMI BIT10
  215. #define B_PCH_SMI_STS_GPE0 BIT9
  216. #define B_PCH_SMI_STS_PM1_STS_REG BIT8
  217. #define B_PCH_SMI_STS_SWSMI_TMR BIT6
  218. #define B_PCH_SMI_STS_APM BIT5
  219. #define B_PCH_SMI_STS_ON_SLP_EN BIT4
  220. #define B_PCH_SMI_STS_LEGACY_USB BIT3
  221. #define B_PCH_SMI_STS_BIOS BIT2
  222. #define N_PCH_SMI_STS_LEGACY_USB3 31
  223. #define N_PCH_SMI_STS_ESPI 28
  224. #define N_PCH_SMI_STS_GPIO_UNLOCK 27
  225. #define N_PCH_SMI_STS_SPI 26
  226. #define N_PCH_SMI_STS_MONITOR 21
  227. #define N_PCH_SMI_STS_PCI_EXP 20
  228. #define N_PCH_SMI_STS_PATCH 19
  229. #define N_PCH_SMI_STS_INTEL_USB2 18
  230. #define N_PCH_SMI_STS_LEGACY_USB2 17
  231. #define N_PCH_SMI_STS_SMBUS 16
  232. #define N_PCH_SMI_STS_SERIRQ 15
  233. #define N_PCH_SMI_STS_PERIODIC 14
  234. #define N_PCH_SMI_STS_TCO 13
  235. #define N_PCH_SMI_STS_DEVMON 12
  236. #define N_PCH_SMI_STS_MCSMI 11
  237. #define N_PCH_SMI_STS_GPIO_SMI 10
  238. #define N_PCH_SMI_STS_GPE0 9
  239. #define N_PCH_SMI_STS_PM1_STS_REG 8
  240. #define N_PCH_SMI_STS_SWSMI_TMR 6
  241. #define N_PCH_SMI_STS_APM 5
  242. #define N_PCH_SMI_STS_ON_SLP_EN 4
  243. #define N_PCH_SMI_STS_LEGACY_USB 3
  244. #define N_PCH_SMI_STS_BIOS 2
  245. #define R_PCH_ACPI_GPE_CNTL 0x40
  246. #define B_PCH_ACPI_GPE_CNTL_SWGPE_CTRL BIT17
  247. #define R_PCH_DEVACT_STS 0x44
  248. #define S_PCH_DEVACT_STS 2
  249. #define B_PCH_DEVACT_STS_MASK 0x13E1
  250. #define B_PCH_DEVACT_STS_KBC BIT12
  251. #define B_PCH_DEVACT_STS_PIRQDH BIT9
  252. #define B_PCH_DEVACT_STS_PIRQCG BIT8
  253. #define B_PCH_DEVACT_STS_PIRQBF BIT7
  254. #define B_PCH_DEVACT_STS_PIRQAE BIT6
  255. #define B_PCH_DEVACT_STS_D0_TRP BIT0
  256. #define N_PCH_DEVACT_STS_KBC 12
  257. #define N_PCH_DEVACT_STS_PIRQDH 9
  258. #define N_PCH_DEVACT_STS_PIRQCG 8
  259. #define N_PCH_DEVACT_STS_PIRQBF 7
  260. #define N_PCH_DEVACT_STS_PIRQAE 6
  261. #define R_PCH_ACPI_PM2_CNT 0x50
  262. #define B_PCH_ACPI_PM2_CNT_ARB_DIS BIT0
  263. #define R_PCH_OC_WDT_CTL 0x54
  264. #define B_PCH_OC_WDT_CTL_RLD BIT31
  265. #define B_PCH_OC_WDT_CTL_ICCSURV_STS BIT25
  266. #define B_PCH_OC_WDT_CTL_NO_ICCSURV_STS BIT24
  267. #define B_PCH_OC_WDT_CTL_FORCE_ALL BIT15
  268. #define B_PCH_OC_WDT_CTL_EN BIT14
  269. #define B_PCH_OC_WDT_CTL_ICCSURV BIT13
  270. #define B_PCH_OC_WDT_CTL_LCK BIT12
  271. #define B_PCH_OC_WDT_CTL_TOV_MASK 0x3FF
  272. #define B_PCH_OC_WDT_CTL_FAILURE_STS BIT23
  273. #define B_PCH_OC_WDT_CTL_UNXP_RESET_STS BIT22
  274. #define B_PCH_OC_WDT_CTL_AFTER_POST 0x3F0000
  275. #define V_PCH_OC_WDT_CTL_STATUS_FAILURE 1
  276. #define V_PCH_OC_WDT_CTL_STATUS_OK 0
  277. #define R_PCH_ACPI_GPE0_STS_31_0 0x80
  278. #define R_PCH_ACPI_GPE0_STS_63_32 0x84
  279. #define R_PCH_ACPI_GPE0_STS_95_64 0x88
  280. #define R_PCH_ACPI_GPE0_STS_127_96 0x8C
  281. #define S_PCH_ACPI_GPE0_STS_127_96 4
  282. #define B_PCH_ACPI_GPE0_STS_127_96_WADT BIT18
  283. #define B_PCH_ACPI_GPE0_STS_127_96_LAN_WAKE BIT16
  284. #define B_PCH_ACPI_GPE0_STS_127_96_PME_B0 BIT13
  285. #define B_PCH_ACPI_GPE0_STS_127_96_ME_SCI BIT12
  286. #define B_PCH_ACPI_GPE0_STS_127_96_PME BIT11
  287. #define B_PCH_ACPI_GPE0_STS_127_96_BATLOW BIT10
  288. #define B_PCH_ACPI_GPE0_STS_127_96_PCI_EXP BIT9
  289. #define B_PCH_ACPI_GPE0_STS_127_96_RI BIT8
  290. #define B_PCH_ACPI_GPE0_STS_127_96_SMB_WAK BIT7
  291. #define B_PCH_ACPI_GPE0_STS_127_96_TC0SCI BIT6
  292. #define B_PCH_ACPI_GPE0_STS_127_96_SWGPE BIT2
  293. #define B_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG BIT1
  294. #define N_PCH_ACPI_GPE0_STS_127_96_PME_B0 13
  295. #define N_PCH_ACPI_GPE0_STS_127_96_PME 11
  296. #define N_PCH_ACPI_GPE0_STS_127_96_BATLOW 10
  297. #define N_PCH_ACPI_GPE0_STS_127_96_PCI_EXP 9
  298. #define N_PCH_ACPI_GPE0_STS_127_96_RI 8
  299. #define N_PCH_ACPI_GPE0_STS_127_96_SMB_WAK 7
  300. #define N_PCH_ACPI_GPE0_STS_127_96_TC0SCI 6
  301. #define N_PCH_ACPI_GPE0_STS_127_96_SWGPE 2
  302. #define N_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG 1
  303. #define R_PCH_ACPI_GPE0_EN_31_0 0x90
  304. #define R_PCH_ACPI_GPE0_EN_63_32 0x94
  305. #define R_PCH_ACPI_GPE0_EN_95_64 0x98
  306. #define R_PCH_ACPI_GPE0_EN_127_96 0x9C
  307. #define S_PCH_ACPI_GPE0_EN_127_96 4
  308. #define B_PCH_ACPI_GPE0_EN_127_96_WADT BIT18
  309. #define B_PCH_ACPI_GPE0_EN_127_96_LAN_WAKE BIT16
  310. #define B_PCH_ACPI_GPE0_EN_127_96_PME_B0 BIT13
  311. #define B_PCH_ACPI_GPE0_EN_127_96_ME_SCI BIT12
  312. #define B_PCH_ACPI_GPE0_EN_127_96_PME BIT11
  313. #define B_PCH_ACPI_GPE0_EN_127_96_BATLOW BIT10
  314. #define B_PCH_ACPI_GPE0_EN_127_96_PCI_EXP BIT9
  315. #define B_PCH_ACPI_GPE0_EN_127_96_RI BIT8
  316. #define B_PCH_ACPI_GPE0_EN_127_96_TC0SCI BIT6
  317. #define B_PCH_ACPI_GPE0_EN_127_96_SWGPE BIT2
  318. #define B_PCH_ACPI_GPE0_EN_127_96_HOT_PLUG BIT1
  319. #define N_PCH_ACPI_GPE0_EN_127_96_PME_B0 13
  320. #define N_PCH_ACPI_GPE0_EN_127_96_USB3 12
  321. #define N_PCH_ACPI_GPE0_EN_127_96_PME 11
  322. #define N_PCH_ACPI_GPE0_EN_127_96_BATLOW 10
  323. #define N_PCH_ACPI_GPE0_EN_127_96_PCI_EXP 9
  324. #define N_PCH_ACPI_GPE0_EN_127_96_RI 8
  325. #define N_PCH_ACPI_GPE0_EN_127_96_TC0SCI 6
  326. #define N_PCH_ACPI_GPE0_EN_127_96_SWGPE 2
  327. #define N_PCH_ACPI_GPE0_EN_127_96_HOT_PLUG 1
  328. //
  329. // TCO register I/O map
  330. //
  331. #define R_PCH_TCO_RLD 0x0
  332. #define R_PCH_TCO_DAT_IN 0x2
  333. #define R_PCH_TCO_DAT_OUT 0x3
  334. #define R_PCH_TCO1_STS 0x04
  335. #define S_PCH_TCO1_STS 2
  336. #define B_PCH_TCO1_STS_DMISERR BIT12
  337. #define B_PCH_TCO1_STS_DMISMI BIT10
  338. #define B_PCH_TCO1_STS_DMISCI BIT9
  339. #define B_PCH_TCO1_STS_BIOSWR BIT8
  340. #define B_PCH_TCO1_STS_NEWCENTURY BIT7
  341. #define B_PCH_TCO1_STS_TIMEOUT BIT3
  342. #define B_PCH_TCO1_STS_TCO_INT BIT2
  343. #define B_PCH_TCO1_STS_SW_TCO_SMI BIT1
  344. #define B_PCH_TCO1_STS_NMI2SMI BIT0
  345. #define N_PCH_TCO1_STS_DMISMI 10
  346. #define N_PCH_TCO1_STS_BIOSWR 8
  347. #define N_PCH_TCO1_STS_NEWCENTURY 7
  348. #define N_PCH_TCO1_STS_TIMEOUT 3
  349. #define N_PCH_TCO1_STS_SW_TCO_SMI 1
  350. #define N_PCH_TCO1_STS_NMI2SMI 0
  351. #define R_PCH_TCO2_STS 0x06
  352. #define S_PCH_TCO2_STS 2
  353. #define B_PCH_TCO2_STS_SMLINK_SLV_SMI BIT4
  354. #define B_PCH_TCO2_STS_BAD_BIOS BIT3
  355. #define B_PCH_TCO2_STS_BOOT BIT2
  356. #define B_PCH_TCO2_STS_SECOND_TO BIT1
  357. #define B_PCH_TCO2_STS_INTRD_DET BIT0
  358. #define N_PCH_TCO2_STS_INTRD_DET 0
  359. #define R_PCH_TCO1_CNT 0x08
  360. #define S_PCH_TCO1_CNT 2
  361. #define B_PCH_TCO_CNT_LOCK BIT12
  362. #define B_PCH_TCO_CNT_TMR_HLT BIT11
  363. #define B_PCH_TCO_CNT_NMI2SMI_EN BIT9
  364. #define B_PCH_TCO_CNT_NMI_NOW BIT8
  365. #define N_PCH_TCO_CNT_NMI2SMI_EN 9
  366. #define R_PCH_TCO2_CNT 0x0A
  367. #define S_PCH_TCO2_CNT 2
  368. #define B_PCH_TCO2_CNT_OS_POLICY 0x0030
  369. #define B_PCH_TCO2_CNT_GPI11_ALERT_DISABLE 0x0008
  370. #define B_PCH_TCO2_CNT_INTRD_SEL 0x0006
  371. #define N_PCH_TCO2_CNT_INTRD_SEL 2
  372. #define R_PCH_TCO_MESSAGE1 0x0C
  373. #define R_PCH_TCO_MESSAGE2 0x0D
  374. #define R_PCH_TCO_WDCNT 0x0E
  375. #define R_PCH_TCO_SW_IRQ_GEN 0x10
  376. #define B_PCH_TCO_IRQ12_CAUSE BIT1
  377. #define B_PCH_TCO_IRQ1_CAUSE BIT0
  378. #define R_PCH_TCO_TMR 0x12
  379. //
  380. // PWRM Registers
  381. //
  382. #define R_PCH_WADT_AC 0x0 ///< Wake Alarm Device Timer: AC
  383. #define R_PCH_WADT_DC 0x4 ///< Wake Alarm Device Timer: DC
  384. #define R_PCH_WADT_EXP_AC 0x8 ///< Wake Alarm Device Expired Timer: AC
  385. #define R_PCH_WADT_EXP_DC 0xC ///< Wake Alarm Device Expired Timer: DC
  386. #define R_PCH_PWRM_PRSTS 0x10 ///< Power and Reset Status
  387. #define B_PCH_PWRM_PRSTS_VE_WD_TMR_STS BIT7 ///< VE Watchdog Timer Status
  388. #define B_PCH_PWRM_PRSTS_WOL_OVR_WK_STS BIT5
  389. #define B_PCH_PWRM_PRSTS_FIELD_1 BIT4
  390. #define B_PCH_PWRM_PRSTS_ME_WAKE_STS BIT0
  391. #define R_PCH_PWRM_14 0x14
  392. #define R_PCH_PWRM_CFG 0x18 ///< Power Management Configuration
  393. #define B_PCH_PWRM_CFG_ALLOW_24_OSC_SD BIT29 ///< Allow 24MHz Crystal Oscillator Shutdown
  394. #define B_PCH_PWRM_CFG_ALLOW_USB2_CORE_PG BIT25 ///< Allow USB2 Core Power Gating
  395. #define B_PCH_PWRM_CFG_RTC_DS_WAKE_DIS BIT21 ///< RTC Wake from Deep S4/S5 Disable
  396. #define B_PCH_PWRM_CFG_SSMAW_MASK (BIT19 | BIT18) ///< SLP_SUS# Min Assertion Width
  397. #define V_PCH_PWRM_CFG_SSMAW_4S (BIT19 | BIT18) ///< 4 seconds
  398. #define V_PCH_PWRM_CFG_SSMAW_1S BIT19 ///< 1 second
  399. #define V_PCH_PWRM_CFG_SSMAW_0_5S BIT18 ///< 0.5 second (500ms)
  400. #define V_PCH_PWRM_CFG_SSMAW_0S 0 ///< 0 second
  401. #define B_PCH_PWRM_CFG_SAMAW_MASK (BIT17 | BIT16) ///< SLP_A# Min Assertion Width
  402. #define V_PCH_PWRM_CFG_SAMAW_2S (BIT17 | BIT16) ///< 2 seconds
  403. #define V_PCH_PWRM_CFG_SAMAW_98ms BIT17 ///< 98ms
  404. #define V_PCH_PWRM_CFG_SAMAW_4S BIT16 ///< 4 seconds
  405. #define V_PCH_PWRM_CFG_SAMAW_0S 0 ///< 0 second
  406. #define B_PCH_PWRM_CFG_RPCD_MASK (BIT9 | BIT8) ///< Reset Power Cycle Duration
  407. #define V_PCH_PWRM_CFG_RPCD_1S (BIT9 | BIT8) ///< 1-2 seconds
  408. #define V_PCH_PWRM_CFG_RPCD_2S BIT9 ///< 2-3 seconds
  409. #define V_PCH_PWRM_CFG_RPCD_3S BIT8 ///< 3-4 seconds
  410. #define V_PCH_PWRM_CFG_RPCD_4S 0 ///< 4-5 seconds (Default)
  411. #define R_PCH_PWRM_PCH_PM_STS 0x1C ///< Contains misc. fields used to record PCH power management events
  412. #define B_PCH_PWRM_PCH_PM_STS_PMC_MSG_FULL_STS BIT24 ///< MTPMC transport mechanism full indication
  413. #define R_PCH_PWRM_MTPMC 0x20 ///< Message to PMC
  414. #define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_0_15 0xE ///< Command to override lanes 0-15 power gating
  415. #define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_16_31 0xF ///< Command to override lanes 16-31 power gating
  416. #define B_PCH_PWRM_MTPMC_PG_CMD_DATA 0xFFFF0000 ///< Data part of PowerGate Message to PMC
  417. #define N_PCH_PWRM_MTPMC_PG_CMD_DATA 16
  418. #define R_PCH_PWRM_PCH_PM_STS2 0x24 ///< PCH Power Management Status
  419. #define R_PCH_PWRM_S3_PWRGATE_POL 0x28 ///< S3 Power Gating Policies
  420. #define B_PCH_PWRM_S3DC_GATE_SUS BIT1 ///< Deep S3 Enable in DC Mode
  421. #define B_PCH_PWRM_S3AC_GATE_SUS BIT0 ///< Deep S3 Enable in AC Mode
  422. #define R_PCH_PWRM_S4_PWRGATE_POL 0x2C ///< Deep S4 Power Policies
  423. #define B_PCH_PWRM_S4DC_GATE_SUS BIT1 ///< Deep S4 Enable in DC Mode
  424. #define B_PCH_PWRM_S4AC_GATE_SUS BIT0 ///< Deep S4 Enable in AC Mode
  425. #define R_PCH_PWRM_S5_PWRGATE_POL 0x30 ///< Deep S5 Power Policies
  426. #define B_PCH_PWRM_S5DC_GATE_SUS BIT15 ///< Deep S5 Enable in DC Mode
  427. #define B_PCH_PWRM_S5AC_GATE_SUS BIT14 ///< Deep S5 Enable in AC Mode
  428. #define R_PCH_PWRM_DSX_CFG 0x34 ///< Deep SX Configuration
  429. #define B_PCH_PWRM_DSX_CFG_WAKE_PIN_DSX_EN BIT2 ///< WAKE# Pin DeepSx Enable
  430. #define B_PCH_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS BIT1 ///< AC_PRESENT pin pulldown in DeepSx disable
  431. #define B_PCH_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 ///< LAN_WAKE Pin DeepSx Enable
  432. #define R_PCH_PWRM_CFG2 0x3C ///< Power Management Configuration Reg 2
  433. #define B_PCH_PWRM_CFG2_PBOP (BIT31 | BIT30 | BIT29) ///< Power Button Override Period (PBOP)
  434. #define N_PCH_PWRM_CFG2_PBOP 29 ///< Power Button Override Period (PBOP)
  435. #define B_PCH_PWRM_CFG2_PB_DIS BIT28 ///< Power Button Native Mode Disable (PB_DIS)
  436. #define B_PCH_PWRM_CFG2_DRAM_RESET_CTL BIT26 ///< DRAM RESET# control
  437. #define R_PCH_PWRM_EN_SN_SLOW_RING 0x48 ///< Enable Snoop Request to SLOW_RING
  438. #define R_PCH_PWRM_EN_SN_SLOW_RING2 0x4C ///< Enable Snoop Request to SLOW_RING 2nd Reg
  439. #define R_PCH_PWRM_EN_SN_SA 0x50 ///< Enable Snoop Request to SA
  440. #define R_PCH_PWRM_EN_SN_SA2 0x54 ///< Enable Snoop Request to SA 2nd Reg
  441. #define R_PCH_PWRM_EN_SN_SLOW_RING_CF 0x58 ///< Enable Snoop Request to SLOW_RING_CF
  442. #define R_PCH_PWRM_EN_NS_SA 0x68 ///< Enable Non-Snoop Request to SA
  443. #define R_PCH_PWRM_EN_CW_SLOW_RING 0x80 ///< Enable Clock Wake to SLOW_RING
  444. #define R_PCH_PWRM_EN_CW_SLOW_RING2 0x84 ///< Enable Clock Wake to SLOW_RING 2nd Reg
  445. #define R_PCH_PWRM_EN_CW_SA 0x88 ///< Enable Clock Wake to SA
  446. #define R_PCH_PWRM_EN_CW_SA2 0x8C ///< Enable Clock Wake to SA 2nd Reg
  447. #define R_PCH_PWRM_EN_CW_SLOW_RING_CF 0x98 ///< Enable Clock Wake to SLOW_RING_CF
  448. #define R_PCH_PWRM_EN_PA_SLOW_RING 0xA8 ///< Enable Pegged Active to SLOW_RING
  449. #define R_PCH_PWRM_EN_PA_SLOW_RING2 0xAC ///< Enable Pegged Active to SLOW_RING 2nd Reg
  450. #define R_PCH_PWRM_EN_PA_SA 0xB0 ///< Enable Pegged Active to SA
  451. #define R_PCH_PWRM_EN_PA_SA2 0xB4 ///< Enable Pegged Active to SA 2nd Reg
  452. #define R_PCH_PWRM_EN_MISC_EVENT 0xC0 ///< Enable Misc PM_SYNC Events
  453. #define R_PCH_PWRM_PMSYNC_TPR_CONFIG 0xC4
  454. #define B_PCH_PWRM_PMSYNC_TPR_CONFIG_LOCK BIT31
  455. #define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_EN BIT26
  456. #define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE (BIT25 | BIT24)
  457. #define N_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE 24
  458. #define V_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE_1 1
  459. #define R_PCH_PWRM_PMSYNC_MISC_CFG 0xC8
  460. #define B_PCH_PWRM_PMSYNC_PM_SYNC_LOCK BIT15 ///< PM_SYNC Configuration Lock
  461. #define B_PCH_PWRM_PMSYNC_GPIO_D_SEL BIT11
  462. #define B_PCH_PWRM_PMSYNC_GPIO_C_SEL BIT10
  463. #define R_PCH_PWRM_PM_SYNC_STATE_HYS 0xD0 ///< PM_SYNC State Hysteresis
  464. #define R_PCH_PWRM_PM_SYNC_MODE 0xD4 ///< PM_SYNC Pin Mode
  465. #define R_PCH_PWRM_CFG3 0xE0 ///< Power Management Configuration Reg 3
  466. #define B_PCH_PWRM_CFG3_DSX_WLAN_PP_EN BIT16 ///< Deep-Sx WLAN Phy Power Enable
  467. #define B_PCH_PWRM_CFG3_HOST_WLAN_PP_EN BIT17 ///< Host Wireless LAN Phy Power Enable
  468. #define B_PCH_PWRM_CFG3_PWRG_LOCK BIT2 ///< Lock power gating override messages
  469. #define R_PCH_PWRM_PM_DOWN_PPB_CFG 0xE4 ///< PM_DOWN PCH_POWER_BUDGET CONFIGURATION
  470. #define R_PCH_PWRM_CFG4 0xE8 ///< Power Management Configuration Reg 4
  471. #define B_PCH_PWRM_CFG4_U2_PHY_PG_EN BIT30 ///< USB2 PHY SUS Well Power Gating Enable
  472. #define B_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR (0x000001FF) ///< CPU I/O VR Ramp Duration, [8:0]
  473. #define N_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR 0
  474. #define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_70US 0x007
  475. #define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_240US 0x018
  476. #define R_PCH_PWRM_CPU_EPOC 0xEC
  477. #define R_PCH_PWRM_VR_MISC_CTL 0x100
  478. #define B_PCH_PWRM_VR_MISC_CTL_VIDSOVEN BIT3
  479. #define R_PCH_PWRM_GPIO_CFG 0x120
  480. #define B_PCH_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8)
  481. #define N_PCH_PWRM_GPIO_CFG_GPE0_DW2 8
  482. #define B_PCH_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 | BIT5 | BIT4)
  483. #define N_PCH_PWRM_GPIO_CFG_GPE0_DW1 4
  484. #define B_PCH_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0)
  485. #define N_PCH_PWRM_GPIO_CFG_GPE0_DW0 0
  486. #define R_PCH_PWRM_PM_SYNC_MODE_C0 0xF4 ///< PM_SYNC Pin Mode in C0
  487. #define R_PCH_PWRM_ACPI_TMR_CTL 0xFC
  488. #define B_PCH_PWRM_ACPI_TMR_DIS BIT1
  489. #define R_PCH_PWRM_124 0x124
  490. #define R_PCH_PWRM_SLP_S0_RESIDENCY_COUNTER 0x13C
  491. #define R_PCH_PWRM_MODPHY_PM_CFG1 0x200
  492. #define R_PCH_PWRM_MODPHY_PM_CFG1_MLSXSWPGP 0xFFFF
  493. #define R_PCH_PWRM_MODPHY_PM_CFG2 0x204 ///< ModPHY Power Management Configuration Reg 2
  494. #define B_PCH_PWRM_MODPHY_PM_CFG2_MLSPDDGE BIT30 ///< ModPHY Lane SUS Power Domain Dynamic Gating Enable
  495. #define B_PCH_PWRM_MODPHY_PM_CFG2_EMFC BIT29 ///< Enable ModPHY FET Control
  496. #define B_PCH_PWRM_MODPHY_PM_CFG2_EFRT (BIT28 | BIT27 | BIT26 | BIT25 | BIT24) ///< External FET Ramp Time
  497. #define N_PCH_PWRM_MODPHY_PM_CFG2_EFRT 24
  498. #define V_PCH_PWRM_MODPHY_PM_CFG2_EFRT_200US 0x0A
  499. #define B_PCH_PWRM_MODPHY_PM_CFG2_ASLOR_UFS BIT16 ///< UFS ModPHY SPD SPD Override
  500. #define R_PCH_PWRM_MODPHY_PM_CFG3 0x208 ///< ModPHY Power Management Configuration Reg 3
  501. #define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_UFS BIT16 ///< UFS ModPHY SPD RT Request
  502. #define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XDCI BIT15 ///< xDCI ModPHY SPD RT Request
  503. #define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XHCI BIT14 ///< xHCI ModPHY SPD RT Request
  504. #define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_GBE BIT13 ///< GbE ModPHY SPD RT Request
  505. #define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_SATA BIT12 ///< SATA ModPHY SPD RT Request
  506. #define R_PCH_PWRM_30C 0x30C
  507. #define R_PCH_PWRM_OBFF_CFG 0x314 ///< OBFF Configuration
  508. #define R_PCH_PWRM_31C 0x31C
  509. #define R_PCH_PWRM_CPPM_MISC_CFG 0x320 ///< CPPM Miscellaneous Configuration
  510. #define R_PCH_PWRM_CPPM_CG_POL1A 0x324 ///< CPPM Clock Gating Policy Reg 1
  511. #define R_PCH_PWRM_CPPM_CG_POL2A 0x340 ///< CPPM Clock Gating Policy Reg 3
  512. #define R_PCH_PWRM_34C 0x34C
  513. #define R_PCH_PWRM_CPPM_CG_POL3A 0x3A8 ///< CPPM Clock Gating Policy Reg 5
  514. #define B_PCH_PWRM_CPPM_CG_POLXA_CPPM_GX_QUAL BIT30 ///< CPPM Shutdown Qualifier Enable for Clock Source Group X
  515. #define B_PCH_PWRM_CPPM_CG_POLXA_LTR_GX_THRESH (0x000001FF) ///< LTR Threshold for Clock Source Group X, [8:0]
  516. #define R_PCH_PWRM_3D0 0x3D0
  517. #define R_PCH_PWRM_CPPM_MPG_POL1A 0x3E0 ///< CPPM ModPHY Gating Policy Reg 1A
  518. #define B_PCH_PWRM_CPPM_MPG_POL1A_CPPM_MODPHY_QUAL BIT30 ///< CPPM Shutdown Qualifier Enable for ModPHY
  519. #define B_PCH_PWRM_CPPM_MPG_POL1A_LT_MODPHY_SEL BIT29 ///< ASLT/PLT Selection for ModPHY
  520. #define B_PCH_PWRM_CPPM_MPG_POL1A_LTR_MODPHY_THRESH (0x000001FF) ///< LTR Threshold for ModPHY, [8:0]
  521. #define R_PCH_PWRM_CS_SD_CTL1 0x3E8 ///< Clock Source Shutdown Control Reg 1
  522. #define B_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG (BIT22 | BIT21 | BIT20) ///< Clock Source 5 Control Configuration
  523. #define N_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG 20
  524. #define B_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG (BIT2 | BIT1 | BIT0) ///< Clock Source 1 Control Configuration
  525. #define N_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG 0
  526. #define R_PCH_PWRM_CS_SD_CTL2 0x3EC ///< Clock Source Shutdown Control Reg 2
  527. #define R_PCH_PWRM_HSWPGCR1 0x5D0
  528. #define B_PCH_PWRM_SW_PG_CTRL_LOCK BIT31
  529. #define B_PCH_PWRM_DFX_SW_PG_CTRL BIT0
  530. #define R_PCH_PWRM_600 0x600
  531. #define R_PCH_PWRM_604 0x604
  532. #define R_PCH_PWRM_ST_PG_FDIS_PMC_1 0x620 ///< Static PG Related Function Disable Register 1
  533. #define B_PCH_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Static Function Disable Lock (ST_FDIS_LK)
  534. #define B_PCH_PWRM_ST_PG_FDIS_PMC_1_CAM_FDIS_PMC BIT6 ///< Camera Function Disable (PMC Version) (CAM_FDIS_PMC)
  535. #define B_PCH_PWRM_ST_PG_FDIS_PMC_1_ISH_FDIS_PMC BIT5 ///< SH Function Disable (PMC Version) (ISH_FDIS_PMC)
  536. #define B_PCH_PWRM_ST_PG_FDIS_PMC_1_GBE_FDIS_PMC BIT0 ///< GBE Function Disable (PMC Version) (GBE_FDIS_PMC)
  537. #define R_PCH_PWRM_ST_PG_FDIS_PMC_2 0x624 ///< Static Function Disable Control Register 2
  538. #define V_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_FDIS_PMC 0x7FF ///< Static Function Disable Control Register 2
  539. #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI1_FDIS_PMC BIT10 ///< SerialIo Controller GSPI Device 1 Function Disable
  540. #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI0_FDIS_PMC BIT9 ///< SerialIo Controller GSPI Device 0 Function Disable
  541. #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART2_FDIS_PMC BIT8 ///< SerialIo Controller UART Device 2 Function Disable
  542. #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART1_FDIS_PMC BIT7 ///< SerialIo Controller UART Device 1 Function Disable
  543. #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART0_FDIS_PMC BIT6 ///< SerialIo Controller UART Device 0 Function Disable
  544. #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C5_FDIS_PMC BIT5 ///< SerialIo Controller I2C Device 5 Function Disable
  545. #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C4_FDIS_PMC BIT4 ///< SerialIo Controller I2C Device 4 Function Disable
  546. #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C3_FDIS_PMC BIT3 ///< SerialIo Controller I2C Device 3 Function Disable
  547. #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C2_FDIS_PMC BIT2 ///< SerialIo Controller I2C Device 2 Function Disable
  548. #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C1_FDIS_PMC BIT1 ///< SerialIo Controller I2C Device 1 Function Disable
  549. #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C0_FDIS_PMC BIT0 ///< SerialIo Controller I2C Device 0 Function Disable
  550. #define R_PCH_PWRM_NST_PG_FDIS_1 0x628
  551. #define B_PCH_PWRM_NST_PG_FDIS_1_SCC_FDIS_PMC BIT25 ///< SCC Function Disable. This is only avaiable in B0 onward.
  552. #define B_PCH_PWRM_NST_PG_FDIS_1_XDCI_FDIS_PMC BIT24 ///< XDCI Function Disable. This is only avaiable in B0 onward.
  553. #define B_PCH_PWRM_NST_PG_FDIS_1_ADSP_FDIS_PMC BIT23 ///< ADSP Function Disable
  554. #define B_PCH_PWRM_NST_PG_FDIS_1_SATA_FDIS_PMC BIT22 ///< SATA Function Disable
  555. #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C3_FDIS_PMC BIT13 ///< PCIe Controller C Port 3 Function Disable
  556. #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C2_FDIS_PMC BIT12 ///< PCIe Controller C Port 2 Function Disable
  557. #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C1_FDIS_PMC BIT11 ///< PCIe Controller C Port 1 Function Disable
  558. #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C0_FDIS_PMC BIT10 ///< PCIe Controller C Port 0 Function Disable
  559. #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B3_FDIS_PMC BIT9 ///< PCIe Controller B Port 3 Function Disable
  560. #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B2_FDIS_PMC BIT8 ///< PCIe Controller B Port 2 Function Disable
  561. #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B1_FDIS_PMC BIT7 ///< PCIe Controller B Port 1 Function Disable
  562. #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B0_FDIS_PMC BIT6 ///< PCIe Controller B Port 0 Function Disable
  563. #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A3_FDIS_PMC BIT5 ///< PCIe Controller A Port 3 Function Disable
  564. #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A2_FDIS_PMC BIT4 ///< PCIe Controller A Port 2 Function Disable
  565. #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A1_FDIS_PMC BIT3 ///< PCIe Controller A Port 1 Function Disable
  566. #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A0_FDIS_PMC BIT2 ///< PCIe Controller A Port 0 Function Disable
  567. #define B_PCH_PWRM_NST_PG_FDIS_1_XHCI_FDIS_PMC BIT0 ///< XHCI Function Disable
  568. #define R_PCH_PWRM_FUSE_DIS_RD_1 0x640 ///< Fuse Disable Read 1 Register
  569. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E3_FUSE_DIS BIT21 ///< PCIe Controller E Port 3 Fuse Disable
  570. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E2_FUSE_DIS BIT20 ///< PCIe Controller E Port 2 Fuse Disable
  571. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E1_FUSE_DIS BIT19 ///< PCIe Controller E Port 1 Fuse Disable
  572. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E0_FUSE_DIS BIT18 ///< PCIe Controller E Port 0 Fuse Disable
  573. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D3_FUSE_DIS BIT17 ///< PCIe Controller D Port 3 Fuse Disable
  574. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D2_FUSE_DIS BIT16 ///< PCIe Controller D Port 2 Fuse Disable
  575. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D1_FUSE_DIS BIT15 ///< PCIe Controller D Port 1 Fuse Disable
  576. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D0_FUSE_DIS BIT14 ///< PCIe Controller D Port 0 Fuse Disable
  577. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C3_FUSE_DIS BIT13 ///< PCIe Controller C Port 3 Fuse Disable
  578. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C2_FUSE_DIS BIT12 ///< PCIe Controller C Port 2 Fuse Disable
  579. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C1_FUSE_DIS BIT11 ///< PCIe Controller C Port 1 Fuse Disable
  580. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C0_FUSE_DIS BIT10 ///< PCIe Controller C Port 0 Fuse Disable
  581. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B3_FUSE_DIS BIT9 ///< PCIe Controller B Port 3 Fuse Disable
  582. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B2_FUSE_DIS BIT8 ///< PCIe Controller B Port 2 Fuse Disable
  583. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B1_FUSE_DIS BIT7 ///< PCIe Controller B Port 1 Fuse Disable
  584. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B0_FUSE_DIS BIT6 ///< PCIe Controller B Port 0 Fuse Disable
  585. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A3_FUSE_DIS BIT5 ///< PCIe Controller A Port 3 Fuse Disable
  586. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A2_FUSE_DIS BIT4 ///< PCIe Controller A Port 2 Fuse Disable
  587. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A1_FUSE_DIS BIT3 ///< PCIe Controller A Port 1 Fuse Disable
  588. #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A0_FUSE_DIS BIT2 ///< PCIe Controller A Port 0 Fuse Disable
  589. #define B_PCH_PWRM_FUSE_DIS_RD_1_XHCI_FUSE_DIS BIT0 ///< XHCI Fuse Disable
  590. #define R_PCH_PWRM_FUSE_DIS_RD_2 0x644 ///< Fuse Disable Read 2 Register
  591. #define B_PCH_PWRM_FUSE_DIS_RD_2_SPC_SS_DIS BIT25 ///< SPC Fuse Disable
  592. #define B_PCH_PWRM_FUSE_DIS_RD_2_SPB_SS_DIS BIT24 ///< SPB Fuse Disable
  593. #define B_PCH_PWRM_FUSE_DIS_RD_2_SPA_SS_DIS BIT23 ///< SPA Fuse Disable
  594. #define B_PCH_PWRM_FUSE_DIS_RD_2_PSTH_FUSE_SS_DIS BIT21 ///< PSTH Fuse or Soft Strap Disable
  595. #define B_PCH_PWRM_FUSE_DIS_RD_2_DMI_FUSE_SS_DIS BIT20 ///< DMI Fuse or Soft Strap Disable
  596. #define B_PCH_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS BIT19 ///< OTG Fuse or Soft Strap Disable
  597. #define B_PCH_PWRM_FUSE_DIS_RD_2_XHCI_SS_DIS BIT18 ///< XHCI Soft Strap Disable
  598. #define B_PCH_PWRM_FUSE_DIS_RD_2_FIA_FUSE_SS_DIS BIT17 ///< FIA Fuse or Soft Strap Disable
  599. #define B_PCH_PWRM_FUSE_DIS_RD_2_DSP_FUSE_SS_DIS BIT16 ///< DSP Fuse or Soft Strap Disable
  600. #define B_PCH_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS BIT15 ///< SATA Fuse or Soft Strap Disable
  601. #define B_PCH_PWRM_FUSE_DIS_RD_2_ICC_FUSE_SS_DIS BIT14 ///< ICC Fuse or Soft Strap Disable
  602. #define B_PCH_PWRM_FUSE_DIS_RD_2_LPC_FUSE_SS_DIS BIT13 ///< LPC Fuse or Soft Strap Disable
  603. #define B_PCH_PWRM_FUSE_DIS_RD_2_RTC_FUSE_SS_DIS BIT12 ///< RTC Fuse or Soft Strap Disable
  604. #define B_PCH_PWRM_FUSE_DIS_RD_2_P2S_FUSE_SS_DIS BIT11 ///< P2S Fuse or Soft Strap Disable
  605. #define B_PCH_PWRM_FUSE_DIS_RD_2_TRSB_FUSE_SS_DIS BIT10 ///< TRSB Fuse or Soft Strap Disable
  606. #define B_PCH_PWRM_FUSE_DIS_RD_2_SMB_FUSE_SS_DIS BIT9 ///< SMB Fuse or Soft Strap Disable
  607. #define B_PCH_PWRM_FUSE_DIS_RD_2_ITSS_FUSE_SS_DIS BIT8 ///< ITSS Fuse or Soft Strap Disable
  608. #define B_PCH_PWRM_FUSE_DIS_RD_2_SERIALIO_FUSE_SS_DIS BIT6 ///< SerialIo Fuse or Soft Strap Disable
  609. #define B_PCH_PWRM_FUSE_DIS_RD_2_SCC_FUSE_SS_DIS BIT4 ///< SCC Fuse or Soft Strap Disable
  610. #define B_PCH_PWRM_FUSE_DIS_RD_2_P2D_FUSE_SS_DIS BIT3 ///< P2D Fuse or Soft Strap Disable
  611. #define B_PCH_PWRM_FUSE_DIS_RD_2_CAM_FUSE_SS_DIS BIT2 ///< Camera Fuse or Soft Strap Disable
  612. #define B_PCH_PWRM_FUSE_DIS_RD_2_ISH_FUSE_SS_DIS BIT1 ///< ISH Fuse or Soft Strap Disable
  613. #define B_PCH_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 ///< GBE Fuse or Soft Strap Disable
  614. #define R_PCH_PWRM_FUSE_DIS_RD_3 0x648 ///< Static PG Fuse and Soft Strap Disable Read Register 3
  615. #define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA3_FUSE_SS_DIS BIT3 ///< PNCRA3 Fuse or Soft Strap Disable
  616. #define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA2_FUSE_SS_DIS BIT2 ///< PNCRA2 Fuse or Soft Strap Disable
  617. #define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA1_FUSE_SS_DIS BIT1 ///< PNCRA1 Fuse or Soft Strap Disable
  618. #define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA_FUSE_SS_DIS BIT0 ///< PNCRA Fuse or Soft Strap Disable
  619. #endif