PchReservedResources.h 3.4 KB

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  1. /** @file
  2. PCH preserved MMIO resource definitions.
  3. Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _PCH_PRESERVED_RESOURCES_H_
  7. #define _PCH_PRESERVED_RESOURCES_H_
  8. /**
  9. PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF
  10. Detailed recommended static allocation
  11. +-------------------------------------------------------------------------+
  12. | Size | Start | End | Usage |
  13. | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG |
  14. | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR |
  15. | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 |
  16. | 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode |
  17. | 24 KB | 0xFE036000 | 0xFE03BFFF | Unused |
  18. | 4 KB | 0xFE03C000 | 0xFE03CFFF | Thermal Device in ACPI mode |
  19. | 524 KB | 0xFE03D000 | 0xFE0BFFFF | Unused |
  20. | 256 KB | 0xFE0C0000 | 0xFE0FFFFF | TraceHub FW BAR |
  21. | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR |
  22. | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub SW BAR |
  23. | 64 KB | 0xFE400000 | 0xFE40FFFF | CIO2 MMIO BAR in ACPI mode |
  24. | 2 MB - 64KB | 0xFE410000 | 0xFE5FFFFF | Unused |
  25. | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address |
  26. +-------------------------------------------------------------------------+
  27. **/
  28. #define PCH_PRESERVED_BASE_ADDRESS 0xFD000000 ///< Pch preserved MMIO base address
  29. #define PCH_PRESERVED_MMIO_SIZE 0x01800000 ///< 24MB
  30. #define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO base address
  31. #define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB
  32. #define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO base address
  33. #define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB
  34. #define PCH_SPI_BASE_ADDRESS 0xFED1C000 + 0x3800 ///< SPI MBAR MMIO base address
  35. #define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB
  36. #define PCH_SERIAL_IO_BASE_ADDRESS 0xFE020000 ///< SerialIo MMIO base address
  37. #define PCH_SERIAL_IO_MMIO_SIZE 0x00016000 ///< 88KB
  38. #define PCH_THERMAL_BASE_ADDRESS 0xFE03C000 ///< Thermal Device in ACPI mode
  39. #define PCH_THERMAL_MMIO_SIZE 0x00001000 ///< 4KB
  40. #define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE0C0000 ///< TraceHub FW MMIO base address
  41. #define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00040000 ///< 256KB
  42. #define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///< TraceHub MTB MMIO base address
  43. #define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB
  44. #define PCH_TRACE_HUB_SW_BASE_ADDRESS 0xFE200000 ///< TraceHub SW MMIO base address
  45. #define PCH_TRACE_HUB_SW_MMIO_SIZE 0x00200000 ///< 2MB
  46. #define PCH_CIO2_BASE_ADDRESS 0xFE400000 ///< CIO2 MMIO BAR in ACPI mode
  47. #define PCH_CIO2_MMIO_SIZE 0x00010000 ///< 64KB
  48. #define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved temp address for misc usage
  49. #define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB
  50. #define RCRB 0xFED1C000
  51. #define SPIBAR 0x3800
  52. #endif // _PCH_PRESERVED_RESOURCES_H_