PchLimits.h 3.4 KB

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  1. /** @file
  2. Build time limits of PCH resources.
  3. Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef _PCH_LIMITS_H_
  7. #define _PCH_LIMITS_H_
  8. //
  9. // PCIe limits
  10. //
  11. #define PCH_MAX_PCIE_ROOT_PORTS PCH_H_PCIE_MAX_ROOT_PORTS
  12. #define PCH_H_PCIE_MAX_ROOT_PORTS 20
  13. #define PCH_LP_PCIE_MAX_ROOT_PORTS 12
  14. #define PCH_MAX_PCIE_CONTROLLERS PCH_H_PCIE_MAX_CONTROLLERS
  15. #define PCH_PCIE_CONTROLLER_PORTS 4
  16. #define PCH_H_PCIE_MAX_CONTROLLERS (PCH_H_PCIE_MAX_ROOT_PORTS / PCH_PCIE_CONTROLLER_PORTS)
  17. #define PCH_LP_PCIE_MAX_CONTROLLERS (PCH_LP_PCIE_MAX_ROOT_PORTS / PCH_PCIE_CONTROLLER_PORTS)
  18. //
  19. // PCIe clocks limits
  20. //
  21. #define PCH_LP_PCIE_MAX_CLK_REQ 6
  22. #define PCH_H_PCIE_MAX_CLK_REQ 16
  23. //
  24. // RST PCIe Storage Cycle Router limits
  25. //
  26. #define PCH_MAX_RST_PCIE_STORAGE_CR 3
  27. //
  28. // SATA limits
  29. //
  30. #define PCH_MAX_SATA_PORTS PCH_H_AHCI_MAX_PORTS
  31. #define PCH_H_AHCI_MAX_PORTS 8 ///< Max number of sata ports in SKL PCH H
  32. #define PCH_LP_AHCI_MAX_PORTS 3 ///< Max number of sata ports in SKL PCH LP
  33. #define PCH_SATA_MAX_DEVICES_PER_PORT 1 ///< Max support device numner per port, Port Multiplier is not support.
  34. //
  35. // USB limits
  36. //
  37. #define PCH_MAX_USB2_PORTS PCH_H_XHCI_MAX_USB2_PORTS
  38. #define PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS 14 ///< Max Physical Connector XHCI, not counting virtual ports like USB-R.
  39. #define PCH_LP_XHCI_MAX_USB2_PHYSICAL_PORTS 10 ///< Max Physical Connector XHCI, not counting virtual ports like USB-R.
  40. #define PCH_H_XHCI_MAX_USB2_PORTS 16 ///< 14 High Speed lanes + Including two ports reserved for USBr
  41. #define PCH_LP_XHCI_MAX_USB2_PORTS 12 ///< 10 High Speed lanes + Including two ports reserved for USBr
  42. #define PCH_MAX_USB3_PORTS PCH_H_XHCI_MAX_USB3_PORTS
  43. #define PCH_H_XHCI_MAX_USB3_PORTS 10 ///< 10 Super Speed lanes
  44. #define PCH_LP_XHCI_MAX_USB3_PORTS 6 ///< 6 Super Speed lanes
  45. #define PCH_XHCI_MAX_SSIC_PORT_COUNT 2 ///< 2 SSIC ports in SKL PCH-LP and SKL PCH-H
  46. //
  47. // SerialIo limits
  48. //
  49. #define PCH_SERIALIO_MAX_CONTROLLERS 11 ///< Number of SerialIo controllers, this includes I2C, SPI and UART
  50. #define PCH_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I2C controllers
  51. #define PCH_LP_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I2C controllers for PCH-LP
  52. #define PCH_H_SERIALIO_MAX_I2C_CONTROLLERS 4 ///< Number of SerialIo I2C controllers for PCH-H
  53. #define PCH_SERIALIO_MAX_SPI_CONTROLLERS 2 ///< Number of SerialIo SPI controllers
  54. #define PCH_SERIALIO_MAX_UART_CONTROLLERS 3 ///< Number of SerialIo UART controllers
  55. //
  56. // ISH limits
  57. //
  58. #define PCH_ISH_MAX_GP_PINS 8
  59. #define PCH_ISH_MAX_UART_CONTROLLERS 2
  60. #define PCH_ISH_MAX_I2C_CONTROLLERS 3
  61. #define PCH_ISH_MAX_SPI_CONTROLLERS 1
  62. //
  63. // SCS limits
  64. //
  65. #define PCH_SCS_MAX_CONTROLLERS 3 ///< Number of Storage and Communication Subsystem controllers, this includes eMMC, SDIO, SDCARD
  66. //
  67. // Flash Protection Range Register
  68. //
  69. #define PCH_FLASH_PROTECTED_RANGES 5
  70. //
  71. // Number of eSPI slaves
  72. //
  73. #define PCH_ESPI_MAX_SLAVE_ID 2
  74. #endif // _PCH_LIMITS_H_