PlatformEarlyInit.c 32 KB

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  1. /** @file
  2. Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. PlatformEarlyInit.c
  6. Abstract:
  7. Do platform specific PEI stage initializations.
  8. --*/
  9. #include "PlatformEarlyInit.h"
  10. #ifdef __GNUC__
  11. #pragma GCC push_options
  12. #pragma GCC optimize ("O0")
  13. #else
  14. #pragma optimize ("", off)
  15. #endif
  16. static EFI_PEI_STALL_PPI mStallPpi = {
  17. PEI_STALL_RESOLUTION,
  18. Stall
  19. };
  20. static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi = {
  21. EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  22. &gEfiPeiStallPpiGuid,
  23. &mStallPpi
  24. };
  25. //
  26. // The reserved SMBus addresses are defined in PlatformDxe.h file.
  27. //
  28. static UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
  29. static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi = {
  30. SMBUS_BASE_ADDRESS,
  31. SMBUS_BUS_DEV_FUNC,
  32. PLATFORM_NUM_SMBUS_RSVD_ADDRESSES,
  33. mSmbusRsvdAddresses
  34. };
  35. static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi = {
  36. EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  37. &gPeiSmbusPolicyPpiGuid,
  38. &mSmbusPolicyPpi
  39. };
  40. static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi = {
  41. ProgramToneFrequency,
  42. GenerateBeepTone
  43. };
  44. static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi = {
  45. EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  46. &gPeiSpeakerInterfacePpiGuid,
  47. &mSpeakerInterfacePpi
  48. };
  49. static EFI_PEI_RESET_PPI mResetPpi = { IchReset };
  50. static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
  51. {
  52. EFI_PEI_PPI_DESCRIPTOR_PPI,
  53. &gEfiPeiMasterBootModePpiGuid,
  54. NULL
  55. },
  56. {
  57. (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
  58. &gEfiPeiResetPpiGuid,
  59. &mResetPpi
  60. }
  61. };
  62. static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
  63. {
  64. EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,
  65. &gEfiEndOfPeiSignalPpiGuid,
  66. (EFI_PEIM_NOTIFY_ENTRY_POINT)EndOfPeiPpiNotifyCallback
  67. },
  68. {
  69. (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
  70. &gEfiPeiMemoryDiscoveredPpiGuid,
  71. (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotifyCallback
  72. }
  73. };
  74. /**
  75. Parse the status registers for figuring out the wake-up event and save it into
  76. an GUID HOB which will be referenced later. However, modification is required
  77. to meet the chipset register definition and the practical hardware design. Thus,
  78. this is just an example.
  79. @param PeiServices pointer to the PEI Service Table
  80. @param EFI_SUCCESS Always return Success
  81. @retval None
  82. **/
  83. EFI_STATUS
  84. EFIAPI
  85. GetWakeupEventAndSaveToHob (
  86. IN CONST EFI_PEI_SERVICES **PeiServices
  87. )
  88. {
  89. UINT16 Pm1Sts;
  90. UINTN Gpe0Sts;
  91. UINTN WakeEventData;
  92. //
  93. // Read the ACPI registers
  94. //
  95. Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
  96. Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);
  97. //
  98. // Figure out the wake-up event
  99. //
  100. if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) {
  101. WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
  102. } else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) {
  103. WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME;
  104. } else if (Gpe0Sts != 0) {
  105. WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS;
  106. } else {
  107. WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN;
  108. }
  109. DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts));
  110. DEBUG ((EFI_D_ERROR, "ACPI Wake Event Data: %02x\n", WakeEventData));
  111. return EFI_SUCCESS;
  112. }
  113. EFI_STATUS
  114. GetSetupVariable (
  115. IN CONST EFI_PEI_SERVICES **PeiServices,
  116. IN SYSTEM_CONFIGURATION *SystemConfiguration
  117. )
  118. {
  119. UINTN VariableSize;
  120. EFI_STATUS Status;
  121. EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
  122. VariableSize = sizeof (SYSTEM_CONFIGURATION);
  123. ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
  124. Status = (*PeiServices)->LocatePpi (
  125. PeiServices,
  126. &gEfiPeiReadOnlyVariable2PpiGuid,
  127. 0,
  128. NULL,
  129. (void **)&Variable
  130. );
  131. ASSERT_EFI_ERROR (Status);
  132. //
  133. // Use normal setup default from NVRAM variable,
  134. // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
  135. //
  136. VariableSize = sizeof(SYSTEM_CONFIGURATION);
  137. Status = Variable->GetVariable (
  138. Variable,
  139. L"Setup",
  140. &gEfiSetupVariableGuid,
  141. NULL,
  142. &VariableSize,
  143. SystemConfiguration
  144. );
  145. if (EFI_ERROR (Status) || VariableSize != sizeof(SYSTEM_CONFIGURATION)) {
  146. //The setup variable is corrupted
  147. VariableSize = sizeof(SYSTEM_CONFIGURATION);
  148. Status = Variable->GetVariable(
  149. Variable,
  150. L"SetupRecovery",
  151. &gEfiSetupVariableGuid,
  152. NULL,
  153. &VariableSize,
  154. SystemConfiguration
  155. );
  156. ASSERT_EFI_ERROR (Status);
  157. }
  158. return Status;
  159. }
  160. EFI_STATUS
  161. VlvPolicyInit (
  162. IN CONST EFI_PEI_SERVICES **PeiServices,
  163. IN SYSTEM_CONFIGURATION *SystemConfiguration
  164. )
  165. {
  166. EFI_STATUS Status;
  167. EFI_PEI_PPI_DESCRIPTOR *mVlvPolicyPpiDesc;
  168. VLV_POLICY_PPI *mVlvPolicyPpi;
  169. Status = (*PeiServices)->AllocatePool(
  170. PeiServices,
  171. sizeof (EFI_PEI_PPI_DESCRIPTOR),
  172. (void **)&mVlvPolicyPpiDesc
  173. );
  174. ASSERT_EFI_ERROR (Status);
  175. Status = (*PeiServices)->AllocatePool(
  176. PeiServices,
  177. sizeof (VLV_POLICY_PPI),
  178. (void **)&mVlvPolicyPpi
  179. );
  180. ASSERT_EFI_ERROR (Status);
  181. //
  182. // Initialize PPI
  183. //
  184. (*PeiServices)->SetMem ((VOID *)mVlvPolicyPpi, sizeof (VLV_POLICY_PPI), 0);
  185. mVlvPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
  186. mVlvPolicyPpiDesc->Guid = &gVlvPolicyPpiGuid;
  187. mVlvPolicyPpiDesc->Ppi = mVlvPolicyPpi;
  188. mVlvPolicyPpi->GtConfig.PrimaryDisplay = SystemConfiguration->PrimaryVideoAdaptor;
  189. mVlvPolicyPpi->GtConfig.IgdDvmt50PreAlloc = SystemConfiguration->IgdDvmt50PreAlloc;
  190. mVlvPolicyPpi->GtConfig.ApertureSize = SystemConfiguration->IgdApertureSize;
  191. mVlvPolicyPpi->GtConfig.GttSize = SystemConfiguration->GTTSize;
  192. if (SystemConfiguration->PrimaryVideoAdaptor != 2) {
  193. mVlvPolicyPpi->GtConfig.InternalGraphics = SystemConfiguration->Igd;
  194. } else {
  195. mVlvPolicyPpi->GtConfig.InternalGraphics = 0;
  196. }
  197. mVlvPolicyPpi->GtConfig.IgdTurboEn = 1;
  198. mVlvPolicyPpi->PlatformData.FastBoot = SystemConfiguration->FastBoot;
  199. mVlvPolicyPpi->PlatformData.DynSR = 1;
  200. DEBUG ((EFI_D_ERROR, "Setup Option ISPEn: 0x%x\n", SystemConfiguration->ISPEn));
  201. mVlvPolicyPpi->ISPEn = SystemConfiguration->ISPEn;
  202. DEBUG ((EFI_D_ERROR, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration->ISPDevSel));
  203. mVlvPolicyPpi->ISPPciDevConfig = SystemConfiguration->ISPDevSel;
  204. if (SystemConfiguration->ISPEn == 0) {
  205. mVlvPolicyPpi->ISPPciDevConfig = 0;
  206. DEBUG ((EFI_D_ERROR, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi->ISPPciDevConfig));
  207. }
  208. Status = (*PeiServices)->InstallPpi(
  209. PeiServices,
  210. mVlvPolicyPpiDesc
  211. );
  212. ASSERT_EFI_ERROR (Status);
  213. return EFI_SUCCESS;
  214. }
  215. EFI_STATUS
  216. ConfigureSoCGpio (
  217. IN SYSTEM_CONFIGURATION *SystemConfiguration
  218. )
  219. {
  220. DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------start\n"));
  221. if (SystemConfiguration->eMMCBootMode== 1) {// Auto detection mode
  222. DEBUG ((EFI_D_ERROR, "Auto detection mode------------start\n"));
  223. //
  224. //Silicon Steppings
  225. //
  226. switch (PchStepping()) {
  227. case PchA0: // SOC A0 and A1
  228. case PchA1:
  229. DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));
  230. SystemConfiguration->LpsseMMCEnabled = 1;
  231. SystemConfiguration->LpsseMMC45Enabled = 0;
  232. break;
  233. case PchB0: // SOC B0 and later
  234. default:
  235. DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));
  236. SystemConfiguration->LpsseMMCEnabled = 0;
  237. SystemConfiguration->LpsseMMC45Enabled = 1;
  238. break;
  239. }
  240. } else if (SystemConfiguration->eMMCBootMode == 2) { // eMMC 4.41
  241. DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 GPIO Configuration\n"));
  242. SystemConfiguration->LpsseMMCEnabled = 1;
  243. SystemConfiguration->LpsseMMC45Enabled = 0;
  244. } else if (SystemConfiguration->eMMCBootMode == 3) { // eMMC 4.5
  245. DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 GPIO Configuration\n"));
  246. SystemConfiguration->LpsseMMCEnabled = 0;
  247. SystemConfiguration->LpsseMMC45Enabled = 1;
  248. } else { // Disable eMMC controllers
  249. DEBUG ((EFI_D_ERROR, "Disable eMMC GPIO controllers\n"));
  250. SystemConfiguration->LpsseMMCEnabled = 0;
  251. SystemConfiguration->LpsseMMC45Enabled = 0;
  252. }
  253. /*
  254. 20.1.1 EMMC
  255. SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0
  256. SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390
  257. SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0
  258. SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400
  259. SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0
  260. SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360
  261. MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380
  262. MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0
  263. MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370
  264. MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0
  265. MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330
  266. */
  267. if (SystemConfiguration->LpsseMMCEnabled== 1) {
  268. MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41
  269. MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);
  270. MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);
  271. MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);
  272. MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);
  273. MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);
  274. MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);
  275. MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);
  276. MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);
  277. MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);
  278. MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED01);
  279. }
  280. /*
  281. eMMC 4.5 controller
  282. SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0
  283. SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390
  284. SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0
  285. SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400
  286. SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0
  287. SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360
  288. MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380
  289. MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0
  290. MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370
  291. MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0
  292. MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330
  293. */
  294. if (SystemConfiguration->LpsseMMC45Enabled== 1) {
  295. MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED03); // EMMC 4.5
  296. MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC83);
  297. MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC83);
  298. MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC83);
  299. MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC83);
  300. MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC83);
  301. MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC83);
  302. MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC83);
  303. MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC83);
  304. MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC83);
  305. MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED03);
  306. }
  307. //
  308. // Change GPIOC_0 setting to allow MMIO access under Android.
  309. //
  310. IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,
  311. (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) & (UINT32)~BIT0));
  312. DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------end\n"));
  313. return EFI_SUCCESS;
  314. }
  315. EFI_STATUS
  316. MeasuredBootInit (
  317. IN CONST EFI_PEI_SERVICES **PeiServices,
  318. IN SYSTEM_CONFIGURATION *SystemConfiguration
  319. )
  320. {
  321. if (SystemConfiguration->MeasuredBootEnable) {
  322. PcdSetBool (PcdMeasuredBootEnable, TRUE);
  323. } else {
  324. PcdSetBool (PcdMeasuredBootEnable, FALSE);
  325. }
  326. return EFI_SUCCESS;
  327. }
  328. EFI_STATUS
  329. ConfigureLpssAndSccGpio (
  330. IN SYSTEM_CONFIGURATION *SystemConfiguration,
  331. IN EFI_PLATFORM_INFO_HOB *PlatformInfo
  332. )
  333. {
  334. /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:
  335. GPIO SCORE - write 0x01001002 to IOBASE + 0x0700
  336. GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00
  337. GPIO SSUS - write 0x01001002 to IOBASE + 0x1700
  338. */
  339. DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------start\n"));
  340. /*
  341. 19.1.1 PWM0
  342. PWM0 - write 0x2003CD01 to IOBASE + 0x00A0
  343. 19.1.2 PWM1
  344. PWM0 - write 0x2003CD01 to IOBASE + 0x00B0
  345. */
  346. if (SystemConfiguration->LpssPwm0Enabled== 1) {
  347. MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD01);
  348. } else if (SystemConfiguration->LpssPwm0Enabled== 0) {
  349. MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD00);
  350. }
  351. if (SystemConfiguration->LpssPwm1Enabled== 1) {
  352. MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CC01);
  353. } else if (SystemConfiguration->LpssPwm1Enabled== 0) {
  354. MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CD00);
  355. }
  356. /*
  357. 19.1.3 UART1
  358. UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020
  359. UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010
  360. UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000
  361. UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040
  362. */
  363. if (SystemConfiguration->LpssHsuart0Enabled== 1) {
  364. MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC81); // uart1
  365. MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC81);
  366. if (SystemConfiguration->LpssHsuart0FlowControlEnabled== 0) {
  367. DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[0]\n"));
  368. MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC80);
  369. MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC80);
  370. } else {
  371. DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[1]\n"));
  372. MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC81);
  373. MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81
  374. }
  375. } else if (SystemConfiguration->LpssHsuart0Enabled== 0) {
  376. MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC80); // uart1
  377. MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC80);
  378. }
  379. /*
  380. 19.1.4 UART2
  381. UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090
  382. UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080
  383. UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060
  384. UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070
  385. */
  386. if (SystemConfiguration->LpssHsuart1Enabled== 1) {
  387. MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC81);
  388. MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC81);
  389. if (SystemConfiguration->LpssHsuart1FlowControlEnabled== 0) {
  390. DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[0]\n"));
  391. MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC80); // UART2_RTS_B
  392. MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC80); // UART2_CTS_B
  393. } else {
  394. DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[1]\n"));
  395. MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC81); // uart2
  396. MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81
  397. }
  398. } else if (SystemConfiguration->LpssHsuart1Enabled== 0) {
  399. MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC80);
  400. MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC80);
  401. }
  402. /*
  403. 19.1.5 SPI
  404. SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110
  405. SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100
  406. SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130
  407. SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120
  408. */
  409. if (SystemConfiguration->LpssSpiEnabled== 1) {
  410. MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003CC81); // SPI
  411. MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003CD01);
  412. MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003CC81);
  413. MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003CC81);
  414. } else if (SystemConfiguration->LpssSpiEnabled== 0) {
  415. MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003cc80);
  416. MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003cc80);
  417. MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003cc80);
  418. MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003cc80);
  419. }
  420. /*
  421. 19.1.6 I2C0
  422. I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210
  423. I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200
  424. */
  425. if (SystemConfiguration->LpssI2C0Enabled== 1) {
  426. MmioWrite32 (IO_BASE_ADDRESS + 0x0210, 0x2003C881);
  427. MmioWrite32 (IO_BASE_ADDRESS + 0x0200, 0x2003C881);
  428. }
  429. /*
  430. 19.1.7 I2C1
  431. I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0
  432. I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0
  433. */
  434. if (SystemConfiguration->LpssI2C1Enabled== 1) {
  435. MmioWrite32 (IO_BASE_ADDRESS + 0x01F0, 0x2003C881);
  436. MmioWrite32 (IO_BASE_ADDRESS + 0x01E0, 0x2003C881);
  437. }
  438. /*
  439. 19.1.8 I2C2
  440. I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0
  441. I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0
  442. */
  443. if (SystemConfiguration->LpssI2C2Enabled== 1) {
  444. MmioWrite32 (IO_BASE_ADDRESS + 0x01D0, 0x2003C881);
  445. MmioWrite32 (IO_BASE_ADDRESS + 0x01B0, 0x2003C881);
  446. }
  447. /*
  448. 19.1.9 I2C3
  449. I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190
  450. I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0
  451. */
  452. if (SystemConfiguration->LpssI2C3Enabled== 1) {
  453. MmioWrite32 (IO_BASE_ADDRESS + 0x0190, 0x2003C881);
  454. MmioWrite32 (IO_BASE_ADDRESS + 0x01C0, 0x2003C881);
  455. }
  456. /*
  457. 19.1.10 I2C4
  458. I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0
  459. I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170
  460. */
  461. if (SystemConfiguration->LpssI2C4Enabled== 1) {
  462. MmioWrite32 (IO_BASE_ADDRESS + 0x01A0, 0x2003C881);
  463. MmioWrite32 (IO_BASE_ADDRESS + 0x0170, 0x2003C881);
  464. }
  465. /*
  466. 19.1.11 I2C5
  467. I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150
  468. I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140
  469. */
  470. //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.
  471. if (SystemConfiguration->LpssI2C5Enabled== 1) {
  472. MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C881);
  473. MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C881);
  474. } else if(SystemConfiguration->LpssI2C5Enabled== 0) {
  475. MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C880);
  476. MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C880);
  477. }
  478. /*
  479. 19.1.12 I2C6
  480. I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180
  481. I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160
  482. */
  483. if (SystemConfiguration->LpssI2C6Enabled== 1) {
  484. MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C881);
  485. MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C881);
  486. } else if (SystemConfiguration->LpssI2C6Enabled== 0) {
  487. MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C880);
  488. MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C880);
  489. }
  490. /*
  491. 20.1.2 SDIO
  492. SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320
  493. SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300
  494. SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350
  495. SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0
  496. SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340
  497. SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310
  498. */
  499. if (SystemConfiguration->LpssSdioEnabled== 1) {
  500. MmioWrite32 (IO_BASE_ADDRESS + 0x0320, 0x2003ED01);//SDIO
  501. MmioWrite32 (IO_BASE_ADDRESS + 0x0300, 0x2003EC81);
  502. MmioWrite32 (IO_BASE_ADDRESS + 0x0350, 0x2003EC81);
  503. MmioWrite32 (IO_BASE_ADDRESS + 0x02F0, 0x2003EC81);
  504. MmioWrite32 (IO_BASE_ADDRESS + 0x0340, 0x2003EC81);
  505. MmioWrite32 (IO_BASE_ADDRESS + 0x0310, 0x2003EC81);
  506. }
  507. /*
  508. 20.1.3 SD Card
  509. SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0
  510. SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0
  511. SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0
  512. SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0
  513. SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0
  514. SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290
  515. SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0
  516. SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0
  517. SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690
  518. SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160
  519. */
  520. if (SystemConfiguration->LpssSdcardEnabled == 1) {
  521. if (!((PlatformInfo->BoardId == BOARD_ID_BL_FFRD && PlatformInfo->BoardRev== PR11) && (SystemConfiguration->CfioPnpSettings == 1))) {
  522. MmioWrite32 (IO_BASE_ADDRESS + 0x05F0, 0x2003CD01);//SDCARD
  523. MmioWrite32 (IO_BASE_ADDRESS + 0x02B0, 0x2003CD01);
  524. MmioWrite32 (IO_BASE_ADDRESS + 0x02C0, 0x2003CC81);
  525. MmioWrite32 (IO_BASE_ADDRESS + 0x02E0, 0x2003CC81);
  526. MmioWrite32 (IO_BASE_ADDRESS + 0x0290, 0x2003CC81);
  527. MmioWrite32 (IO_BASE_ADDRESS + 0x02D0, 0x2003CC81);
  528. MmioWrite32 (IO_BASE_ADDRESS + 0x02A0, 0x2003CC81);
  529. MmioWrite32 (IO_BASE_ADDRESS + 0x0690, 0x2003CC81);
  530. MmioWrite32 (IO_BASE_ADDRESS + 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin
  531. }
  532. }
  533. DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------end\n"));
  534. return EFI_SUCCESS;
  535. }
  536. EFI_STATUS
  537. ConfigureLpeGpio (
  538. IN SYSTEM_CONFIGURATION *SystemConfiguration
  539. )
  540. {
  541. DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------start\n"));
  542. if (SystemConfiguration->PchAzalia == 0) {
  543. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7), (UINT32) (0x01));
  544. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7), (UINT32) (0x01));
  545. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7), (UINT32) (0x01));
  546. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7), (UINT32) (0x01));
  547. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7), (UINT32) (0x01));
  548. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7), (UINT32) (0x01));
  549. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7), (UINT32) (0x01));
  550. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7), (UINT32) (0x01));
  551. }
  552. DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------end\n"));
  553. return EFI_SUCCESS;
  554. }
  555. EFI_STATUS
  556. ConfigureSciSmiGpioRout (
  557. IN EFI_PLATFORM_INFO_HOB *PlatformInfo)
  558. {
  559. UINT32 GPI_Routing;
  560. GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT);
  561. //
  562. // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
  563. //
  564. if(PlatformInfo->BoardRev == 3) {
  565. GPI_Routing = GPI_Routing & 0xfffc3ffc;
  566. GPI_Routing = GPI_Routing | 0x00024002;
  567. }
  568. //
  569. // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
  570. //
  571. else {
  572. GPI_Routing = GPI_Routing & 0x3fff3ffc;
  573. GPI_Routing = GPI_Routing | 0x80004002;
  574. }
  575. MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT), GPI_Routing);
  576. return EFI_SUCCESS;
  577. }
  578. EFI_STATUS
  579. ConfigureMipiCsi (
  580. VOID)
  581. {
  582. //
  583. //Configure the platform clock for MIPI-CSI usage
  584. //PLT_CLK0
  585. //
  586. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7), (UINT32) (0x01));
  587. //
  588. //PLT_CLK1
  589. //
  590. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7), (UINT32) (0x01));
  591. //
  592. //PLT_CLK2
  593. //
  594. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x5B0, (UINT32)~(0x7), (UINT32) (0x01));
  595. return EFI_SUCCESS;
  596. }
  597. EFI_STATUS
  598. ConfigureUSBULPI (
  599. VOID)
  600. {
  601. //
  602. //Configure USB ULPI
  603. //USB_ULPI_0_CLK
  604. //
  605. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x338, (UINT32)~(0x7), (UINT32) (GPI));
  606. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x330, (UINT32)~(0x187), (UINT32) (0x101));
  607. //
  608. //USB_ULPI_0_DATA0
  609. //
  610. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x388, (UINT32)~(0x7), (UINT32) (GPI));
  611. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x380, (UINT32)~(0x187), (UINT32) (0x101));
  612. //
  613. //USB_ULPI_0_DATA1
  614. //
  615. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x368, (UINT32)~(0x7), (UINT32) (GPI));
  616. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x360, (UINT32)~(0x187), (UINT32) (0x101));
  617. //
  618. //USB_ULPI_0_DATA2
  619. //
  620. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x318, (UINT32)~(0x7), (UINT32) (GPI));
  621. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x310, (UINT32)~(0x187), (UINT32) (0x101));
  622. //
  623. //USB_ULPI_0_DATA3
  624. //
  625. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x378, (UINT32)~(0x7), (UINT32) (GPI));
  626. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x370, (UINT32)~(0x187), (UINT32) (0x101));
  627. //
  628. //USB_ULPI_0_DATA4
  629. //
  630. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x308, (UINT32)~(0x7), (UINT32) (GPI));
  631. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x300, (UINT32)~(0x187), (UINT32) (0x101));
  632. //
  633. //USB_ULPI_0_DATA5
  634. //
  635. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x398, (UINT32)~(0x7), (UINT32) (GPI));
  636. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x390, (UINT32)~(0x187), (UINT32) (0x101));
  637. //
  638. //USB_ULPI_0_DATA6
  639. //
  640. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x328, (UINT32)~(0x7), (UINT32) (GPI));
  641. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x320, (UINT32)~(0x187), (UINT32) (0x101));
  642. //
  643. //USB_ULPI_0_DATA7
  644. //
  645. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a8, (UINT32)~(0x7), (UINT32) (GPI));
  646. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a0, (UINT32)~(0x187), (UINT32) (0x101));
  647. //
  648. //USB_ULPI_0_DIR
  649. //
  650. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x348, (UINT32)~(0x7), (UINT32) (GPI));
  651. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x340, (UINT32)~(0x187), (UINT32) (0x81));
  652. //
  653. //USB_ULPI_0_NXT
  654. //
  655. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x358, (UINT32)~(0x7), (UINT32) (GPI));
  656. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x350, (UINT32)~(0x187), (UINT32) (0x101));
  657. //
  658. //USB_ULPI_0_STP
  659. //
  660. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b8, (UINT32)~(0x7), (UINT32) (GPI));
  661. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b0, (UINT32)~(0x187), (UINT32) (0x81));
  662. //
  663. //USB_ULPI_0_REFCLK
  664. //
  665. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x288, (UINT32)~(0x7), (UINT32) (GPI));
  666. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x280, (UINT32)~(0x187), (UINT32) (0x101));
  667. return EFI_SUCCESS;
  668. }
  669. EFI_STATUS
  670. DisableRTD3 (
  671. VOID)
  672. {
  673. //
  674. //Disable RTD3
  675. //
  676. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x210, (UINT32)~(0x0f000007), (UINT32) (0x00));
  677. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x1e0, (UINT32)~(0x0f000007), (UINT32) (0x00));
  678. return EFI_SUCCESS;
  679. }
  680. /**
  681. Platform specific initializations in stage1.
  682. @param FfsHeader Pointer to the PEIM FFS file header.
  683. @param PeiServices General purpose services available to every PEIM.
  684. @retval EFI_SUCCESS Operation completed successfully.
  685. @retval Otherwise Platform initialization failed.
  686. **/
  687. EFI_STATUS
  688. EFIAPI
  689. PlatformEarlyInitEntry (
  690. IN EFI_PEI_FILE_HANDLE FileHandle,
  691. IN CONST EFI_PEI_SERVICES **PeiServices
  692. )
  693. {
  694. EFI_STATUS Status;
  695. SYSTEM_CONFIGURATION SystemConfiguration;
  696. EFI_PLATFORM_INFO_HOB *PlatformInfo;
  697. EFI_PEI_HOB_POINTERS Hob;
  698. EFI_PLATFORM_CPU_INFO PlatformCpuInfo;
  699. //
  700. // Initialize SmbusPolicy PPI
  701. //
  702. Status = (*PeiServices)->InstallPpi(PeiServices, &mInstallSmbusPolicyPpi);
  703. ASSERT_EFI_ERROR (Status);
  704. //
  705. // Initialize Stall PPIs
  706. //
  707. Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi);
  708. ASSERT_EFI_ERROR (Status);
  709. //
  710. // Initialize platform PPIs
  711. //
  712. Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallSpeakerInterfacePpi);
  713. ASSERT_EFI_ERROR (Status);
  714. //
  715. // Variable initialization
  716. //
  717. ZeroMem(&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));
  718. //
  719. // Set the some PCI and chipset range as UC
  720. // And align to 1M at leaset
  721. //
  722. Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
  723. ASSERT (Hob.Raw != NULL);
  724. PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
  725. //
  726. // Initialize PlatformInfo HOB
  727. //
  728. MultiPlatformInfoInit(PeiServices, PlatformInfo);
  729. //
  730. // Do basic MCH init
  731. //
  732. MchInit (PeiServices);
  733. //
  734. // Set the new boot mode
  735. //
  736. Status = UpdateBootMode (PeiServices, PlatformInfo);
  737. ASSERT_EFI_ERROR (Status);
  738. SetPlatformBootMode (PeiServices, PlatformInfo);
  739. //
  740. // Get setup variable. This can only be done after BootMode is updated
  741. //
  742. GetSetupVariable (PeiServices, &SystemConfiguration);
  743. CheckOsSelection(PeiServices, &SystemConfiguration);
  744. //
  745. // Update PlatformInfo HOB according to setup variable
  746. //
  747. PlatformInfoUpdate(PeiServices, PlatformInfo, &SystemConfiguration);
  748. InitializePlatform (PeiServices, PlatformInfo, &SystemConfiguration);
  749. //
  750. // Initialize VlvPolicy PPI
  751. //
  752. Status = VlvPolicyInit (PeiServices, &SystemConfiguration);
  753. ASSERT_EFI_ERROR (Status);
  754. //
  755. // Soc specific GPIO setting
  756. //
  757. ConfigureSoCGpio(&SystemConfiguration);
  758. //
  759. // Baylake Board specific.
  760. //
  761. if (PlatformInfo->BoardId == BOARD_ID_BL_RVP ||
  762. PlatformInfo->BoardId == BOARD_ID_BL_FFRD ||
  763. PlatformInfo->BoardId == BOARD_ID_BL_FFRD8 ||
  764. PlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ||
  765. PlatformInfo->BoardId == BOARD_ID_BL_STHI ||
  766. PlatformInfo->BoardId == BOARD_ID_BB_RVP ||
  767. PlatformInfo->BoardId == BOARD_ID_BS_RVP ||
  768. PlatformInfo->BoardId == BOARD_ID_MINNOW2 ||
  769. PlatformInfo->BoardId == BOARD_ID_MINNOW2_TURBOT||
  770. PlatformInfo->BoardId == BOARD_ID_CVH) {
  771. ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo);
  772. }
  773. //
  774. // Configure LPE
  775. // Alpine Valley and Bayley Bay board specific
  776. //
  777. ConfigureLpeGpio(&SystemConfiguration);
  778. //
  779. // Bayley Bay Board specific.
  780. //
  781. ConfigureSciSmiGpioRout(PlatformInfo);
  782. if (SystemConfiguration.LpssI2C3Enabled == 1) {
  783. ConfigureMipiCsi();
  784. }
  785. //
  786. // Do basic CPU init
  787. //
  788. Status = PlatformCpuInit (PeiServices, &SystemConfiguration, &PlatformCpuInfo);
  789. //
  790. // Perform basic SSA related platform initialization
  791. //
  792. PlatformSsaInit (&SystemConfiguration,PeiServices);
  793. //
  794. // Do basic PCH init
  795. //
  796. Status = PlatformPchInit (&SystemConfiguration, PeiServices, PlatformInfo->PlatformType);
  797. ASSERT_EFI_ERROR (Status);
  798. //
  799. // Initialize platform PPIs
  800. //
  801. Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);
  802. ASSERT_EFI_ERROR (Status);
  803. if (PlatformInfo->BoardId != BOARD_ID_CVH) {
  804. InstallPlatformClocksNotify (PeiServices);
  805. InstallPlatformSysCtrlGPIONotify(PeiServices);
  806. }
  807. //
  808. // Initialize platform PPIs
  809. //
  810. Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
  811. ASSERT_EFI_ERROR (Status);
  812. //
  813. // Initialize Measured Boot
  814. //
  815. Status = MeasuredBootInit (PeiServices, &SystemConfiguration);
  816. ASSERT_EFI_ERROR (Status);
  817. return Status;
  818. }
  819. EFI_STATUS
  820. EFIAPI
  821. CpuOnlyReset (
  822. IN CONST EFI_PEI_SERVICES **PeiServices
  823. )
  824. {
  825. // MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)
  826. #ifdef __GNUC__
  827. __asm__
  828. (
  829. "xorl %ecx, %ecx\n"
  830. "1:hlt; hlt; hlt\n"
  831. "jmp 1b\n"
  832. );
  833. #else
  834. _asm {
  835. xor ecx, ecx
  836. HltLoop:
  837. hlt
  838. hlt
  839. hlt
  840. loop HltLoop
  841. }
  842. #endif
  843. //
  844. // If we get here we need to mark it as a failure.
  845. //
  846. return EFI_UNSUPPORTED;
  847. }
  848. #ifdef __GNUC__
  849. #pragma GCC pop_options
  850. #else
  851. #pragma optimize ("", on)
  852. #endif