SioInit.c 6.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127
  1. /** @file
  2. Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. SioInit.c
  6. Abstract:
  7. Functions for LpcSio initialization
  8. --*/
  9. #include "PlatformSerialPortLib.h"
  10. #include "SioInit.h"
  11. typedef struct {
  12. UINT8 Register;
  13. UINT8 Value;
  14. } EFI_SIO_TABLE;
  15. EFI_SIO_TABLE mSioTableWpcn381u[] = {
  16. {0x29, 0x0A0},
  17. {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device
  18. {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB
  19. {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
  20. {WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4
  21. {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
  22. {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device
  23. {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB
  24. {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
  25. {WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3
  26. {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
  27. {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device
  28. {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB
  29. {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
  30. {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
  31. {0x21, 0x001}, // Global Device Enable
  32. {0x26, 0x000}
  33. };
  34. EFI_SIO_TABLE mSioTableWdcp376[] = {
  35. {0x29, 0x0A0},
  36. {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device
  37. {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB
  38. {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
  39. {WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4
  40. {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
  41. {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device
  42. {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB
  43. {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
  44. {WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3
  45. {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
  46. {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device
  47. {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB
  48. {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB
  49. {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
  50. {0x21, 0x001}, // Global Device Enable
  51. {0x26, 0x000},
  52. {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K}, // Select PS2 Keyboard
  53. {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)}, // Set Base Address MSB
  54. {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)}, // Set Base Address LSB
  55. {WPCN381U_BASE2_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)}, // Set Base Address MSB
  56. {WPCN381U_BASE2_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)}, // Set Base Address LSB
  57. {WPCN381U_IRQ1_REGISTER, 0x011}, // Set to IRQ1
  58. {0xF0, (SIO_KBC_CLOCK << 6)}, // Select KBC Clock Source
  59. {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit
  60. {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M}, // Select PS2 Mouse
  61. {WPCN381U_IRQ1_REGISTER, 0x01c}, // Set to IRQ12
  62. {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE} // Enable it with Activation bit
  63. };
  64. /**
  65. Initialization for SIO.
  66. @param FfsHeader FV this PEIM was loaded from.
  67. @param PeiServices General purpose services available to every PEIM.
  68. None
  69. **/
  70. VOID
  71. InitializeSio (
  72. VOID
  73. )
  74. {
  75. UINT16 Index;
  76. UINT16 IndexPort;
  77. UINT16 DataPort;
  78. //
  79. // Super I/O initialization for Winbond WPCN381U
  80. //
  81. IndexPort = WPCN381U_CONFIG_INDEX;
  82. DataPort = WPCN381U_CONFIG_DATA;
  83. //
  84. // Check for Winbond WPCN381U
  85. //
  86. IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER); // Winbond WPCN381U Device ID register is 0x20
  87. if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) { // Winbond WPCN381U Device ID is 0xF4
  88. //
  89. // Configure WPCN381U SIO
  90. //
  91. for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {
  92. IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
  93. IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
  94. }
  95. }
  96. if (IoRead8 (DataPort) == WDCP376_CHIP_ID) { // Winbond WDCP376 Device ID is 0xF1
  97. //
  98. // Configure WDCP376 SIO
  99. //
  100. for (Index = 0; Index < sizeof (mSioTableWdcp376) / sizeof (EFI_SIO_TABLE); Index++) {
  101. IoWrite8 (IndexPort, mSioTableWdcp376[Index].Register);
  102. IoWrite8 (DataPort, mSioTableWdcp376[Index].Value);
  103. }
  104. }
  105. return;
  106. }