I2CLibPei.h 13 KB

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  1. /** @file
  2. I2C PEI Lib Instance.
  3. Copyright (c) 1999- 2015, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef I2C_PEI_REGS_H
  7. #define I2C_PEI_REGS_H
  8. #include "PiPei.h"
  9. #define R_PCH_LPC_PMC_BASE 0x44
  10. #define B_PCH_LPC_PMC_BASE_BAR 0xFFFFFE00
  11. #define R_PCH_PMC_FUNC_DIS 0x34 // Function Disable Register
  12. #define PCIEX_BASE_ADDRESS 0xE0000000
  13. #define PciD31F0RegBase PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)
  14. #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC7 BIT7 // LPSS SPI Disable
  15. #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC6 BIT6 // LPSS HSUART #2 Disable
  16. #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC5 BIT5 // LPSS HSUART #1 Disable
  17. #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC4 BIT4 // LPSS I2S Disable
  18. #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC3 BIT3 // LPSS PCM Disable
  19. #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC2 BIT2 // LPSS I2C #2 Disable
  20. #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC1 BIT1 // LPSS I2C #1 Disable
  21. #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC0 BIT0 // LPSS DMA Disable
  22. #define DEFAULT_PCI_BUS_NUMBER_PCH 0
  23. #define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command
  24. #define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA
  25. #define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA
  26. #define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List
  27. #define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status
  28. #define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable
  29. #define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable
  30. #define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable
  31. #define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable
  32. #define R_PCH_LPSS_I2C_BAR 0x10 // BAR
  33. #define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address
  34. #define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator
  35. #define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable
  36. #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
  37. #define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space
  38. #define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1
  39. #define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address
  40. #define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator
  41. #define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable
  42. #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
  43. #define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space
  44. #define NUM_RETRIES 0xFFFF
  45. //
  46. // LPIO I2C Module Memory Space Registers
  47. //
  48. #define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset
  49. #define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
  50. #define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset
  51. #define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock Parameters
  52. #define bit(a) 1 << (a)
  53. //
  54. // MMIO Register Definitions
  55. //
  56. #define I2C0_REG_SPACE_ADDR_BASE 0xFF138000 //01K
  57. #define R_IC_CON ( 0x00) // I2C Control
  58. #define B_IC_RESTART_EN BIT5
  59. #define B_IC_SLAVE_DISABLE BIT6
  60. #define V_SPEED_STANDARD 0x02
  61. #define V_SPEED_FAST 0x04
  62. #define V_SPEED_HIGH 0x06
  63. #define B_MASTER_MODE BIT0
  64. #define R_IC_TAR ( 0x04) // I2C Target Address
  65. #define IC_TAR_10BITADDR_MASTER BIT12
  66. #define R_IC_SAR ( 0x08) // I2C Slave Address
  67. #define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address
  68. #define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command
  69. #define B_READ_CMD BIT8 // 1 = read, 0 = write
  70. #define B_CMD_STOP BIT9 // 1 = STOP
  71. #define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
  72. #define V_WRITE_CMD_MASK ( 0xFF)
  73. #define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count
  74. #define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count
  75. #define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count
  76. #define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count
  77. #define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count
  78. #define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count
  79. #define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status
  80. #define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask
  81. #define I2C_INTR_GEN_CALL BIT11 // General call received
  82. #define I2C_INTR_START_DET BIT10
  83. #define I2C_INTR_STOP_DET BIT9
  84. #define I2C_INTR_ACTIVITY BIT8
  85. #define I2C_INTR_TX_ABRT BIT6 // Set on NACK
  86. #define I2C_INTR_TX_EMPTY BIT4
  87. #define I2C_INTR_TX_OVER BIT3
  88. #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
  89. #define I2C_INTR_RX_OVER BIT1
  90. #define I2C_INTR_RX_UNDER BIT0
  91. #define R_IC_RawIntrStat ( 0x34) // I2C Raw Interrupt Status
  92. #define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold
  93. #define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold
  94. #define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts
  95. #define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt
  96. #define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt
  97. #define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt
  98. #define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt
  99. #define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt
  100. #define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt
  101. #define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt
  102. #define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt
  103. #define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt
  104. #define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt
  105. #define R_IC_ENABLE ( 0x6C) // I2C Enable
  106. #define R_IC_STATUS ( 0x70) // I2C Status
  107. #define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits
  108. #define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.
  109. #define STAT_RFF BIT4 // RX FIFO is completely full
  110. #define STAT_RFNE BIT3 // RX FIFO is not empty
  111. #define STAT_TFE BIT2 // TX FIFO is completely empty
  112. #define STAT_TFNF BIT1 // TX FIFO is not full
  113. #define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register
  114. #define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register
  115. #define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register
  116. #define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register
  117. #define R_IC_DMA_CR ( 0x88) // DMA Control Register
  118. #define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level
  119. #define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level
  120. #define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register
  121. #define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register
  122. #define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register
  123. #define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register
  124. #define R_IC_COMP_VERSION ( 0xF8) // Component Version ID
  125. #define R_IC_COMP_TYPE ( 0xFC) // Component Type
  126. #define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD
  127. #define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4
  128. #define I2C_FS_SCL_HCNT_VALUE_100M 0x54
  129. #define I2C_FS_SCL_LCNT_VALUE_100M 0x9a
  130. #define I2C_HS_SCL_HCNT_VALUE_100M 0x7
  131. #define I2C_HS_SCL_LCNT_VALUE_100M 0xE
  132. //
  133. // FIFO write workaround value.
  134. //
  135. #define FIFO_WRITE_DELAY 2
  136. #define IC_TAR_10BITADDR_MASTER BIT12
  137. #define FIFO_SIZE 32
  138. #define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status
  139. #define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask
  140. #define I2C_INTR_GEN_CALL BIT11 // General call received
  141. #define I2C_INTR_START_DET BIT10
  142. #define I2C_INTR_STOP_DET BIT9
  143. #define I2C_INTR_ACTIVITY BIT8
  144. #define I2C_INTR_TX_ABRT BIT6 // Set on NACK
  145. #define I2C_INTR_TX_EMPTY BIT4
  146. #define I2C_INTR_TX_OVER BIT3
  147. #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
  148. #define I2C_INTR_RX_OVER BIT1
  149. #define I2C_INTR_RX_UNDER BIT0
  150. /**
  151. Programe all I2C controllers on LPSS.
  152. I2C0 is function 1 of LPSS. I2C1 is function 2 of LPSS, etc..
  153. @param VOID
  154. @return EFI_SUCCESS
  155. **/
  156. EFI_STATUS
  157. ProgramPciLpssI2C (
  158. VOID
  159. );
  160. /**
  161. Reads a Byte from I2C Device.
  162. @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
  163. @param SlaveAddress Device Address from which the byte value has to be read
  164. @param Offset Offset from which the data has to be read
  165. @param *Byte Address to which the value read has to be stored
  166. @param Start Whether a RESTART is issued before the byte is sent or received
  167. @param End Whether STOP is generated after a data byte is sent or received
  168. @return EFI_SUCCESS If the byte value has been successfully read
  169. @return EFI_DEVICE_ERROR Operation Failed, Device Error
  170. **/
  171. EFI_STATUS
  172. ByteReadI2CBasic(
  173. IN UINT8 I2cControllerIndex,
  174. IN UINT8 SlaveAddress,
  175. IN UINTN ReadBytes,
  176. OUT UINT8 *ReadBuffer,
  177. IN UINT8 Start,
  178. IN UINT8 End
  179. );
  180. /**
  181. Writes a Byte to I2C Device.
  182. @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
  183. @param SlaveAddress Device Address from which the byte value has to be written
  184. @param Offset Offset from which the data has to be read
  185. @param *Byte Address to which the value written is stored
  186. @param Start Whether a RESTART is issued before the byte is sent or received
  187. @param End Whether STOP is generated after a data byte is sent or received
  188. @return EFI_SUCCESS IF the byte value has been successfully written
  189. @return EFI_DEVICE_ERROR Operation Failed, Device Error
  190. **/
  191. EFI_STATUS
  192. ByteWriteI2CBasic(
  193. IN UINT8 I2cControllerIndex,
  194. IN UINT8 SlaveAddress,
  195. IN UINTN WriteBytes,
  196. IN UINT8 *WriteBuffer,
  197. IN UINT8 Start,
  198. IN UINT8 End
  199. );
  200. /**
  201. Reads a Byte from I2C Device.
  202. @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
  203. @param SlaveAddress Device Address from which the byte value has to be read
  204. @param Offset Offset from which the data has to be read
  205. @param ReadBytes Number of bytes to be read
  206. @param *ReadBuffer Address to which the value read has to be stored
  207. @return EFI_SUCCESS IF the byte value has been successfully read
  208. @return EFI_DEVICE_ERROR Operation Failed, Device Error
  209. **/
  210. EFI_STATUS
  211. ByteReadI2C(
  212. IN UINT8 I2cControllerIndex,
  213. IN UINT8 SlaveAddress,
  214. IN UINT8 Offset,
  215. IN UINTN ReadBytes,
  216. OUT UINT8 *ReadBuffer
  217. );
  218. /**
  219. Writes a Byte to I2C Device.
  220. @param I2cControllerIndex I2C Bus no to which the I2C device has been connected
  221. @param SlaveAddress Device Address from which the byte value has to be written
  222. @param Offset Offset from which the data has to be written
  223. @param WriteBytes Number of bytes to be written
  224. @param *Byte Address to which the value written is stored
  225. @return EFI_SUCCESS IF the byte value has been successfully read
  226. @return EFI_DEVICE_ERROR Operation Failed, Device Error
  227. **/
  228. EFI_STATUS
  229. ByteWriteI2C(
  230. IN UINT8 I2cControllerIndex,
  231. IN UINT8 SlaveAddress,
  232. IN UINT8 Offset,
  233. IN UINTN WriteBytes,
  234. IN UINT8 *WriteBuffer
  235. );
  236. #endif