I2CRegs.h 7.1 KB

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  1. /** @file
  2. Register Definitions for I2C Driver/PEIM.
  3. Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. --*/
  6. #ifndef I2C_REGS_H
  7. #define I2C_REGS_H
  8. //
  9. // FIFO write delay value.
  10. //
  11. #define FIFO_WRITE_DELAY 2
  12. //
  13. // MMIO Register Definitions.
  14. //
  15. #define R_IC_CON ( 0x00) // I2C Control
  16. #define B_IC_RESTART_EN BIT5
  17. #define B_IC_SLAVE_DISABLE BIT6
  18. #define V_SPEED_STANDARD 0x02
  19. #define V_SPEED_FAST 0x04
  20. #define V_SPEED_HIGH 0x06
  21. #define B_MASTER_MODE BIT0
  22. #define R_IC_TAR ( 0x04) // I2C Target Address
  23. #define IC_TAR_10BITADDR_MASTER BIT12
  24. #define R_IC_SAR ( 0x08) // I2C Slave Address
  25. #define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address
  26. #define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command
  27. #define B_READ_CMD BIT8 // 1 = read, 0 = write
  28. #define B_CMD_STOP BIT9 // 1 = STOP
  29. #define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
  30. #define V_WRITE_CMD_MASK ( 0xFF)
  31. #define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count
  32. #define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count
  33. #define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count
  34. #define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count
  35. #define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count
  36. #define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count
  37. #define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status
  38. #define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask
  39. #define I2C_INTR_GEN_CALL BIT11 // General call received
  40. #define I2C_INTR_START_DET BIT10
  41. #define I2C_INTR_STOP_DET BIT9
  42. #define I2C_INTR_ACTIVITY BIT8
  43. #define I2C_INTR_TX_ABRT BIT6 // Set on NACK
  44. #define I2C_INTR_TX_EMPTY BIT4
  45. #define I2C_INTR_TX_OVER BIT3
  46. #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
  47. #define I2C_INTR_RX_OVER BIT1
  48. #define I2C_INTR_RX_UNDER BIT0
  49. #define R_IC_RawIntrStat ( 0x34) // I2C Raw Interrupt Status
  50. #define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold
  51. #define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold
  52. #define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts
  53. #define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt
  54. #define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt
  55. #define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt
  56. #define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt
  57. #define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt
  58. #define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt
  59. #define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt
  60. #define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt
  61. #define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt
  62. #define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt
  63. #define R_IC_ENABLE ( 0x6C) // I2C Enable
  64. #define R_IC_STATUS ( 0x70) // I2C Status
  65. #define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits
  66. #define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.
  67. #define STAT_RFF BIT4 // RX FIFO is completely full
  68. #define STAT_RFNE BIT3 // RX FIFO is not empty
  69. #define STAT_TFE BIT2 // TX FIFO is completely empty
  70. #define STAT_TFNF BIT1 // TX FIFO is not full
  71. #define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register
  72. #define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register
  73. #define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register
  74. #define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register
  75. #define R_IC_DMA_CR ( 0x88) // DMA Control Register
  76. #define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level
  77. #define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level
  78. #define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register
  79. #define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register
  80. #define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register
  81. #define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register
  82. #define R_IC_COMP_VERSION ( 0xF8) // Component Version ID
  83. #define R_IC_COMP_TYPE ( 0xFC) // Component Type
  84. #define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD
  85. #define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4
  86. #define I2C_FS_SCL_HCNT_VALUE_100M 0x54
  87. #define I2C_FS_SCL_LCNT_VALUE_100M 0x9a
  88. #define I2C_HS_SCL_HCNT_VALUE_100M 0x7
  89. #define I2C_HS_SCL_LCNT_VALUE_100M 0xE
  90. #define IC_TAR_10BITADDR_MASTER BIT12
  91. #define FIFO_SIZE 32
  92. #define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status
  93. #define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask
  94. #define I2C_INTR_GEN_CALL BIT11 // General call received
  95. #define I2C_INTR_START_DET BIT10
  96. #define I2C_INTR_STOP_DET BIT9
  97. #define I2C_INTR_ACTIVITY BIT8
  98. #define I2C_INTR_TX_ABRT BIT6 // Set on NACK
  99. #define I2C_INTR_TX_EMPTY BIT4
  100. #define I2C_INTR_TX_OVER BIT3
  101. #define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
  102. #define I2C_INTR_RX_OVER BIT1
  103. #define I2C_INTR_RX_UNDER BIT0
  104. #define R_PCH_LPIO_I2C_MEM_RESETS 0x804 // Software Reset
  105. #define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
  106. #define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset
  107. #define R_PCH_LPSS_I2C_MEM_PCP 0x800 // Private Clock Parameters
  108. #endif