CoreInfoHob.c 10 KB

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  1. /**@file
  2. Build up platform processor information of SiFive U54 core.
  3. Copyright (c) 2019 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <IndustryStandard/RiscVOpensbi.h>
  7. //
  8. // The Library classes this module consumes
  9. //
  10. #include <Library/BaseMemoryLib.h>
  11. #include <Library/DebugLib.h>
  12. #include <Library/FirmwareContextProcessorSpecificLib.h>
  13. #include <Library/HobLib.h>
  14. #include <Library/PcdLib.h>
  15. #include <Library/RiscVEdk2SbiLib.h>
  16. #include <RiscVImpl.h>
  17. #include <sbi/sbi_hart.h>
  18. #include <sbi/sbi_platform.h>
  19. #include <sbi/sbi_scratch.h>
  20. /**
  21. Function to build core specific information HOB for U54 or E51 core.
  22. @param ParentProcessorGuid Parent processor of this core. ParentProcessorGuid
  23. could be the same as CoreGuid if one processor has
  24. only one core.
  25. @param ParentProcessorUid Unique ID of pysical processor which owns this core.
  26. @param HartId Hart ID of this core.
  27. @param IsBootHart TRUE means this is the boot HART.
  28. @param IsManagementCore TRUE means this is for the E51 management core, not U54
  29. @param GuidHobData Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
  30. @return EFI_SUCCESS The PEIM initialized successfully.
  31. EFI_UNSUPPORTED HART is ignored by platform.
  32. **/
  33. EFI_STATUS
  34. EFIAPI
  35. CreateU54E51CoreProcessorSpecificDataHob (
  36. IN EFI_GUID *ParentProcessorGuid,
  37. IN UINTN ParentProcessorUid,
  38. IN UINTN HartId,
  39. IN BOOLEAN IsBootHart,
  40. IN BOOLEAN IsManagementCore,
  41. OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData
  42. )
  43. {
  44. RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *CoreGuidHob;
  45. EFI_GUID *ProcessorSpecDataHobGuid;
  46. RISC_V_PROCESSOR_SPECIFIC_HOB_DATA ProcessorSpecDataHob;
  47. EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
  48. EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific;
  49. DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));
  50. if (GuidHobData == NULL) {
  51. return EFI_INVALID_PARAMETER;
  52. }
  53. ASSERT_EFI_ERROR (SbiGetFirmwareContext (&FirmwareContext));
  54. DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContext));
  55. FirmwareContextHartSpecific = FirmwareContext->HartSpecific[HartId];
  56. DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", FirmwareContextHartSpecific));
  57. if (FirmwareContextHartSpecific == NULL) {
  58. DEBUG ((DEBUG_INFO, " This hart: %d is ignored by platform.\n", HartId));
  59. return EFI_UNSUPPORTED;
  60. }
  61. //
  62. // Build up RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
  63. //
  64. CommonFirmwareContextHartSpecificInfo (
  65. FirmwareContextHartSpecific,
  66. ParentProcessorGuid,
  67. ParentProcessorUid,
  68. (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid),
  69. HartId,
  70. IsBootHart,
  71. &ProcessorSpecDataHob
  72. );
  73. ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L = TO_BE_FILLED;
  74. ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_H = TO_BE_FILLED;
  75. ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L = TO_BE_FILLED;
  76. ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_H = TO_BE_FILLED;
  77. ProcessorSpecDataHob.ProcessorSpecificData.HartXlen = RegisterLen64;
  78. ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen = RegisterLen64;
  79. ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen = RegisterLen64;
  80. if (IsManagementCore) {
  81. // Configuration for E51
  82. ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = RegisterUnsupported;
  83. } else {
  84. // Configuration for U54
  85. ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = RegisterLen64;
  86. }
  87. DebugPrintHartSpecificInfo (&ProcessorSpecDataHob);
  88. //
  89. // Build GUID HOB for core, this is for SMBIOS type 44
  90. //
  91. ProcessorSpecDataHobGuid = PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid);
  92. CoreGuidHob = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)BuildGuidDataHob (ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA));
  93. if (CoreGuidHob == NULL) {
  94. DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core.\n"));
  95. ASSERT (FALSE);
  96. }
  97. *GuidHobData = CoreGuidHob;
  98. return EFI_SUCCESS;
  99. }
  100. /**
  101. Function to build cache related SMBIOS information. RISC-V SMBIOS DXE driver collects
  102. this information and builds SMBIOS Type 7 record.
  103. The caller can adjust the allocated hob data to their needs.
  104. @param ProcessorUid Unique ID of physical processor which owns this core.
  105. @param L1CacheDataHobPtr Pointer to allocated HOB data.
  106. **/
  107. VOID
  108. EFIAPI
  109. CreateU54SmbiosType7L1DataHob (
  110. IN UINTN ProcessorUid,
  111. OUT RISC_V_PROCESSOR_TYPE7_HOB_DATA **L1CacheDataHobPtr
  112. )
  113. {
  114. EFI_GUID *GuidPtr;
  115. RISC_V_PROCESSOR_TYPE7_HOB_DATA L1CacheDataHob;
  116. //
  117. // Build up SMBIOS type 7 L1 cache record.
  118. //
  119. ZeroMem((VOID *)&L1CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
  120. L1CacheDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
  121. L1CacheDataHob.ProcessorUid = ProcessorUid;
  122. L1CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
  123. L1CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
  124. RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \
  125. RISC_V_CACHE_CONFIGURATION_ENABLED | \
  126. RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
  127. L1CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
  128. L1CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
  129. L1CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
  130. L1CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
  131. L1CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
  132. L1CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
  133. L1CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified;
  134. L1CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
  135. GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
  136. *L1CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L1CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
  137. if (L1CacheDataHobPtr == NULL) {
  138. DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5 MC Coreplex L1 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
  139. ASSERT (FALSE);
  140. }
  141. }
  142. /**
  143. Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collects
  144. this information and builds SMBIOS Type 4 record.
  145. The caller can adjust the allocated hob data to their needs.
  146. @param ProcessorUid Unique ID of physical processor which owns this core.
  147. @param ProcessorDataHobPtr Pointer to allocated HOB data.
  148. **/
  149. VOID
  150. EFIAPI
  151. CreateU54SmbiosType4DataHob (
  152. IN UINTN ProcessorUid,
  153. OUT RISC_V_PROCESSOR_TYPE4_HOB_DATA **ProcessorDataHobPtr
  154. )
  155. {
  156. EFI_GUID *GuidPtr;
  157. RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;
  158. //
  159. // Build up SMBIOS type 4 record.
  160. //
  161. ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
  162. ProcessorDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
  163. ProcessorDataHob.ProcessorUid = ProcessorUid;
  164. ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
  165. ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
  166. ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
  167. ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture = TO_BE_FILLED_BY_VENDOR;
  168. SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);
  169. ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR;
  170. ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1;
  171. ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR;
  172. ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR;
  173. ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR;
  174. ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE;
  175. ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR;
  176. ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
  177. ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
  178. ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff;
  179. ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
  180. ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
  181. ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
  182. ProcessorDataHob.SmbiosType4Processor.CoreCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
  183. ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
  184. ProcessorDataHob.SmbiosType4Processor.ThreadCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
  185. ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
  186. ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
  187. ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
  188. ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
  189. ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
  190. GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
  191. *ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
  192. if (ProcessorDataHobPtr == NULL) {
  193. DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));
  194. ASSERT (FALSE);
  195. }
  196. }